21 Commits (main)

Author SHA1 Message Date
Torsten Rasmussen c79c4ef9a8 linker: move last section id constant to c-code 2 months ago
Tom Hughes 7f0cd6692b soc: andestech: linker.ld: Handle symtab/strtab/shstrtab to fix warnings 3 months ago
Yong Cong Sin e6dd68ec89 arch: riscv: introduce `CONFIG_RISCV_GP_PURPOSE` choice 7 months ago
Yong Cong Sin ad7f3a9a0c soc: andestech: refactor out soc_early_init_hook() from pma.c 8 months ago
Yong Cong Sin 01b69e9c22 soc: andestech: run pma_init_per_core() with soc_per_core_init_hook() 8 months ago
Yong Cong Sin cc0796ab86 soc: andestech: soc_per_core_init_hook() shouldn't return value 8 months ago
Jimmy Zheng f4fe84e112 soc: andestech: ae350: support 2 PLIC instances (PLIC, PLIC-SW) 9 months ago
Jimmy Zheng da99144891 soc: andestech: linker.ld: fix incorrect padding of rom_mpu_padding 9 months ago
Yong Cong Sin 022041edba soc: riscv: andes_v5: fix PMA compilation warnings 10 months ago
Anas Nashif da118b9f24 soc: andestech: move init code from SYS_INIT to hooks 10 months ago
Marcio Ribeiro cb583995b8 arch: riscv: imply XIP config pushed to SoC level 10 months ago
Pieter De Gendt 99366dd2be linker: Add ROM_SECTIONS location 1 year ago
Mathieu Choplain 8aa6ae43ce llext: add support for SLID-based linking 1 year ago
Yong Cong Sin bbe5e1e6eb build: namespace the generated headers with `zephyr/` 1 year ago
Wei-Tai Lee 5db2590106 soc: andestech: Remove l2_cache.c 1 year ago
Wei-Tai Lee 6b26cdb7e0 soc: andestech: set default cache type 1 year ago
Wei-Tai Lee d1e2c8bea5 soc: andestech: add the definitions for cache driver 1 year ago
Jimmy Zheng f80377bd4e soc: andestech: linker.ld: clarify usage of __rom_region_end/size 1 year ago
Jimmy Zheng ed021551dc soc: andestech: linker.ld: fixed ROM padding issue 1 year ago
Jimmy Zheng abffe27edb soc: andestech: pma.c: include soc_v5.h 1 year ago
Torsten Rasmussen 8dc3f85622 hwmv2: Introduce Hardware model version 2 and convert devices 1 year ago