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Port IMX8M Quad SOC to HWMv2. Only the M4 core is enabled. Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>collab-hwm
Daniel DeGrasse
1 year ago
committed by
Jamie
21 changed files with 48 additions and 204 deletions
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# |
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# Copyright (c) 2017, NXP |
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# |
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# SPDX-License-Identifier: Apache-2.0 |
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# |
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add_subdirectory(${SOC_SERIES}) |
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# Copyright (c) 2017-2021, NXP |
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# SPDX-License-Identifier: Apache-2.0 |
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config SOC_FAMILY_IMX |
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bool |
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select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE |
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if SOC_FAMILY_IMX |
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config SOC_FAMILY |
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string |
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default "nxp_imx" |
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# Used for default value in FLASH_MCUX_FLEXSPI_XIP |
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DT_CHOSEN_Z_FLASH := zephyr,flash |
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DT_COMPAT_FLEXSPI := nxp,imx-flexspi |
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# Macros to shorten Kconfig definitions |
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DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH)) |
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DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE)) |
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source "soc/soc_legacy/arm/nxp_imx/*/Kconfig.soc" |
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config SOC_PART_NUMBER |
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default SOC_PART_NUMBER_IMX_RT5XX if SOC_SERIES_IMX_RT5XX |
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default SOC_PART_NUMBER_IMX_RT6XX if SOC_SERIES_IMX_RT6XX |
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default SOC_PART_NUMBER_IMX_RT if SOC_SERIES_IMX_RT |
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default SOC_PART_NUMBER_IMX_6X_M4 if SOC_SERIES_IMX_6X_M4 |
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default SOC_PART_NUMBER_IMX7_M4 if SOC_SERIES_IMX7_M4 |
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default SOC_PART_NUMBER_IMX8MM_M4 if SOC_SERIES_IMX8MM_M4 |
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default SOC_PART_NUMBER_IMX8ML_M7 if SOC_SERIES_IMX8ML_M7 |
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default SOC_PART_NUMBER_IMX8MQ_M4 if SOC_SERIES_IMX8MQ_M4 |
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config FLASH_MCUX_FLEXSPI_XIP |
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bool "MCUX FlexSPI flash access with xip" |
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default $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_FLEXSPI)) |
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depends on (CODE_FLEXSPI || CODE_FLEXSPI2 || SOC_SERIES_IMX_RT6XX || SOC_SERIES_IMX_RT5XX) |
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select XIP |
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help |
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Allows for the soc to safely initialize the clocks for the |
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FlexSpi when planning to execute code in FlexSpi Memory. |
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endif # SOC_FAMILY_IMX |
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# Copyright (c) 2017, NXP |
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# SPDX-License-Identifier: Apache-2.0 |
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config SERIAL_INIT_PRIORITY |
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default 55 |
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depends on SERIAL |
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source "soc/soc_legacy/arm/nxp_imx/*/Kconfig.defconfig.series" |
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# Copyright (c) 2017, NXP |
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# SPDX-License-Identifier: Apache-2.0 |
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source "soc/soc_legacy/arm/nxp_imx/*/Kconfig.series" |
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# i.MX8MQ M4 SoC series defconfig |
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# Copyright (c) 2021, Kwon Tae-young <tykwon@m2i.co.kr> |
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# SPDX-License-Identifier: Apache-2.0 |
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if SOC_SERIES_IMX8MQ_M4 |
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config SOC_SERIES |
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default "mimx8mq6_m4" |
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config NUM_IRQS |
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int |
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# must be >= the highest interrupt number used |
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default 127 |
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source "soc/soc_legacy/arm/nxp_imx/mimx8mq6_m4/Kconfig.defconfig.mimx8mq6_m4" |
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endif # SOC_SERIES_IMX8MQ_M4 |
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# i.MX8MQ M4 core series |
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# Copyright (c) 2021, Kwon Tae-young <tykwon@m2i.co.kr> |
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# SPDX-License-Identifier: Apache-2.0 |
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config SOC_SERIES_IMX8MQ_M4 |
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bool "i.MX8MQ M4 Core Series" |
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select ARM |
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select CPU_CORTEX_M4 |
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select SOC_FAMILY_IMX |
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select CPU_HAS_FPU |
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select CPU_HAS_ARM_MPU |
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help |
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Enable support for i.MX8MQ M4 MCU series |
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# i.MX8MQ M4 SoC series |
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# Copyright (c) 2021, Kwon Tae-young <tykwon@m2i.co.kr> |
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# SPDX-License-Identifier: Apache-2.0 |
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choice |
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prompt "i.MX8MQ M4 Selection" |
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depends on SOC_SERIES_IMX8MQ_M4 |
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config SOC_MIMX8MQ6 |
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bool "SOC_MIMX8MQ6" |
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select HAS_MCUX |
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select HAS_MCUX_CCM |
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select HAS_MCUX_RDC |
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select HAS_MCUX_IOMUXC |
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endchoice |
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if SOC_SERIES_IMX8MQ_M4 |
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config SOC_PART_NUMBER_MIMX8MQ6DVAJZ |
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bool |
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config SOC_PART_NUMBER_IMX8MQ_M4 |
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string |
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default "MIMX8MQ6DVAJZ" if SOC_PART_NUMBER_MIMX8MQ6DVAJZ |
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help |
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This string holds the full part number of the SoC. It is a hidden option |
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that you should not set directly. The part number selection choice defines |
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the default value for this string. |
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endif # SOC_SERIES_IMX8MQ_M4 |
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/*
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* Copyright (c) 2023, NXP |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#include <fsl_clock.h> |
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#include <fsl_flexspi.h> |
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#include <soc.h> |
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#include <errno.h> |
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#include <zephyr/irq.h> |
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#include <zephyr/dt-bindings/clock/imx_ccm_rev2.h> |
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uint32_t flexspi_clock_set_freq(uint32_t clock_name, uint32_t rate) |
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{ |
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clock_name_t root; |
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uint32_t root_rate; |
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FLEXSPI_Type *flexspi; |
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clock_root_t flexspi_clk; |
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clock_ip_name_t clk_gate; |
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uint32_t divider; |
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switch (clock_name) { |
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case IMX_CCM_FLEXSPI_CLK: |
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flexspi_clk = kCLOCK_Root_Flexspi1; |
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flexspi = (FLEXSPI_Type *)DT_REG_ADDR(DT_NODELABEL(flexspi)); |
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clk_gate = kCLOCK_Flexspi1; |
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break; |
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case IMX_CCM_FLEXSPI2_CLK: |
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flexspi_clk = kCLOCK_Root_Flexspi2; |
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flexspi = (FLEXSPI_Type *)DT_REG_ADDR(DT_NODELABEL(flexspi2)); |
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clk_gate = kCLOCK_Flexspi2; |
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break; |
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default: |
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return -ENOTSUP; |
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} |
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root = CLOCK_GetRootClockSource(flexspi_clk, |
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CLOCK_GetRootClockMux(flexspi_clk)); |
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/* Get clock root frequency */ |
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root_rate = CLOCK_GetFreq(root); |
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/* Select a divider based on root clock frequency. We round the
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* divider up, so that the resulting clock frequency is lower than |
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* requested when we can't output the exact requested frequency |
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*/ |
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divider = ((root_rate + (rate - 1)) / rate); |
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/* Cap divider to max value */ |
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divider = MIN(divider, CCM_CLOCK_ROOT_CONTROL_DIV_MASK); |
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while (FLEXSPI_GetBusIdleStatus(flexspi) == false) { |
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/* Spin */ |
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} |
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FLEXSPI_Enable(flexspi, false); |
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CLOCK_DisableClock(clk_gate); |
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CLOCK_SetRootClockDiv(flexspi_clk, divider); |
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CLOCK_EnableClock(clk_gate); |
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FLEXSPI_Enable(flexspi, true); |
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FLEXSPI_SoftwareReset(flexspi); |
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return 0; |
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} |
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