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Convert NXP iMX RT5xx SOC to hardware model V2. This core is dual architecture, so both the ARM Cortex M33 and Xtensa Fusion F1 DSP have been unified within one SOC port folder. Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>pull/69687/head
Daniel DeGrasse
1 year ago
committed by
Carles Cufi
41 changed files with 301 additions and 465 deletions
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# |
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# Copyright 2024 NXP |
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# |
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# SPDX-License-Identifier: Apache-2.0 |
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# |
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if(CONFIG_SOC_MIMXRT595S_CM33) |
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add_subdirectory(cm33) |
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elseif(CONFIG_SOC_MIMXRT595S_F1) |
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add_subdirectory(f1) |
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endif() |
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# Copyright 2024 NXP |
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# Copyright (c) 2023 Google LLC. |
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# SPDX-License-Identifier: Apache-2.0 |
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config SOC_MIMXRT595S_CM33 |
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select CPU_CORTEX_M33 |
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select CLOCK_CONTROL |
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select CPU_CORTEX_M_HAS_DWT |
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select ARM |
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select HAS_PM |
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select HAS_POWEROFF |
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select CPU_HAS_ARM_SAU |
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select CPU_HAS_ARM_MPU |
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select CPU_HAS_FPU |
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select PLATFORM_SPECIFIC_INIT |
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select ARMV8_M_DSP |
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select ARM_TRUSTZONE_M |
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select CPU_CORTEX_M_HAS_SYSTICK |
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select HAS_MCUX |
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select HAS_MCUX_SYSCON |
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select HAS_MCUX_FLEXCOMM |
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select HAS_MCUX_FLEXSPI |
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select HAS_MCUX_CACHE |
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select HAS_MCUX_LPC_DMA |
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select HAS_MCUX_LPADC |
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select HAS_MCUX_OS_TIMER |
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select HAS_MCUX_LPC_RTC |
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select HAS_MCUX_TRNG |
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select HAS_MCUX_SCTIMER |
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select HAS_MCUX_USDHC1 |
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select HAS_MCUX_USDHC2 |
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select HAS_MCUX_USB_LPCIP3511 |
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select HAS_MCUX_CTIMER |
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config SOC_MIMXRT595S_F1 |
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select XTENSA |
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select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang") |
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select XTENSA_RESET_VECTOR |
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select XTENSA_USE_CORE_CRT1 |
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if SOC_SERIES_IMXRT5XX |
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if NXP_IMXRT_BOOT_HEADER |
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config IMAGE_VECTOR_TABLE_OFFSET |
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default 0x1000 |
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endif # NXP_IMXRT_BOOT_HEADER |
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config IMXRT5XX_CODE_CACHE |
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bool "Code cache" |
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default y |
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help |
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Enable code cache for FlexSPI region at boot. If this Kconfig is |
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cleared, the CACHE64 controller will be disabled during SOC init |
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choice FLEXCOMM0_CLK_SRC |
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prompt "Clock source for Flexcomm0" |
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default FLEXCOMM0_CLK_SRC_FRG |
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config FLEXCOMM0_CLK_SRC_FRG |
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bool "FRG is source of Flexcomm0 clock" |
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config FLEXCOMM0_CLK_SRC_FRO |
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bool "FRO_DIV4 is source of Flexcomm0 clock" |
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endchoice |
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choice MIPI_DPHY_CLK_SRC |
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prompt "Clock source for MIPI DPHY" |
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default MIPI_DPHY_CLK_SRC_AUX1_PLL |
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config MIPI_DPHY_CLK_SRC_AUX1_PLL |
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bool "AUX1_PLL is source of MIPI_DPHY clock" |
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config MIPI_DPHY_CLK_SRC_FRO |
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bool "FRO 192/96M is source of MIPI_DPHY clock" |
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endchoice |
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config MCUX_CORE_SUFFIX |
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default "_cm33" if SOC_MIMXRT595S_CM33 |
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default "_dsp" if SOC_MIMXRT595S_F1 |
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endif # SOC_SERIES_IMXRT5XX |
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# Copyright 2024 NXP |
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# SPDX-License-Identifier: Apache-2.0 |
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if SOC_MIMXRT595S_CM33 |
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config ROM_START_OFFSET |
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default 0x1200 if NXP_IMXRT_BOOT_HEADER |
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# The PVT Sensor uses IRQ #75. For more details, see |
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# https://www.nxp.com/design/design-center/software/embedded-software/application-software-packs/application-software-pack-dynamic-voltage-scaling-using-pvt-sensor:APP-SW-PACK-DVS-PVT-SENSOR |
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config NUM_IRQS |
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default 76 |
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config ZTEST_NO_YIELD |
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default y if (PM && ZTEST) |
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# Code relocation is needed for flash clock setup |
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config CODE_DATA_RELOCATION_SRAM |
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default y |
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# |
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# MBEDTLS is larger but much faster than TinyCrypt so choose wisely |
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# |
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config MBEDTLS |
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#config TINYCRYPT |
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default y if CSPRNG_ENABLED |
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depends on ENTROPY_GENERATOR |
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if MBEDTLS |
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# |
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# MBEDTLS CTR_DRBG code path needs extra stack space for initialization than |
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# what the ztest_thread_stack defaults to. |
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# |
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config TEST_EXTRA_STACK_SIZE |
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int |
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default 1024 |
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endif # MBEDTLS |
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if MCUX_OS_TIMER |
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config SYS_CLOCK_HW_CYCLES_PER_SEC |
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default 1000000 |
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endif # MCUX_OS_TIMER |
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if CORTEX_M_SYSTICK |
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config SYS_CLOCK_HW_CYCLES_PER_SEC |
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default 250105263 |
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endif # CORTEX_M_SYSTICK |
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choice USB_MCUX_CONTROLLER_TYPE |
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default USB_DC_NXP_LPCIP3511 |
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endchoice |
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if PM_DEVICE |
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# Enable the MEMC FlexSPI driver when using device power |
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# management so we can reconfigure the FlexSPI pins to |
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# save power. The MEMC FlexSPI driver is enabled when we |
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# enable the Flash subsystem, however we would like to |
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# reconfigure the FlexSPI pins even when the Flash driver |
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# is disabled, hence MEMC is selected when PM_DEVICE |
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# is turned on. |
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config MEMC |
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default y |
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select MEMC_MCUX_FLEXSPI |
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endif |
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endif # SOC_MIMXRT595S_CM33 |
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if SOC_MIMXRT595S_F1 |
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config SMP |
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default n |
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config XTENSA_TIMER |
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default y |
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config KERNEL_ENTRY |
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default "__start" |
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config MULTI_LEVEL_INTERRUPTS |
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default n |
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config 2ND_LEVEL_INTERRUPTS |
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default n |
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# To prevent test uses TEST_LOGGING_MINIMAL |
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config TEST_LOGGING_DEFAULTS |
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default n |
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depends on TEST |
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config SYS_CLOCK_HW_CYCLES_PER_SEC |
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default 198000000 |
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config XTENSA_CCOUNT_HZ |
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default SYS_CLOCK_HW_CYCLES_PER_SEC |
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config SYS_CLOCK_TICKS_PER_SEC |
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default 1000 |
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config DYNAMIC_INTERRUPTS |
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default n |
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config CACHE |
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default n |
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config DCACHE |
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default n |
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config CACHE_MANAGEMENT |
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default n |
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config LOG |
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default n |
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endif # SOC_MIMXRT595S_F1 |
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# i.MX RT5XX Series |
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# Copyright 2022-2024, NXP |
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# SPDX-License-Identifier: Apache-2.0 |
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config SOC_SERIES_IMXRT5XX |
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bool |
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select SOC_FAMILY_NXP_IMXRT |
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config SOC_MIMXRT595S |
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bool |
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select SOC_SERIES_IMXRT5XX |
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config SOC_MIMXRT595S_CM33 |
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bool |
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select SOC_MIMXRT595S |
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help |
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NXP RT5xx CM33 core |
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config SOC_MIMXRT595S_F1 |
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bool |
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select SOC_MIMXRT595S |
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help |
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NXP RT5xx ADSP Series |
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config SOC_SERIES |
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default "imxrt5xx" if SOC_SERIES_IMXRT5XX |
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config SOC |
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default "mimxrt595s" if SOC_MIMXRT595S |
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config SOC_TOOLCHAIN_NAME |
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string |
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default "nxp_rt500_adsp" if SOC_MIMXRT595S_F1 |
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config SOC_PART_NUMBER_MIMXRT533SFFOC |
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bool |
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config SOC_PART_NUMBER_MIMXRT555SFFOC |
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bool |
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config SOC_PART_NUMBER_MIMXRT595SFFOC |
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bool |
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config SOC_PART_NUMBER_MIMXRT533SFAWC |
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bool |
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config SOC_PART_NUMBER_MIMXRT555SFAWC |
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bool |
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config SOC_PART_NUMBER_MIMXRT595SFAWC |
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bool |
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config SOC_PART_NUMBER |
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default "MIMXRT533SFAWC" if SOC_PART_NUMBER_MIMXRT533SFAWC |
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default "MIMXRT555SFAWC" if SOC_PART_NUMBER_MIMXRT555SFAWC |
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default "MIMXRT595SFAWC" if SOC_PART_NUMBER_MIMXRT595SFAWC |
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default "MIMXRT533SFFOC" if SOC_PART_NUMBER_MIMXRT533SFFOC |
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default "MIMXRT555SFFOC" if SOC_PART_NUMBER_MIMXRT555SFFOC |
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default "MIMXRT595SFFOC" if SOC_PART_NUMBER_MIMXRT595SFFOC |
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# NXP MIMXRT5XX platform configuration options |
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# Copyright (c) 2022, NXP |
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# SPDX-License-Identifier: Apache-2.0 |
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if SOC_MIMXRT595S_CM33 |
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config SOC |
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default "mimxrt595s_cm33" |
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if MCUX_OS_TIMER |
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config SYS_CLOCK_HW_CYCLES_PER_SEC |
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default 1000000 |
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endif # MCUX_OS_TIMER |
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if CORTEX_M_SYSTICK |
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config SYS_CLOCK_HW_CYCLES_PER_SEC |
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default 250105263 |
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endif # CORTEX_M_SYSTICK |
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choice USB_MCUX_CONTROLLER_TYPE |
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default USB_DC_NXP_LPCIP3511 |
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endchoice |
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# Enable the MEMC FlexSPI driver when using device power |
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# management so we can reconfigure the FlexSPI pins to |
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# save power. The MEMC FlexSPI driver is enabled when we |
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# enable the Flash subsystem, however we would like to |
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# reconfigure the FlexSPI pins even when the Flash driver |
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# is disabled, hence MEMC is selected when PM_DEVICE |
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# is turned on. |
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config MEMC |
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default y if PM_DEVICE |
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select MEMC_MCUX_FLEXSPI |
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endif # SOC_MIMXRT685S_CM33 |
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# i.MX RT5XX series configuration options |
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# Copyright (c) 2022-2024, NXP |
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# SPDX-License-Identifier: Apache-2.0 |
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if SOC_SERIES_IMX_RT5XX |
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config SOC_SERIES |
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default "rt5xx" |
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config ROM_START_OFFSET |
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default 0x1200 if NXP_IMX_RT5XX_BOOT_HEADER |
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# The PVT Sensor uses IRQ #75. For more details, see |
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# https://www.nxp.com/design/design-center/software/embedded-software/application-software-packs/application-software-pack-dynamic-voltage-scaling-using-pvt-sensor:APP-SW-PACK-DVS-PVT-SENSOR |
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config NUM_IRQS |
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default 76 |
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config ZTEST_NO_YIELD |
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default y if (PM && ZTEST) |
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# The base address is determined from the zephyr,flash node with the following |
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# precedence: |
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# FlexSPI base address (if flash node is on a FlexSPI bus) |
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# node reg property (used for memory regions such as SRAM) |
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# Workaround for not being able to have commas in macro arguments |
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DT_CHOSEN_Z_FLASH := zephyr,flash |
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DT_COMPAT_FLEXSPI := nxp,imx-flexspi |
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# Macros to shorten Kconfig definitions |
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DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH)) |
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DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE)) |
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config FLASH_BASE_ADDRESS |
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default $(dt_node_reg_addr_hex,$(DT_CHOSEN_FLASH_PARENT),1) \ |
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if $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_FLEXSPI)) |
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default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) |
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# The RT5xx has no internal flash. If the flash node has a size property, |
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# use that over the reg property. This is used for the external flash |
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# present on the board. Otherwise, fallback to the reg property |
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config FLASH_SIZE |
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default $(dt_node_int_prop_int,$(DT_CHOSEN_FLASH_NODE),size,Kb) \ |
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if $(dt_node_has_prop,$(DT_CHOSEN_FLASH_NODE),size) |
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default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) |
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if FLASH_MCUX_FLEXSPI_XIP |
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# Avoid RWW hazards by defaulting logging to disabled |
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choice FLASH_LOG_LEVEL_CHOICE |
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default FLASH_LOG_LEVEL_OFF |
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endchoice |
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choice MEMC_LOG_LEVEL_CHOICE |
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default MEMC_LOG_LEVEL_OFF |
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endchoice |
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endif |
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# |
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# MBEDTLS is larger but much faster than TinyCrypt so choose wisely |
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# |
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config MBEDTLS |
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#config TINYCRYPT |
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default y if CSPRNG_ENABLED |
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depends on ENTROPY_GENERATOR |
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if MBEDTLS |
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# |
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# MBEDTLS CTR_DRBG code path needs extra stack space for initialization than |
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# what the ztest_thread_stack defaults to. |
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# |
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config TEST_EXTRA_STACK_SIZE |
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int |
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default 1024 |
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endif # MBEDTLS |
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source "soc/soc_legacy/arm/nxp_imx/rt5xx/Kconfig.defconfig.mimxrt5*" |
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endif # SOC_SERIES_MIMXRT5XX |
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@@ -1,16 +0,0 @@
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# i.MX RT5XX Series |
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# Copyright (c) 2022, NXP |
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# SPDX-License-Identifier: Apache-2.0 |
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config SOC_SERIES_IMX_RT5XX |
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bool "i.MX RT5XX Series Family MCU" |
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select ARM |
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select CPU_CORTEX_M33 |
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select CPU_CORTEX_M_HAS_DWT |
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select SOC_FAMILY_IMX |
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select CLOCK_CONTROL |
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select HAS_PM |
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select HAS_POWEROFF |
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help |
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Enable support for i.MX RT5XX Series MCU series |
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@@ -1,156 +0,0 @@
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# i.MX RT5XX Series |
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# Copyright 2022-2023, NXP |
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# SPDX-License-Identifier: Apache-2.0 |
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choice |
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prompt "i.MX RT5XX Series MCU Selection" |
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depends on SOC_SERIES_IMX_RT5XX |
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config SOC_MIMXRT595S_CM33 |
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bool "SOC_MIMXRT595S M33" |
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select CPU_HAS_ARM_SAU |
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select CPU_HAS_ARM_MPU |
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select CPU_HAS_FPU |
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select PLATFORM_SPECIFIC_INIT |
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select ARMV8_M_DSP |
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select ARM_TRUSTZONE_M |
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select CPU_CORTEX_M_HAS_SYSTICK |
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select HAS_MCUX |
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select HAS_MCUX_SYSCON |
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select HAS_MCUX_FLEXCOMM |
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select HAS_MCUX_FLEXSPI |
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select HAS_MCUX_CACHE |
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select HAS_MCUX_LPC_DMA |
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select HAS_MCUX_LPADC |
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select HAS_MCUX_OS_TIMER |
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select HAS_MCUX_LPC_RTC |
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select HAS_MCUX_TRNG |
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select HAS_MCUX_SCTIMER |
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select HAS_MCUX_USDHC1 |
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select HAS_MCUX_USDHC2 |
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select HAS_MCUX_USB_LPCIP3511 |
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select HAS_MCUX_CTIMER |
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endchoice |
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if SOC_SERIES_IMX_RT5XX |
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config SOC_PART_NUMBER_MIMXRT533SFFOC |
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bool |
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config SOC_PART_NUMBER_MIMXRT555SFFOC |
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bool |
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config SOC_PART_NUMBER_MIMXRT595SFFOC |
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bool |
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config SOC_PART_NUMBER_MIMXRT533SFAWC |
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bool |
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config SOC_PART_NUMBER_MIMXRT555SFAWC |
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bool |
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config SOC_PART_NUMBER_MIMXRT595SFAWC |
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bool |
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config SOC_PART_NUMBER_IMX_RT5XX |
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string |
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default "MIMXRT533SFAWC" if SOC_PART_NUMBER_MIMXRT533SFAWC |
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default "MIMXRT555SFAWC" if SOC_PART_NUMBER_MIMXRT555SFAWC |
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default "MIMXRT595SFAWC" if SOC_PART_NUMBER_MIMXRT595SFAWC |
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default "MIMXRT533SFFOC" if SOC_PART_NUMBER_MIMXRT533SFFOC |
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default "MIMXRT555SFFOC" if SOC_PART_NUMBER_MIMXRT555SFFOC |
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default "MIMXRT595SFFOC" if SOC_PART_NUMBER_MIMXRT595SFFOC |
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|
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help |
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This string holds the full part number of the SoC. It is a hidden |
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option that you should not set directly. The part number selection |
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choice defines the default value for this string. |
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menuconfig NXP_IMX_RT5XX_BOOT_HEADER |
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bool "The boot header" |
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depends on !BOOTLOADER_MCUBOOT |
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help |
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Enable data structures required by the boot ROM to boot the |
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application from an external flash device. |
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if NXP_IMX_RT5XX_BOOT_HEADER |
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choice BOOT_DEVICE |
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prompt "Boot device selection" |
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default BOOT_FLEXSPI_NOR |
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config BOOT_FLEXSPI_NOR |
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bool "FlexSPI serial NOR" |
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endchoice |
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config FLASH_CONFIG_OFFSET |
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hex "Flash config data offset" |
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default 0x400 |
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help |
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The flash config offset provides the boot ROM with the on-board |
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flash type and parameters. The boot ROM requires a fixed flash config |
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offset for FlexSPI device. |
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|
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config IMAGE_VECTOR_TABLE_OFFSET |
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hex "Image vector table offset" |
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default 0x1000 |
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help |
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The Image Vector Table (IVT) provides the boot ROM with pointers to |
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the application entry point and device configuration data. The boot |
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ROM requires a fixed IVT offset for each type of boot device. |
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config NXP_IMX_RT_ROM_RAMLOADER |
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depends on !FLASH_MCUX_FLEXSPI_XIP |
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# Required so that debugger will load image to correct offset |
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select BUILD_OUTPUT_HEX |
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bool "Create output image that IMX RT ROM can load from FlexSPI to ram" |
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help |
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Builds an output image that the IMX RT BootROM can load from the |
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FlexSPI boot device into RAM region. The image will be loaded |
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from FLEXSPI0 into the region specified by `zephyr,flash` node. |
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|
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# Setup LMA adjustment if using the RAMLOADER feature of ROM |
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FLASH_CHOSEN := zephyr,flash |
||||
FLASH_BASE := $(dt_chosen_reg_addr_hex,$(FLASH_CHOSEN)) |
||||
FLEXSPI_BASE := $(dt_node_reg_addr_hex,/soc/spi@134000,1) |
||||
config BUILD_OUTPUT_ADJUST_LMA |
||||
default "$(FLEXSPI_BASE) - $(FLASH_BASE)" if NXP_IMX_RT_ROM_RAMLOADER |
||||
|
||||
endif # NXP_IMX_RT5XX_BOOT_HEADER |
||||
|
||||
|
||||
|
||||
config IMXRT5XX_CODE_CACHE |
||||
bool "Code cache" |
||||
default y |
||||
help |
||||
Enable code cache for FlexSPI region at boot. If this Kconfig is |
||||
cleared, the CACHE64 controller will be disabled during SOC init |
||||
|
||||
choice FLEXCOMM0_CLK_SRC |
||||
prompt "Clock source for Flexcomm0" |
||||
default FLEXCOMM0_CLK_SRC_FRG |
||||
|
||||
config FLEXCOMM0_CLK_SRC_FRG |
||||
bool "FRG is source of Flexcomm0 clock" |
||||
|
||||
config FLEXCOMM0_CLK_SRC_FRO |
||||
bool "FRO_DIV4 is source of Flexcomm0 clock" |
||||
|
||||
endchoice |
||||
|
||||
choice MIPI_DPHY_CLK_SRC |
||||
prompt "Clock source for MIPI DPHY" |
||||
default MIPI_DPHY_CLK_SRC_AUX1_PLL |
||||
|
||||
config MIPI_DPHY_CLK_SRC_AUX1_PLL |
||||
bool "AUX1_PLL is source of MIPI_DPHY clock" |
||||
|
||||
config MIPI_DPHY_CLK_SRC_FRO |
||||
bool "FRO 192/96M is source of MIPI_DPHY clock" |
||||
|
||||
endchoice |
||||
|
||||
endif # SOC_SERIES_IMX_RT5XX |
||||
@ -1,10 +0,0 @@
@@ -1,10 +0,0 @@
|
||||
/* |
||||
* Copyright (c) 2022 NXP |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
|
||||
. = CONFIG_FLASH_CONFIG_OFFSET; |
||||
KEEP(*(.flash_conf)) |
||||
. = CONFIG_IMAGE_VECTOR_TABLE_OFFSET; |
||||
KEEP(*(.boot_hdr.ivt)) |
||||
@ -1,20 +0,0 @@
@@ -1,20 +0,0 @@
|
||||
# NXP i.MX8 SoC family configuration options |
||||
# |
||||
# Copyright (c) 2021 NXP |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
config SOC_FAMILY_NXP_ADSP |
||||
bool |
||||
select ARCH_HAS_COHERENCE |
||||
select CPU_HAS_DCACHE |
||||
|
||||
if SOC_FAMILY_NXP_ADSP |
||||
|
||||
config SOC_FAMILY |
||||
string |
||||
default "nxp_adsp" |
||||
|
||||
# Select SoC Part No. and configuration options |
||||
source "soc/soc_legacy/xtensa/nxp_adsp/*/Kconfig.soc" |
||||
|
||||
endif # SOC_FAMILY_NXP_ADSP |
||||
@ -1,33 +0,0 @@
@@ -1,33 +0,0 @@
|
||||
# NXP i.MX8/RT SoC family default configuration options |
||||
# |
||||
# Copyright (c) 2021 NXP |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
if SOC_FAMILY_NXP_ADSP |
||||
|
||||
source "soc/soc_legacy/xtensa/nxp_adsp/*/Kconfig.defconfig.series" |
||||
|
||||
config CACHE_MANAGEMENT |
||||
default y |
||||
|
||||
config SMP |
||||
default n |
||||
|
||||
config XTENSA_TIMER |
||||
default y |
||||
|
||||
config KERNEL_ENTRY |
||||
default "__start" |
||||
|
||||
config MULTI_LEVEL_INTERRUPTS |
||||
default n |
||||
|
||||
config 2ND_LEVEL_INTERRUPTS |
||||
default n |
||||
|
||||
# To prevent test uses TEST_LOGGING_MINIMAL |
||||
config TEST_LOGGING_DEFAULTS |
||||
default n |
||||
depends on TEST |
||||
|
||||
endif |
||||
@ -1,6 +0,0 @@
@@ -1,6 +0,0 @@
|
||||
# NXP i.MX8 SoC series selection |
||||
# |
||||
# Copyright (c) 2021 NXP |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
source "soc/soc_legacy/xtensa/nxp_adsp/*/Kconfig.series" |
||||
@ -1,6 +0,0 @@
@@ -1,6 +0,0 @@
|
||||
# NXP SoC family CMake file |
||||
# |
||||
# Copyright (c) 2021 NXP |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
zephyr_include_directories(include) |
||||
@ -1,46 +0,0 @@
@@ -1,46 +0,0 @@
|
||||
# Copyright (c) 2023 Google LLC. |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
if SOC_SERIES_NXP_RT5XX |
||||
|
||||
config SOC_SERIES |
||||
string |
||||
default "rt5xx" |
||||
|
||||
config SOC_TOOLCHAIN_NAME |
||||
string |
||||
default "nxp_rt500_adsp" |
||||
|
||||
config SOC |
||||
string |
||||
default "nxp_rt5xx" |
||||
|
||||
config SOC_PART_NUMBER |
||||
string |
||||
default "MIMXRT595SFFOC_dsp" if SOC_NXP_RT595 |
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC |
||||
default 198000000 |
||||
|
||||
config XTENSA_CCOUNT_HZ |
||||
default SYS_CLOCK_HW_CYCLES_PER_SEC |
||||
|
||||
config SYS_CLOCK_TICKS_PER_SEC |
||||
default 1000 |
||||
|
||||
config DYNAMIC_INTERRUPTS |
||||
default n |
||||
|
||||
config CACHE |
||||
default n |
||||
|
||||
config DCACHE |
||||
default n |
||||
|
||||
config CACHE_MANAGEMENT |
||||
default n |
||||
|
||||
config LOG |
||||
default n |
||||
|
||||
endif # SOC_SERIES_NXP_RT5XX |
||||
@ -1,12 +0,0 @@
@@ -1,12 +0,0 @@
|
||||
# Copyright (c) 2023 Google LLC. |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
config SOC_SERIES_NXP_RT5XX |
||||
bool "NXP RT5xx Series" |
||||
select SOC_FAMILY_NXP_ADSP |
||||
select XTENSA |
||||
select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang") |
||||
select XTENSA_RESET_VECTOR |
||||
select XTENSA_USE_CORE_CRT1 |
||||
help |
||||
NXP RT5xx ADSP Series |
||||
@ -1,10 +0,0 @@
@@ -1,10 +0,0 @@
|
||||
# Copyright (c) 2023 Google LLC. |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
choice |
||||
prompt "NXP RT5xx ADSP SoC Selection" |
||||
|
||||
config SOC_NXP_RT595 |
||||
bool "NXP RT595" |
||||
depends on SOC_SERIES_NXP_RT5XX |
||||
endchoice |
||||
Loading…
Reference in new issue