boards: arm: fvp_baser_aemv8r_aarch32: Convert to v2

Converts the board to hwmv2

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>

boards/arm/fvp_baser_aemv8r/Kconfig.fvp_baser_aemv8r

@@ -2,5 +2,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config BOARD_FVP_BASER_AEMV8R
-	select SOC_SERIES_FVP_AEMV8R
-	select SOC_FVP_AEMV8R_AARCH64
+	select SOC_FVP_AEMV8R_AARCH64 if BOARD_FVP_BASER_AEMV8R_FVP_AEMV8R_AARCH64 || BOARD_FVP_BASER_AEMV8R_FVP_AEMV8R_AARCH64_SMP
+	select SOC_FVP_AEMV8R_AARCH32 if BOARD_FVP_BASER_AEMV8R_FVP_AEMV8R_AARCH32 || BOARD_FVP_BASER_AEMV8R_FVP_AEMV8R_AARCH32_SMP

boards/arm/fvp_baser_aemv8r/board.cmake

@@ -5,35 +5,70 @@ set(SUPPORTED_EMU_PLATFORMS armfvp)
 set(ARMFVP_BIN_NAME FVP_BaseR_AEMv8R)
 set(ARMFVP_MIN_VERSION 11.16.16)
 
-set(ARMFVP_FLAGS
-  -C cluster0.has_aarch64=1
-  -C cluster0.VMSA_supported=0
-  -C cluster0.NUM_CORES=${CONFIG_MP_MAX_NUM_CPUS}
-  -C cluster0.gicv3.cpuintf-mmap-access-level=2
-  -C cluster0.gicv3.SRE-enable-action-on-mmap=2
-  -C cluster0.gicv3.SRE-EL2-enable-RAO=1
-  -C cluster0.gicv3.extended-interrupt-range-support=1
-  -C gic_distributor.GICD_CTLR-DS-1-means-secure-only=1
-  -C gic_distributor.has-two-security-states=0
-  -C bp.refcounter.non_arch_start_at_default=1
-  # UART0 config
-  -C bp.pl011_uart0.out_file=-
-  -C bp.pl011_uart0.unbuffered_output=1
-  -C bp.terminal_0.start_telnet=0
-  # UART1 config
-  -C bp.pl011_uart1.out_file=-
-  -C bp.pl011_uart1.unbuffered_output=1
-  -C bp.terminal_1.start_telnet=0
-  # UART2 config
-  -C bp.pl011_uart2.out_file=-
-  -C bp.pl011_uart2.unbuffered_output=1
-  -C bp.terminal_2.start_telnet=0
-  # UART3 config
-  -C bp.pl011_uart3.out_file=-
-  -C bp.pl011_uart3.unbuffered_output=1
-  -C bp.terminal_3.start_telnet=0
+if(CONFIG_BOARD_FVP_BASER_AEMV8R_FVP_AEMV8R_AARCH64)
+  set(ARMFVP_FLAGS
+    -C cluster0.has_aarch64=1
+    -C cluster0.VMSA_supported=0
+    -C cluster0.NUM_CORES=${CONFIG_MP_MAX_NUM_CPUS}
+    -C cluster0.gicv3.cpuintf-mmap-access-level=2
+    -C cluster0.gicv3.SRE-enable-action-on-mmap=2
+    -C cluster0.gicv3.SRE-EL2-enable-RAO=1
+    -C cluster0.gicv3.extended-interrupt-range-support=1
+    -C gic_distributor.GICD_CTLR-DS-1-means-secure-only=1
+    -C gic_distributor.has-two-security-states=0
+    -C bp.refcounter.non_arch_start_at_default=1
+    # UART0 config
+    -C bp.pl011_uart0.out_file=-
+    -C bp.pl011_uart0.unbuffered_output=1
+    -C bp.terminal_0.start_telnet=0
+    # UART1 config
+    -C bp.pl011_uart1.out_file=-
+    -C bp.pl011_uart1.unbuffered_output=1
+    -C bp.terminal_1.start_telnet=0
+    # UART2 config
+    -C bp.pl011_uart2.out_file=-
+    -C bp.pl011_uart2.unbuffered_output=1
+    -C bp.terminal_2.start_telnet=0
+    # UART3 config
+    -C bp.pl011_uart3.out_file=-
+    -C bp.pl011_uart3.unbuffered_output=1
+    -C bp.terminal_3.start_telnet=0
 
-  -C bp.vis.disable_visualisation=1
-  -C bp.vis.rate_limit-enable=0
-  -C cache_state_modelled=1
-  )
+    -C bp.vis.disable_visualisation=1
+    -C bp.vis.rate_limit-enable=0
+    -C cache_state_modelled=1
+    )
+elseif(CONFIG_BOARD_FVP_BASER_AEMV8R_FVP_AEMV8R_AARCH32)
+  set(ARMFVP_FLAGS
+    -C cluster0.has_aarch64=0
+    -C cluster0.VMSA_supported=0
+    -C cluster0.NUM_CORES=${CONFIG_MP_MAX_NUM_CPUS}
+    -C cluster0.gicv3.cpuintf-mmap-access-level=2
+    -C cluster0.gicv3.SRE-enable-action-on-mmap=2
+    -C cluster0.gicv3.SRE-EL2-enable-RAO=1
+    -C cluster0.gicv3.extended-interrupt-range-support=1
+    -C gic_distributor.GICD_CTLR-DS-1-means-secure-only=1
+    -C gic_distributor.has-two-security-states=0
+    -C bp.refcounter.non_arch_start_at_default=1
+    # UART0 config
+    -C bp.pl011_uart0.out_file=-
+    -C bp.pl011_uart0.unbuffered_output=1
+    -C bp.terminal_0.start_telnet=0
+    # UART1 config
+    -C bp.pl011_uart1.out_file=-
+    -C bp.pl011_uart1.unbuffered_output=1
+    -C bp.terminal_1.start_telnet=0
+    # UART2 config
+    -C bp.pl011_uart2.out_file=-
+    -C bp.pl011_uart2.unbuffered_output=1
+    -C bp.terminal_2.start_telnet=0
+    # UART3 config
+    -C bp.pl011_uart3.out_file=-
+    -C bp.pl011_uart3.unbuffered_output=1
+    -C bp.terminal_3.start_telnet=0
+
+    -C bp.vis.disable_visualisation=1
+    -C bp.vis.rate_limit-enable=0
+    -C cache_state_modelled=0
+    )
+endif()

boards/arm/fvp_baser_aemv8r/board.yml

@@ -5,3 +5,6 @@ board:
   - name: fvp_aemv8r_aarch64
     variants:
     - name: 'smp'
+  - name: fvp_aemv8r_aarch32
+    variants:
+    - name: 'smp'

boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32.yaml

@@ -2,7 +2,7 @@
 # Copyright (c) 2022 IoT.bzh
 # SPDX-License-Identifier: Apache-2.0
 
-identifier: fvp_baser_aemv8r_aarch32
+identifier: fvp_baser_aemv8r/fvp_aemv8r_aarch32
 name: FVP Emulation FVP_BaseR_AEMv8R AArch32
 arch: arm
 type: sim

boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32_defconfig

@@ -2,9 +2,6 @@
 # Copyright (c) 2022 IoT.bzh
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SOC_SERIES_FVP_AEMV8R_AARCH32=y
-CONFIG_SOC_FVP_AEMV8R_AARCH32=y
-CONFIG_BOARD_FVP_BASER_AEMV8R_AARCH32=y
 CONFIG_ARM_MPU=y
 
 CONFIG_ISR_STACK_SIZE=1024

boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32_smp.dts

@@ -5,4 +5,4 @@
 
 /dts-v1/;
 
-#include "fvp_baser_aemv8r_aarch32.dts"
+#include "fvp_baser_aemv8r_fvp_aemv8r_aarch32.dts"

boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32_smp.yaml

@@ -1,7 +1,7 @@
 # Copyright (c) 2023 Arm Limited (or its affiliates). All rights reserved.
 # SPDX-License-Identifier: Apache-2.0
 
-identifier: fvp_baser_aemv8r_aarch32_smp
+identifier: fvp_baser_aemv8r/fvp_aemv8r_aarch32/smp
 name: FVP Emulation FVP_BaseR_AEMv8R AArch32 (SMP)
 arch: arm
 type: sim

boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32_smp_defconfig

@@ -0,0 +1,6 @@
+# Copyright (c) 2023 Arm Limited (or its affiliates). All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_USE_SWITCH=y
+CONFIG_SMP=y
+CONFIG_MP_MAX_NUM_CPUS=4

boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64.yaml

@@ -1,7 +1,7 @@
 # Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
 # SPDX-License-Identifier: Apache-2.0
 
-identifier: fvp_baser_aemv8r
+identifier: fvp_baser_aemv8r/fvp_aemv8r_aarch64
 name: FVP Emulation FVP_BaseR_AEMv8R
 arch: arm64
 type: sim

boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64_smp.dts

@@ -3,4 +3,4 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include "fvp_baser_aemv8r.dts"
+#include "fvp_baser_aemv8r_fvp_aemv8r_aarch64.dts"

boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64_smp.yaml

@@ -1,7 +1,7 @@
 # Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
 # SPDX-License-Identifier: Apache-2.0
 
-identifier: fvp_baser_aemv8r//smp
+identifier: fvp_baser_aemv8r/fvp_aemv8r_aarch64/smp
 name: FVP Emulation FVP_BaseR_AEMv8R (SMP)
 arch: arm64
 type: sim

boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64_smp_defconfig

@@ -1,26 +1,7 @@
 # Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
 # SPDX-License-Identifier: Apache-2.0
 
-# Cache management
-CONFIG_CACHE_MANAGEMENT=y
-
-CONFIG_THREAD_STACK_INFO=y
-
-# Enable Timer and Sys clock
-CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
-CONFIG_ARM_ARCH_TIMER=y
-
-# Enable UART driver
-CONFIG_SERIAL=y
-
-# Enable serial port
-CONFIG_UART_INTERRUPT_DRIVEN=y
-
-# Enable console
-CONFIG_CONSOLE=y
-CONFIG_UART_CONSOLE=y
-
-# Enable simulate cpu power management
+# Enable simulated CPU power management
 CONFIG_SOC_FVP_AEMV8R_SIMULATE_CPU_PM=y
 CONFIG_PM_CPU_OPS=y
 CONFIG_PM_CPU_OPS_PSCI=n

boards/boards_legacy/arm/fvp_baser_aemv8r_aarch32/Kconfig.board

@@ -1,7 +0,0 @@
-# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
-# Copyright (c) 2022 IoT.bzh
-# SPDX-License-Identifier: Apache-2.0
-
-config BOARD_FVP_BASER_AEMV8R_AARCH32
-	bool "FVP BaseR AEMv8R AArch32 simulation board"
-	depends on SOC_FVP_AEMV8R_AARCH32

boards/boards_legacy/arm/fvp_baser_aemv8r_aarch32/Kconfig.defconfig

@@ -1,13 +0,0 @@
-# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
-# Copyright (c) 2022 IoT.bzh
-# SPDX-License-Identifier: Apache-2.0
-
-if BOARD_FVP_BASER_AEMV8R_AARCH32
-
-config BUILD_OUTPUT_BIN
-	default y
-
-config BOARD
-	default "fvp_baser_aemv8r_aarch32"
-
-endif # BOARD_FVP_BASER_AEMV8R_AARCH32

boards/boards_legacy/arm/fvp_baser_aemv8r_aarch32/board.cmake

@@ -1,39 +0,0 @@
-# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
-# Copyright (c) 2022 IoT.bzh
-# SPDX-License-Identifier: Apache-2.0
-
-set(SUPPORTED_EMU_PLATFORMS armfvp)
-set(ARMFVP_BIN_NAME FVP_BaseR_AEMv8R)
-
-set(ARMFVP_FLAGS
-  -C cluster0.has_aarch64=0
-  -C cluster0.VMSA_supported=0
-  -C cluster0.NUM_CORES=${CONFIG_MP_MAX_NUM_CPUS}
-  -C cluster0.gicv3.cpuintf-mmap-access-level=2
-  -C cluster0.gicv3.SRE-enable-action-on-mmap=2
-  -C cluster0.gicv3.SRE-EL2-enable-RAO=1
-  -C cluster0.gicv3.extended-interrupt-range-support=1
-  -C gic_distributor.GICD_CTLR-DS-1-means-secure-only=1
-  -C gic_distributor.has-two-security-states=0
-  -C bp.refcounter.non_arch_start_at_default=1
-  # UART0 config
-  -C bp.pl011_uart0.out_file=-
-  -C bp.pl011_uart0.unbuffered_output=1
-  -C bp.terminal_0.start_telnet=0
-  # UART1 config
-  -C bp.pl011_uart1.out_file=-
-  -C bp.pl011_uart1.unbuffered_output=1
-  -C bp.terminal_1.start_telnet=0
-  # UART2 config
-  -C bp.pl011_uart2.out_file=-
-  -C bp.pl011_uart2.unbuffered_output=1
-  -C bp.terminal_2.start_telnet=0
-  # UART3 config
-  -C bp.pl011_uart3.out_file=-
-  -C bp.pl011_uart3.unbuffered_output=1
-  -C bp.terminal_3.start_telnet=0
-
-  -C bp.vis.disable_visualisation=1
-  -C bp.vis.rate_limit-enable=0
-  -C cache_state_modelled=0
-  )

boards/boards_legacy/arm/fvp_baser_aemv8r_aarch32/fvp_baser_aemv8r_aarch32_smp_defconfig

@@ -1,32 +0,0 @@
-# Copyright (c) 2023 Arm Limited (or its affiliates). All rights reserved.
-# SPDX-License-Identifier: Apache-2.0
-
-CONFIG_SOC_SERIES_FVP_AEMV8R_AARCH32=y
-CONFIG_SOC_FVP_AEMV8R_AARCH32=y
-CONFIG_BOARD_FVP_BASER_AEMV8R_AARCH32=y
-CONFIG_ARM_MPU=y
-
-CONFIG_ISR_STACK_SIZE=1024
-CONFIG_THREAD_STACK_INFO=y
-
-# Enable Timer and Sys clock
-CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
-CONFIG_ARM_ARCH_TIMER=y
-
-# Enable UART driver
-CONFIG_SERIAL=y
-
-# Enable serial port
-CONFIG_UART_INTERRUPT_DRIVEN=y
-
-# Enable console
-CONFIG_CONSOLE=y
-CONFIG_UART_CONSOLE=y
-
-CONFIG_CACHE_MANAGEMENT=y
-
-CONFIG_USE_SWITCH=y
-CONFIG_SMP=y
-CONFIG_MP_MAX_NUM_CPUS=4
-
-CONFIG_DCACHE=n