Browse Source
Port CM4 core to HVMv2. This core is merged with the existing board definition, which supported the A53 target. Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>collab-hwm
Daniel DeGrasse
1 year ago
committed by
Jamie
12 changed files with 128 additions and 244 deletions
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# MIMX8MM EVK board |
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# Copyright (c) 2020, Manivannan Sadhasivam <mani@kernel.org> |
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# SPDX-License-Identifier: Apache-2.0 |
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config BOARD_MIMX8MM_EVK |
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bool "NXP i.MX8M Mini EVK" |
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depends on SOC_SERIES_IMX8MM_M4 |
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select SOC_PART_NUMBER_MIMX8MM6DVTLZ |
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# |
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# Copyright (c) 2020, NXP |
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# |
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# SPDX-License-Identifier: Apache-2.0 |
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# |
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board_set_debugger_ifnset(jlink) |
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board_set_flasher_ifnset(jlink) |
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board_runner_args(jlink "--device=MIMX8MD6_M4") |
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include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) |
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Before Width: | Height: | Size: 47 KiB |
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.. _mimx8mm_evk: |
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NXP MIMX8MM EVK |
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############### |
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Overview |
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******** |
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i.MX8M Mini LPDDR4 EVK board is based on NXP i.MX8M Mini applications |
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processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M4 core. |
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Zephyr OS is ported to run on the Cortex®-M4 core. |
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- Board features: |
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- RAM: 2GB LPDDR4 |
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- Storage: |
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- SanDisk 16GB eMMC5.1 |
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- Micron 32MB QSPI NOR |
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- microSD Socket |
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- Wireless: |
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- WiFi: 2.4/5GHz IEEE 802.11b/g/n |
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- Bluetooth: v4.1 |
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- USB: |
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- OTG - 2x type C |
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- Ethernet |
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- PCI-E M.2 |
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- Connectors: |
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- 40-Pin Dual Row Header |
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- LEDs: |
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- 1x Power status LED |
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- 1x UART LED |
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- Debug |
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- JTAG 20-pin connector |
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- MicroUSB for UART debug, two COM ports for A53 and M4 |
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.. image:: img/mimx8mm_evk.jpg |
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:align: center |
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:alt: MIMX8MM EVK |
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More information about the board can be found at the |
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`NXP website`_. |
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Supported Features |
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================== |
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The Zephyr mimx8mm_evk board configuration supports the following hardware |
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features: |
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+-----------+------------+-------------------------------------+ |
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| Interface | Controller | Driver/Component | |
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+===========+============+=====================================+ |
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| NVIC | on-chip | nested vector interrupt controller | |
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+-----------+------------+-------------------------------------+ |
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| SYSTICK | on-chip | systick | |
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+-----------+------------+-------------------------------------+ |
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| CLOCK | on-chip | clock_control | |
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+-----------+------------+-------------------------------------+ |
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| PINMUX | on-chip | pinmux | |
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+-----------+------------+-------------------------------------+ |
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| UART | on-chip | serial port-polling; | |
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| | | serial port-interrupt | |
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+-----------+------------+-------------------------------------+ |
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| GPIO | on-chip | GPIO output | |
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| | | GPIO input | |
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+-----------+------------+-------------------------------------+ |
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The default configuration can be found in the defconfig file: |
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:zephyr_file:`boards/arm/mimx8mm_evk/mimx8mm_evk_defconfig`. |
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It is recommended to disable peripherals used by the M4 core on the Linux host. |
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Other hardware features are not currently supported by the port. |
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Connections and IOs |
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=================== |
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MIMX8MM EVK board was tested with the following pinmux controller |
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configuration. |
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+---------------+-----------------+---------------------------+ |
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| Board Name | SoC Name | Usage | |
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+===============+=================+===========================+ |
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| UART4 RXD | UART4_TXD | UART Console | |
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+---------------+-----------------+---------------------------+ |
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| UART4 TXD | UART4_RXD | UART Console | |
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+---------------+-----------------+---------------------------+ |
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System Clock |
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============ |
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The M4 Core is configured to run at a 400 MHz clock speed. |
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Serial Port |
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=========== |
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The i.MX8M Mini SoC has four UARTs. UART_4 is configured for the console and |
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the remaining are not used/tested. |
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Programming and Debugging |
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************************* |
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The MIMX8MM EVK board doesn't have QSPI flash for the M4 and it needs |
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to be started by the A53 core. The A53 core is responsible to load the M4 binary |
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application into the RAM, put the M4 in reset, set the M4 Program Counter and |
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Stack Pointer, and get the M4 out of reset. The A53 can perform these steps at |
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bootloader level or after the Linux system has booted. |
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The M4 can use up to 3 different RAMs. These are the memory mapping for A53 and M4: |
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+------------+-------------------------+------------------------+-----------------------+----------------------+ |
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| Region | Cortex-A53 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size | |
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+============+=========================+========================+=======================+======================+ |
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| OCRAM | 0x00900000-0x0093FFFF | 0x20200000-0x2023FFFF | 0x00900000-0x0093FFFF | 256KB | |
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+------------+-------------------------+------------------------+-----------------------+----------------------+ |
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| TCMU | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB | |
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+------------+-------------------------+------------------------+-----------------------+----------------------+ |
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| TCML | 0x007E0000-0x007FFFFF | | 0x1FFE0000-0x1FFFFFFF | 128KB | |
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+------------+-------------------------+------------------------+-----------------------+----------------------+ |
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| OCRAM_S | 0x00180000-0x00187FFF | 0x20180000-0x20187FFF | 0x00180000-0x00187FFF | 32KB | |
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+------------+-------------------------+------------------------+-----------------------+----------------------+ |
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For more information about memory mapping see the |
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`i.MX 8M Applications Processor Reference Manual`_ (section 2.1.2 and 2.1.3) |
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At compilation time you have to choose which RAM will be used. This |
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configuration is done in the file ``boards/arm/mimx8mm_evk/mimx8mm_evk.dts`` |
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with "zephyr,flash" (when CONFIG_XIP=y) and "zephyr,sram" properties. |
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The available configurations are: |
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.. code-block:: none |
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"zephyr,flash" |
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- &tcml_code |
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- &ocram_code |
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- &ocram_s_code |
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"zephyr,sram" |
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- &tcmu_sys |
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- &ocram_sys |
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- &ocram_s_sys |
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Load and run Zephyr on M4 from A53 using u-boot by copying the compiled |
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``zephyr.bin`` to the first FAT partition of the SD card and plug the SD |
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card into the board. Power it up and stop the u-boot execution at prompt. |
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Load the M4 binary onto the desired memory and start its execution using: |
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.. code-block:: console |
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fatload mmc 0:1 0x7e0000 zephyr.bin;bootaux 0x7e0000 |
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Debugging |
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========= |
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MIMX8MM EVK board can be debugged by connecting an external JLink |
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JTAG debugger to the J902 debug connector and to the PC. Then |
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the application can be debugged using the usual way. |
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Here is an example for the :ref:`hello_world` application. |
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.. zephyr-app-commands:: |
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:zephyr-app: samples/hello_world |
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:board: mimx8mm_evk |
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:goals: debug |
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Open a serial terminal, step through the application in your debugger, and you |
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should see the following message in the terminal: |
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.. code-block:: console |
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***** Booting Zephyr OS build zephyr-v2.0.0-1859-g292afe8533c0 ***** |
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Hello World! mimx8mm_evk |
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References |
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========== |
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.. _NXP website: |
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https://www.nxp.com/design/development-boards/i.mx-evaluation-and-development-boards/evaluation-kit-for-thebr-i.mx-8m-mini-applications-processor:8MMINILPD4-EVK |
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.. _i.MX 8M Applications Processor Reference Manual: |
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https://www.nxp.com/webapp/Download?colCode=IMX8MMRM |
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/* |
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* Copyright (c) 2022, NXP |
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* SPDX-License-Identifier: Apache-2.0 |
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* |
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* Note: File generated by gen_board_pinctrl.py |
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* from MIMX8MM-EVK-REV-C.mex |
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*/ |
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#include <nxp/nxp_imx/mimx8mm6dvtlz-pinctrl.dtsi> |
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&pinctrl { |
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uart4_default: uart4_default { |
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group0 { |
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pinmux = <&iomuxc_uart4_rxd_uart_rx_uart4_rx>, |
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<&iomuxc_uart4_txd_uart_tx_uart4_tx>; |
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slew-rate = "fast"; |
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drive-strength = "40-ohm"; |
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}; |
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}; |
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}; |
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# SPDX-License-Identifier: Apache-2.0 |
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# Copyright 2024 NXP |
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if(CONFIG_BOARD_IMX8MM_EVK_MIMX8MM6_M4) |
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board_set_debugger_ifnset(jlink) |
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board_set_flasher_ifnset(jlink) |
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board_runner_args(jlink "--device=MIMX8MD6_M4") |
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include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) |
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endif() |
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# |
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# Copyright (c) 2020, Manivannan Sadhasivam <mani@kernel.org> |
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# Copyright 2024 |
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# |
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# SPDX-License-Identifier: Apache-2.0 |
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# |
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identifier: mimx8mm_evk |
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identifier: imx8mm_evk/mimx8mm6/m4 |
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name: NXP i.MX8M Mini EVK |
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type: mcu |
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arch: arm |
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# |
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# Copyright (c) 2020, Manivannan Sadhasivam <mani@kernel.org> |
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# Copyright 2024 NXP |
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# |
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# SPDX-License-Identifier: Apache-2.0 |
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# |
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CONFIG_SOC_SERIES_IMX8MM_M4=y |
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CONFIG_SOC_MIMX8MM6=y |
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CONFIG_BOARD_MIMX8MM_EVK=y |
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CONFIG_CLOCK_CONTROL=y |
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CONFIG_UART_CONSOLE=y |
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CONFIG_SERIAL=y |
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