Browse Source

soc: boards: xtensa: intel_adsp_ace: Rename with HWMv2

Rename for better HWMv2 use:

  SoC - `intel_ace15_mtpm` --> `ace15_mtpm`
  SoC - `intel_ace20_lnl`  --> `ace20_lnl`

Resulting shortened name for boards:

  `intel_adsp_ace15_mtpm/intel_ace15_mtpm` -->
  `intel_adsp_ace15_mtpm/ace15_mtpm`

  `intel_adsp_ace20_lnl/intel_ace20_lnl` -->
  `intel_adsp_ace20_lnl/ace20_lnl`

Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>
pull/69687/head
Dmitrii Golovanov 1 year ago committed by Carles Cufi
parent
commit
d1b3bcce64
  1. 2
      boards/intel/intel_adsp_ace15_mtpm/board.yml
  2. 2
      boards/intel/intel_adsp_ace20_lnl/board.yml
  3. 4
      soc/intel/intel_adsp/ace/CMakeLists.txt
  4. 4
      soc/intel/intel_adsp/ace/Kconfig.soc
  5. 4
      soc/intel/intel_adsp/soc.yml

2
boards/intel/intel_adsp_ace15_mtpm/board.yml

@ -2,4 +2,4 @@ board: @@ -2,4 +2,4 @@ board:
name: intel_adsp_ace15_mtpm
vendor: intel
socs:
- name: intel_ace15_mtpm
- name: ace15_mtpm

2
boards/intel/intel_adsp_ace20_lnl/board.yml

@ -2,4 +2,4 @@ board: @@ -2,4 +2,4 @@ board:
name: intel_adsp_ace20_lnl
vendor: intel
socs:
- name: intel_ace20_lnl
- name: ace20_lnl

4
soc/intel/intel_adsp/ace/CMakeLists.txt

@ -1,6 +1,6 @@ @@ -1,6 +1,6 @@
# Intel ACE SoC family CMake file
#
# Copyright (c) 2022 Intel Corporation
# Copyright (c) 2022-2024 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
@ -15,7 +15,7 @@ zephyr_library_sources( @@ -15,7 +15,7 @@ zephyr_library_sources(
)
zephyr_include_directories(include)
zephyr_include_directories(include/${SOC_NAME})
zephyr_include_directories(include/${SOC_TOOLCHAIN_NAME})
zephyr_library_sources_ifdef(CONFIG_SOC_INTEL_COMM_WIDGET comm_widget.c)
zephyr_library_sources_ifdef(CONFIG_SOC_INTEL_COMM_WIDGET comm_widget_messages.c)

4
soc/intel/intel_adsp/ace/Kconfig.soc

@ -24,5 +24,5 @@ config SOC_INTEL_ACE20_LNL @@ -24,5 +24,5 @@ config SOC_INTEL_ACE20_LNL
ACE 2.0 Lunar Lake PCH
config SOC
default "intel_ace15_mtpm" if SOC_INTEL_ACE15_MTPM
default "intel_ace20_lnl" if SOC_INTEL_ACE20_LNL
default "ace15_mtpm" if SOC_INTEL_ACE15_MTPM
default "ace20_lnl" if SOC_INTEL_ACE20_LNL

4
soc/intel/intel_adsp/soc.yml

@ -3,8 +3,8 @@ family: @@ -3,8 +3,8 @@ family:
series:
- name: ace
socs:
- name: intel_ace15_mtpm
- name: intel_ace20_lnl
- name: ace15_mtpm
- name: ace20_lnl
- name: cavs
socs:
- name: cavs25

Loading…
Cancel
Save