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boards: convert QEMU RV32E board to Zephyr HWMv2

This commit converts the QEMU RV32E board to Zephyr HWMvW. This includes
the following former target: qemu_riscv32e.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
pull/69687/head
Filip Kokosinski 1 year ago committed by Carles Cufi
parent
commit
f4c31a2b86
  1. 11
      boards/boards_legacy/riscv/qemu_riscv32e/Kconfig.board
  2. 13
      boards/boards_legacy/riscv/qemu_riscv32e/Kconfig.defconfig
  3. 5
      boards/qemu/qemu_riscv32e/Kconfig
  4. 16
      boards/qemu/qemu_riscv32e/Kconfig.defconfig
  5. 5
      boards/qemu/qemu_riscv32e/Kconfig.qemu_riscv32e
  6. 0
      boards/qemu/qemu_riscv32e/board.cmake
  7. 5
      boards/qemu/qemu_riscv32e/board.yml
  8. 0
      boards/qemu/qemu_riscv32e/doc/index.rst
  9. 0
      boards/qemu/qemu_riscv32e/qemu_riscv32e.dts
  10. 0
      boards/qemu/qemu_riscv32e/qemu_riscv32e.yaml
  11. 2
      boards/qemu/qemu_riscv32e/qemu_riscv32e_defconfig

11
boards/boards_legacy/riscv/qemu_riscv32e/Kconfig.board

@ -1,11 +0,0 @@ @@ -1,11 +0,0 @@
# Copyright (c) 2022 Carlo Caione <ccaione@baylibre.com>
# SPDX-License-Identifier: Apache-2.0
config BOARD_QEMU_RISCV32E
bool "QEMU RISCV32E target"
depends on SOC_RISCV_VIRT
select QEMU_TARGET
select HAS_COVERAGE_SUPPORT
select RISCV_ISA_RV32E
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI

13
boards/boards_legacy/riscv/qemu_riscv32e/Kconfig.defconfig

@ -1,13 +0,0 @@ @@ -1,13 +0,0 @@
# Copyright (c) 2022 Carlo Caione <ccaione@baylibre.com>
# SPDX-License-Identifier: Apache-2.0
config BUILD_OUTPUT_BIN
default n
config BOARD
default "qemu_riscv32e" if BOARD_QEMU_RISCV32E
# Use thread local storage by default so that
# this feature gets more CI coverage.
config THREAD_LOCAL_STORAGE
default y

5
boards/qemu/qemu_riscv32e/Kconfig

@ -0,0 +1,5 @@ @@ -0,0 +1,5 @@
# Copyright (c) 2024 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: Apache-2.0
config BOARD_QEMU_RISCV32E
select QEMU_TARGET

16
boards/qemu/qemu_riscv32e/Kconfig.defconfig

@ -0,0 +1,16 @@ @@ -0,0 +1,16 @@
# Copyright (c) 2024 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: Apache-2.0
if BOARD_QEMU_RISCV32E
# Use thread local storage by default so that this feature gets more CI coverage.
config THREAD_LOCAL_STORAGE
default y
config BUILD_OUTPUT_BIN
default n
config HAS_COVERAGE_SUPPORT
default y
endif # BOARD_QEMU_RISCV32E

5
boards/qemu/qemu_riscv32e/Kconfig.qemu_riscv32e

@ -0,0 +1,5 @@ @@ -0,0 +1,5 @@
# Copyright (c) 2024 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: Apache-2.0
config BOARD_QEMU_RISCV32E
select SOC_QEMU_VIRT_RISCV32E

0
boards/boards_legacy/riscv/qemu_riscv32e/board.cmake → boards/qemu/qemu_riscv32e/board.cmake

5
boards/qemu/qemu_riscv32e/board.yml

@ -0,0 +1,5 @@ @@ -0,0 +1,5 @@
board:
name: qemu_riscv32e
vendor: qemu
socs:
- name: qemu_virt_riscv32e

0
boards/boards_legacy/riscv/qemu_riscv32e/doc/index.rst → boards/qemu/qemu_riscv32e/doc/index.rst

0
boards/boards_legacy/riscv/qemu_riscv32e/qemu_riscv32e.dts → boards/qemu/qemu_riscv32e/qemu_riscv32e.dts

0
boards/boards_legacy/riscv/qemu_riscv32e/qemu_riscv32e.yaml → boards/qemu/qemu_riscv32e/qemu_riscv32e.yaml

2
boards/boards_legacy/riscv/qemu_riscv32e/qemu_riscv32e_defconfig → boards/qemu/qemu_riscv32e/qemu_riscv32e_defconfig

@ -1,7 +1,5 @@ @@ -1,7 +1,5 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_SOC_RISCV_VIRT=y
CONFIG_BOARD_QEMU_RISCV32E=y
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
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