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Move and convert to HWMv2 `intel_socfpga_agilex5_socdk` board configuration. Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>pull/69687/head
9 changed files with 21 additions and 22 deletions
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# Copyright (c) 2022 Intel Corporation |
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# SPDX-License-Identifier: Apache-2.0 |
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config BOARD_INTEL_SOCFPGA_AGILEX5_SOCDK |
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bool "Intel SoC FPGA Development Kit (Agilex5)" |
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select HAS_COVERAGE_SUPPORT |
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depends on SOC_AGILEX5 |
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# Copyright (c) 2022 Intel Corporation |
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# SPDX-License-Identifier: Apache-2.0 |
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config BOARD |
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default "intel_socfpga_agilex5_socdk" |
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depends on BOARD_INTEL_SOCFPGA_AGILEX5_SOCDK |
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config MAX_THREAD_BYTES |
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default 5 |
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# Copyright (c) 2022-2024 Intel Corporation |
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# SPDX-License-Identifier: Apache-2.0 |
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config HAS_COVERAGE_SUPPORT |
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default y |
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config MAX_THREAD_BYTES |
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default 5 |
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# Copyright (c) 2022-2024 Intel Corporation |
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# SPDX-License-Identifier: Apache-2.0 |
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config BOARD_INTEL_SOCFPGA_AGILEX5_SOCDK |
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select SOC_AGILEX5 |
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help |
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Intel SoC FPGA Development Kit (Agilex5) |
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board: |
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name: intel_socfpga_agilex5_socdk |
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socs: |
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- name: intel_socfpga_agilex5 |
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# Copyright (c) 2023 Intel Corporation |
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# Copyright (c) 2023-2024 Intel Corporation |
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# SPDX-License-Identifier: Apache-2.0 |
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# The Zephyr build from this defconfig is expected to boot from |
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# Intel Arm Trusted Firmware (ATF). |
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# Boot Flow is: ATF BL21 -> ATF BL31 -> Zephyr |
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CONFIG_SOC_SERIES_AGILEX5=y |
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CONFIG_SOC_AGILEX5=y |
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CONFIG_BOARD_INTEL_SOCFPGA_AGILEX5_SOCDK=y |
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# Compiler Options |
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CONFIG_FORTIFY_SOURCE_RUN_TIME=y |
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