Browse Source
Remove the entire soc/soc_legacy/arm/st_stm32 folder Signed-off-by: Francois Ramu <francois.ramu@st.com>pull/69687/head
Francois Ramu
1 year ago
committed by
Carles Cufi
15 changed files with 0 additions and 810 deletions
@ -1,6 +0,0 @@
@@ -1,6 +0,0 @@
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# SPDX-License-Identifier: Apache-2.0 |
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add_subdirectory(${SOC_SERIES}) |
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add_subdirectory(common) |
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zephyr_include_directories(common) |
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# ST Microelectronics STM32 MCU line |
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# Copyright (c) 2016 Open-RnD Sp. z o.o. |
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# SPDX-License-Identifier: Apache-2.0 |
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config SOC_FAMILY_STM32 |
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bool |
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select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE |
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select STM32_ENABLE_DEBUG_SLEEP_STOP if DEBUG || ZTEST |
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select BUILD_OUTPUT_HEX |
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if SOC_FAMILY_STM32 |
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config SOC_FAMILY |
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string |
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default "st_stm32" |
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config STM32_ENABLE_DEBUG_SLEEP_STOP |
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bool "Allow debugger attach in stop/sleep Mode" |
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help |
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Some STM32 parts disable the DBGMCU in sleep/stop modes because |
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of power consumption. As a side-effects this prevents |
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debuggers from attaching w/o resetting the target. This |
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effectivly destroys the use-case of `west attach`. Also |
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SEGGER RTT and similar technologies need this. |
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source "soc/soc_legacy/arm/st_stm32/*/Kconfig.soc" |
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endif # SOC_FAMILY_STM32 |
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@@ -1,3 +0,0 @@
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# SPDX-License-Identifier: Apache-2.0 |
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source "soc/soc_legacy/arm/st_stm32/*/Kconfig.defconfig.series" |
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# ST Microelectronics STM32 MCU line |
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# Copyright (c) 2016 Open-RnD Sp. z o.o. |
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# SPDX-License-Identifier: Apache-2.0 |
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source "soc/soc_legacy/arm/st_stm32/*/Kconfig.series" |
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@ -1,14 +0,0 @@
@@ -1,14 +0,0 @@
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# SPDX-License-Identifier: Apache-2.0 |
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zephyr_sources(stm32cube_hal.c) |
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zephyr_linker_sources_ifdef(CONFIG_STM32_CCM SECTIONS ccm.ld) |
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zephyr_sources_ifdef(CONFIG_STM32_BACKUP_SRAM stm32_backup_sram.c) |
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zephyr_linker_sources_ifdef(CONFIG_STM32_BACKUP_SRAM SECTIONS stm32_backup_sram.ld) |
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zephyr_sources(soc_config.c) |
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if (NOT CONFIG_DEBUG AND CONFIG_PM) |
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zephyr_sources_ifdef(CONFIG_DT_HAS_SWJ_CONNECTOR_ENABLED pm_debug_swj.c) |
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endif() |
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@ -1,65 +0,0 @@
@@ -1,65 +0,0 @@
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# ST Microelectronics STM32 all MCU lines |
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# Copyright (c) 2017, I-SENSE group of ICCS |
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# SPDX-License-Identifier: Apache-2.0 |
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# Here are set all the Kconfig symbols common to the whole STM32 family |
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if SOC_FAMILY_STM32 |
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config CORTEX_M_SYSTICK |
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default n if STM32_LPTIM_TIMER |
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DT_STM32_RCC_PATH := $(dt_nodelabel_path,rcc) |
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DT_STM32_RCC_CLOCK_FREQ := $(dt_node_int_prop_int,$(DT_STM32_RCC_PATH),clock-frequency) |
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DT_ST_PRESCALER := st,prescaler |
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DT_STM32_LPTIM_PATH := $(dt_nodelabel_path,stm32_lp_tick_source) |
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config SYS_CLOCK_HW_CYCLES_PER_SEC |
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default "$(DT_STM32_RCC_CLOCK_FREQ)" if "$(dt_nodelabel_enabled,rcc)" |
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if LOG_BACKEND_SWO |
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config LOG_BACKEND_SWO_REF_FREQ_HZ |
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default "$(DT_STM32_RCC_CLOCK_FREQ)" if "$(dt_nodelabel_enabled,rcc)" |
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endif # LOG_BACKEND_SWO |
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# set the tick per sec as a divider of the LPTIM clock source |
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# with a minimum value of 4096 for SYS_CLOCK_TICKS_PER_SEC to keep |
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# SYS_CLOCK_TICKS_PER_SEC not too high compared to the LPTIM counter clock |
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config SYS_CLOCK_TICKS_PER_SEC |
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default 4096 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" < 16 |
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default 2048 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 16 |
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default 1024 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 32 |
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default 512 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 64 |
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default 256 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 128 |
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depends on STM32_LPTIM_TIMER && STM32_LPTIM_CLOCK_LSE |
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config SYS_CLOCK_TICKS_PER_SEC |
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default 4000 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" < 16 |
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default 2000 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 16 |
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default 1000 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 32 |
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default 500 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 64 |
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default 250 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 128 |
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depends on STM32_LPTIM_TIMER && STM32_LPTIM_CLOCK_LSI |
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choice STM32_LPTIM_CLOCK |
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default STM32_LPTIM_CLOCK_LSE if "$(dt_node_ph_array_prop_int,$(DT_STM32_LPTIM_PATH),clocks,1,bus)" = 2 |
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default STM32_LPTIM_CLOCK_LSI if "$(dt_node_ph_array_prop_int,$(DT_STM32_LPTIM_PATH),clocks,1,bus)" = 3 |
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endchoice |
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config CLOCK_CONTROL_STM32_CUBE |
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default y |
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depends on CLOCK_CONTROL |
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config CLOCK_CONTROL_INIT_PRIORITY |
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default 1 |
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depends on CLOCK_CONTROL |
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config MEMC_STM32 |
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default y |
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depends on MEMC |
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endif # SOC_FAMILY_STM32 |
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@ -1,72 +0,0 @@
@@ -1,72 +0,0 @@
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# ST Microelectronics Common Kconfig |
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# Copyright (c) 2019 Linaro Ltd. |
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# SPDX-License-Identifier: Apache-2.0 |
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# Workaround for not being able to have commas in macro arguments |
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DT_CHOSEN_Z_CCM := zephyr,ccm |
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config STM32_CCM |
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def_bool $(dt_chosen_enabled,$(DT_CHOSEN_Z_CCM)) |
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config STM32_BACKUP_SRAM |
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bool "STM32 Backup SRAM" |
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depends on DT_HAS_ST_STM32_BACKUP_SRAM_ENABLED |
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help |
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Enable support for STM32 backup SRAM. |
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config USE_STM32_ASSERT |
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depends on ASSERT |
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bool "STM32Cube HAL and LL drivers asserts" |
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help |
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Enable asserts in STM32Cube HAL and LL drivers. |
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config SWJ_ANALOG_PRIORITY |
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int "SWJ DP port to analog routine initialization priority" |
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default 49 |
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help |
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Initialization priority of the routine within the PRE_KERNEL1 level. |
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This priority must be greater than GPIO_INIT_PRIORITY and lower than |
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UART_INIT_PRIORITY. |
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choice POWER_SUPPLY_CHOICE |
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prompt "STM32 power supply configuration" |
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default POWER_SUPPLY_LDO |
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depends on SOC_SERIES_STM32H7X || SOC_SERIES_STM32U5X || \ |
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SOC_STM32WBA55XX |
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config POWER_SUPPLY_LDO |
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bool "LDO supply" |
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config POWER_SUPPLY_DIRECT_SMPS |
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bool "Direct SMPS supply" |
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config POWER_SUPPLY_SMPS_1V8_SUPPLIES_LDO |
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bool "SMPS 1.8V supplies LDO (no external supply)" |
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depends on !SOC_SERIES_STM32U5X && !SOC_SERIES_STM32WBAX |
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config POWER_SUPPLY_SMPS_2V5_SUPPLIES_LDO |
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bool "SMPS 2.5V supplies LDO (no external supply)" |
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depends on !SOC_SERIES_STM32U5X && !SOC_SERIES_STM32WBAX |
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config POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT_AND_LDO |
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bool "External SMPS 1.8V supply, supplies LDO" |
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depends on !SOC_SERIES_STM32U5X && !SOC_SERIES_STM32WBAX |
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config POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT_AND_LDO |
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bool "External SMPS 2.5V supply, supplies LDO" |
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depends on !SOC_SERIES_STM32U5X && !SOC_SERIES_STM32WBAX |
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config POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT |
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bool "External SMPS 1.8V supply and bypass" |
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depends on !SOC_SERIES_STM32U5X && !SOC_SERIES_STM32WBAX |
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config POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT |
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bool "External SMPS 2.5V supply and bypass" |
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depends on !SOC_SERIES_STM32U5X && !SOC_SERIES_STM32WBAX |
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config POWER_SUPPLY_EXTERNAL_SOURCE |
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bool "Bypass" |
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depends on !SOC_SERIES_STM32U5X && !SOC_SERIES_STM32WBAX |
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endchoice |
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@@ -1,34 +0,0 @@
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/* Copied from linker.ld */ |
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GROUP_START(CCM) |
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SECTION_PROLOGUE(_CCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(4)) |
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{ |
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__ccm_start = .; |
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__ccm_bss_start = .; |
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*(.ccm_bss) |
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*(".ccm_bss.*") |
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__ccm_bss_end = .; |
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} GROUP_LINK_IN(LINKER_DT_NODE_REGION_NAME(DT_CHOSEN(zephyr_ccm))) |
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SECTION_PROLOGUE(_CCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(4)) |
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{ |
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__ccm_noinit_start = .; |
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*(.ccm_noinit) |
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*(".ccm_noinit.*") |
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__ccm_noinit_end = .; |
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} GROUP_LINK_IN(LINKER_DT_NODE_REGION_NAME(DT_CHOSEN(zephyr_ccm))) |
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SECTION_PROLOGUE(_CCM_DATA_SECTION_NAME,,SUBALIGN(4)) |
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{ |
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__ccm_data_start = .; |
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*(.ccm_data) |
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*(".ccm_data.*") |
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__ccm_data_end = .; |
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} GROUP_LINK_IN(LINKER_DT_NODE_REGION_NAME(DT_CHOSEN(zephyr_ccm)) AT> ROMABLE_REGION) |
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__ccm_end = .; |
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__ccm_data_rom_start = LOADADDR(_CCM_DATA_SECTION_NAME); |
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GROUP_END(CCM) |
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@@ -1,120 +0,0 @@
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/*
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* Copyright (c) 2020 Linaro Ltd. |
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* Copyright (c) 2021 Nordic Semiconductor ASA |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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/**
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* @file |
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* STM32 SoC specific helpers for pinctrl driver |
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*/ |
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#ifndef ZEPHYR_SOC_ARM_ST_STM32_COMMON_PINCTRL_SOC_H_ |
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#define ZEPHYR_SOC_ARM_ST_STM32_COMMON_PINCTRL_SOC_H_ |
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#include <zephyr/devicetree.h> |
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#include <zephyr/types.h> |
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#ifdef CONFIG_SOC_SERIES_STM32F1X |
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#include <zephyr/dt-bindings/pinctrl/stm32f1-pinctrl.h> |
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#else |
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#include <zephyr/dt-bindings/pinctrl/stm32-pinctrl.h> |
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#endif |
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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/** @cond INTERNAL_HIDDEN */ |
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/** Type for STM32 pin. */ |
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typedef struct pinctrl_soc_pin { |
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/** Pinmux settings (port, pin and function). */ |
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uint32_t pinmux; |
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/** Pin configuration (bias, drive and slew rate). */ |
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uint32_t pincfg; |
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} pinctrl_soc_pin_t; |
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/**
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* @brief Utility macro to initialize pinmux field in #pinctrl_pin_t. |
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* |
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* @param node_id Node identifier. |
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*/ |
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#define Z_PINCTRL_STM32_PINMUX_INIT(node_id) DT_PROP(node_id, pinmux) |
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/**
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* @brief Definitions used to initialize fields in #pinctrl_pin_t |
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*/ |
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#define STM32_NO_PULL 0x0 |
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#define STM32_PULL_UP 0x1 |
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#define STM32_PULL_DOWN 0x2 |
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#define STM32_PUSH_PULL 0x0 |
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#define STM32_OPEN_DRAIN 0x1 |
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#define STM32_OUTPUT_LOW 0x0 |
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#define STM32_OUTPUT_HIGH 0x1 |
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#define STM32_GPIO_OUTPUT 0x1 |
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#ifdef CONFIG_SOC_SERIES_STM32F1X |
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/**
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* @brief Utility macro to initialize pincfg field in #pinctrl_pin_t (F1). |
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* |
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* @param node_id Node identifier. |
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*/ |
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#define Z_PINCTRL_STM32_PINCFG_INIT(node_id) \ |
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(((STM32_NO_PULL * DT_PROP(node_id, bias_disable)) << STM32_PUPD_SHIFT) | \ |
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((STM32_PULL_UP * DT_PROP(node_id, bias_pull_up)) << STM32_PUPD_SHIFT) | \ |
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((STM32_PULL_DOWN * DT_PROP(node_id, bias_pull_down)) << STM32_PUPD_SHIFT) | \ |
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((STM32_PUSH_PULL * DT_PROP(node_id, drive_push_pull)) << STM32_CNF_OUT_0_SHIFT) | \ |
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((STM32_OPEN_DRAIN * DT_PROP(node_id, drive_open_drain)) << STM32_CNF_OUT_0_SHIFT) | \ |
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((STM32_OUTPUT_LOW * DT_PROP(node_id, output_low)) << STM32_ODR_SHIFT) | \ |
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((STM32_OUTPUT_HIGH * DT_PROP(node_id, output_high)) << STM32_ODR_SHIFT) | \ |
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(DT_ENUM_IDX(node_id, slew_rate) << STM32_MODE_OSPEED_SHIFT)) |
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#else |
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/**
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* @brief Utility macro to initialize pincfg field in #pinctrl_pin_t (non-F1). |
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* |
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* @param node_id Node identifier. |
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*/ |
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#define Z_PINCTRL_STM32_PINCFG_INIT(node_id) \ |
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(((STM32_NO_PULL * DT_PROP(node_id, bias_disable)) << STM32_PUPDR_SHIFT) | \ |
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((STM32_PULL_UP * DT_PROP(node_id, bias_pull_up)) << STM32_PUPDR_SHIFT) | \ |
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((STM32_PULL_DOWN * DT_PROP(node_id, bias_pull_down)) << STM32_PUPDR_SHIFT) | \ |
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((STM32_PUSH_PULL * DT_PROP(node_id, drive_push_pull)) << STM32_OTYPER_SHIFT) | \ |
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((STM32_OPEN_DRAIN * DT_PROP(node_id, drive_open_drain)) << STM32_OTYPER_SHIFT) | \ |
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((STM32_OUTPUT_LOW * DT_PROP(node_id, output_low)) << STM32_ODR_SHIFT) | \ |
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((STM32_OUTPUT_HIGH * DT_PROP(node_id, output_high)) << STM32_ODR_SHIFT) | \ |
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((STM32_GPIO_OUTPUT * DT_PROP(node_id, output_low)) << STM32_MODER_SHIFT) | \ |
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((STM32_GPIO_OUTPUT * DT_PROP(node_id, output_high)) << STM32_MODER_SHIFT) | \ |
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(DT_ENUM_IDX(node_id, slew_rate) << STM32_OSPEEDR_SHIFT)) |
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#endif /* CONFIG_SOC_SERIES_STM32F1X */ |
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/**
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* @brief Utility macro to initialize each pin. |
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* |
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* @param node_id Node identifier. |
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* @param state_prop State property name. |
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* @param idx State property entry index. |
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*/ |
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#define Z_PINCTRL_STATE_PIN_INIT(node_id, state_prop, idx) \ |
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{ .pinmux = Z_PINCTRL_STM32_PINMUX_INIT( \ |
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DT_PROP_BY_IDX(node_id, state_prop, idx)), \ |
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.pincfg = Z_PINCTRL_STM32_PINCFG_INIT( \ |
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DT_PROP_BY_IDX(node_id, state_prop, idx)) }, |
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/**
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* @brief Utility macro to initialize state pins contained in a given property. |
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* |
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* @param node_id Node identifier. |
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* @param prop Property name describing state pins. |
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*/ |
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#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ |
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{DT_FOREACH_PROP_ELEM(node_id, prop, Z_PINCTRL_STATE_PIN_INIT)} |
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/** @endcond */ |
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#ifdef __cplusplus |
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} |
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#endif |
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#endif /* ZEPHYR_SOC_ARM_ST_STM32_COMMON_PINCTRL_SOC_H_ */ |
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@ -1,40 +0,0 @@
@@ -1,40 +0,0 @@
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/*
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* Copyright (c) 2023 STMicroelectronics |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#include <zephyr/drivers/pinctrl.h> |
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#include <zephyr/init.h> |
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#define SWJ_NODE DT_NODELABEL(swj_port) |
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PINCTRL_DT_DEFINE(SWJ_NODE); |
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const struct pinctrl_dev_config *swj_pcfg = PINCTRL_DT_DEV_CONFIG_GET(SWJ_NODE); |
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/*
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* Serial Wire / JTAG port pins are enabled as part of SoC default configuration. |
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* When debug access is not needed and in case power consumption performance is |
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* expected, configure matching pins to analog in order to save power. |
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*/ |
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static int swj_to_analog(void) |
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{ |
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int err; |
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/* Set Serial Wire / JTAG port pins to analog mode */ |
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err = pinctrl_apply_state(swj_pcfg, PINCTRL_STATE_SLEEP); |
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if (err < 0) { |
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__ASSERT(0, "SWJ pinctrl setup failed"); |
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return err; |
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} |
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return 0; |
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} |
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/* Run this routine as the earliest pin configuration in the target,
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* to avoid potential conflicts with devices accessing SWJ-DG pins for |
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* their own needs. |
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*/ |
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SYS_INIT(swj_to_analog, PRE_KERNEL_1, CONFIG_SWJ_ANALOG_PRIORITY); |
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@@ -1,116 +0,0 @@
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/*
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* Copyright (c) 2021 Andrés Manelli <am@toroid.io> |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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/** @file
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* @brief System module to support early STM32 MCU configuration |
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*/ |
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#include <zephyr/device.h> |
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#include <zephyr/init.h> |
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#include <soc.h> |
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#include <zephyr/arch/cpu.h> |
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#include <stm32_ll_system.h> |
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#include <stm32_ll_bus.h> |
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/**
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* @brief Perform SoC configuration at boot. |
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* |
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* This should be run early during the boot process but after basic hardware |
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* initialization is done. |
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* |
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* @return 0 |
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*/ |
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static int st_stm32_common_config(void) |
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{ |
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#ifdef CONFIG_LOG_BACKEND_SWO |
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/* Enable SWO trace asynchronous mode */ |
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#if defined(CONFIG_SOC_SERIES_STM32WBX) || defined(CONFIG_SOC_SERIES_STM32H5X) |
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LL_DBGMCU_EnableTraceClock(); |
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#endif |
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#if !defined(CONFIG_SOC_SERIES_STM32WBX) |
||||
LL_DBGMCU_SetTracePinAssignment(LL_DBGMCU_TRACE_ASYNCH); |
||||
#endif |
||||
#endif /* CONFIG_LOG_BACKEND_SWO */ |
||||
|
||||
#if defined(CONFIG_USE_SEGGER_RTT) |
||||
/* On some STM32 boards, for unclear reason,
|
||||
* RTT feature is working with realtime update only when |
||||
* - one of the DMA is clocked. |
||||
* See https://github.com/zephyrproject-rtos/zephyr/issues/34324
|
||||
*/ |
||||
#if defined(__HAL_RCC_DMA1_CLK_ENABLE) |
||||
__HAL_RCC_DMA1_CLK_ENABLE(); |
||||
#elif defined(__HAL_RCC_GPDMA1_CLK_ENABLE) |
||||
__HAL_RCC_GPDMA1_CLK_ENABLE(); |
||||
#endif /* __HAL_RCC_DMA1_CLK_ENABLE */ |
||||
|
||||
/* On some STM32 boards, for unclear reason,
|
||||
* RTT feature is working with realtime update only when |
||||
* - one of the DBGMCU bit STOP/STANDBY/SLEEP is set |
||||
* See https://github.com/zephyrproject-rtos/zephyr/issues/34324
|
||||
*/ |
||||
#if defined(LL_APB1_GRP1_PERIPH_DBGMCU) |
||||
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_DBGMCU); |
||||
#elif defined(LL_APB1_GRP2_PERIPH_DBGMCU) |
||||
LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_DBGMCU); |
||||
#elif defined(LL_APB2_GRP1_PERIPH_DBGMCU) |
||||
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_DBGMCU); |
||||
#endif /* LL_APB1_GRP1_PERIPH_DBGMCU */ |
||||
|
||||
#endif /* CONFIG_USE_SEGGER_RTT */ |
||||
|
||||
|
||||
#if defined(CONFIG_STM32_ENABLE_DEBUG_SLEEP_STOP) |
||||
|
||||
#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32MP1X) |
||||
HAL_EnableDBGStopMode(); |
||||
#else /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32MP1X */ |
||||
#if defined(SOC_SERIES_STM32G0X) || defined(SOC_SERIES_STM32C0X) |
||||
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_DBGMCU); |
||||
LL_DBGMCU_EnableDBGStopMode(); |
||||
LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_DBGMCU); |
||||
#elif defined(SOC_SERIES_STM32F0X) |
||||
LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_DBGMCU); |
||||
LL_DBGMCU_EnableDBGStopMode(); |
||||
LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_DBGMCU); |
||||
#elif defined(SOC_SERIES_STM32L0X) |
||||
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_DBGMCU); |
||||
LL_DBGMCU_EnableDBGStopMode(); |
||||
LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_DBGMCU); |
||||
#else /* all other parts */ |
||||
LL_DBGMCU_EnableDBGStopMode(); |
||||
#endif |
||||
#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32MP1X */ |
||||
|
||||
#else |
||||
|
||||
/* keeping in mind that debugging draws a lot of power we explcitly disable when not needed */ |
||||
#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32MP1X) |
||||
HAL_DisableDBGStopMode(); |
||||
#else /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32MP1X */ |
||||
#if defined(SOC_SERIES_STM32G0X) || defined(SOC_SERIES_STM32C0X) |
||||
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_DBGMCU); |
||||
LL_DBGMCU_DisableDBGStopMode(); |
||||
LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_DBGMCU); |
||||
#elif defined(SOC_SERIES_STM32F0X) |
||||
LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_DBGMCU); |
||||
LL_DBGMCU_DisableDBGStopMode(); |
||||
LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_DBGMCU); |
||||
#elif defined(SOC_SERIES_STM32L0X) |
||||
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_DBGMCU); |
||||
LL_DBGMCU_DisableDBGStopMode(); |
||||
LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_DBGMCU); |
||||
#else /* all other parts */ |
||||
LL_DBGMCU_DisableDBGStopMode(); |
||||
#endif |
||||
#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32MP1X */ |
||||
|
||||
#endif /* CONFIG_STM32_ENABLE_DEBUG_SLEEP_STOP */ |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
SYS_INIT(st_stm32_common_config, PRE_KERNEL_1, 1); |
||||
@ -1,62 +0,0 @@
@@ -1,62 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2021 Teslabs Engineering S.L. |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
|
||||
#define DT_DRV_COMPAT st_stm32_backup_sram |
||||
|
||||
#include <zephyr/device.h> |
||||
#include <zephyr/drivers/clock_control/stm32_clock_control.h> |
||||
|
||||
#include <stm32_ll_pwr.h> |
||||
|
||||
#include <zephyr/logging/log.h> |
||||
LOG_MODULE_REGISTER(stm32_backup_sram, CONFIG_SOC_LOG_LEVEL); |
||||
|
||||
struct stm32_backup_sram_config { |
||||
struct stm32_pclken pclken; |
||||
}; |
||||
|
||||
static int stm32_backup_sram_init(const struct device *dev) |
||||
{ |
||||
const struct stm32_backup_sram_config *config = dev->config; |
||||
|
||||
int ret; |
||||
|
||||
/* enable clock for subsystem */ |
||||
const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE); |
||||
|
||||
if (!device_is_ready(clk)) { |
||||
LOG_ERR("clock control device not ready"); |
||||
return -ENODEV; |
||||
} |
||||
|
||||
ret = clock_control_on(clk, (clock_control_subsys_t)&config->pclken); |
||||
if (ret < 0) { |
||||
LOG_ERR("Could not initialize backup SRAM clock (%d)", ret); |
||||
return ret; |
||||
} |
||||
|
||||
/* enable write access to backup domain */ |
||||
LL_PWR_EnableBkUpAccess(); |
||||
while (!LL_PWR_IsEnabledBkUpAccess()) { |
||||
} |
||||
|
||||
/* enable backup sram regulator (required to retain backup SRAM content
|
||||
* while in standby or VBAT modes). |
||||
*/ |
||||
LL_PWR_EnableBkUpRegulator(); |
||||
while (!LL_PWR_IsEnabledBkUpRegulator()) { |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static const struct stm32_backup_sram_config config = { |
||||
.pclken = { .bus = DT_INST_CLOCKS_CELL(0, bus), |
||||
.enr = DT_INST_CLOCKS_CELL(0, bits) }, |
||||
}; |
||||
|
||||
DEVICE_DT_INST_DEFINE(0, stm32_backup_sram_init, NULL, NULL, &config, |
||||
POST_KERNEL, CONFIG_APPLICATION_INIT_PRIORITY, NULL); |
||||
@ -1,15 +0,0 @@
@@ -1,15 +0,0 @@
|
||||
/* |
||||
* Copyright (c) 2021 Teslabs Engineering S.L. |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
|
||||
GROUP_START(BACKUP_SRAM) |
||||
|
||||
SECTION_PROLOGUE(_STM32_BACKUP_SRAM_SECTION_NAME, (NOLOAD),) |
||||
{ |
||||
*(.stm32_backup_sram) |
||||
*(".stm32_backup_sram.*") |
||||
} GROUP_LINK_IN(BACKUP_SRAM) |
||||
|
||||
GROUP_END(BACKUP_SRAM) |
||||
@ -1,175 +0,0 @@
@@ -1,175 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2019 STMicroelectronics |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
#ifndef ZEPHYR_INCLUDE_DRIVERS_HSEM_STM32_HSEM_H_ |
||||
#define ZEPHYR_INCLUDE_DRIVERS_HSEM_STM32_HSEM_H_ |
||||
|
||||
#include <soc.h> |
||||
#include <stm32_ll_hsem.h> |
||||
#include <zephyr/kernel.h> |
||||
|
||||
#if defined(CONFIG_SOC_SERIES_STM32WBX) || defined(CONFIG_STM32H7_DUAL_CORE) |
||||
/** HW semaphore Complement ID list defined in hw_conf.h from STM32WB
|
||||
* and used also for H7 dualcore targets |
||||
*/ |
||||
/**
|
||||
* Index of the semaphore used by CPU2 to prevent the CPU1 to either write or |
||||
* erase data in flash. The CPU1 shall not either write or erase in flash when |
||||
* this semaphore is taken by the CPU2. When the CPU1 needs to either write or |
||||
* erase in flash, it shall first get the semaphore and release it just |
||||
* after writing a raw (64bits data) or erasing one sector. |
||||
* On v1.4.0 and older CPU2 wireless firmware, this semaphore is unused and |
||||
* CPU2 is using PES bit. By default, CPU2 is using the PES bit to protect its |
||||
* timing. The CPU1 may request the CPU2 to use the semaphore instead of the |
||||
* PES bit by sending the system command SHCI_C2_SetFlashActivityControl() |
||||
*/ |
||||
#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID 7U |
||||
|
||||
/**
|
||||
* Index of the semaphore used by CPU1 to prevent the CPU2 to either write or |
||||
* erase data in flash. In order to protect its timing, the CPU1 may get this |
||||
* semaphore to prevent the CPU2 to either write or erase in flash |
||||
* (as this will stall both CPUs) |
||||
* The PES bit shall not be used as this may stall the CPU2 in some cases. |
||||
*/ |
||||
#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID 6U |
||||
|
||||
/**
|
||||
* Index of the semaphore used to manage the CLK48 clock configuration |
||||
* When the USB is required, this semaphore shall be taken before configuring |
||||
* the CLK48 for USB and should be released after the application switch OFF |
||||
* the clock when the USB is not used anymore. When using the RNG, it is good |
||||
* enough to use CFG_HW_RNG_SEMID to control CLK48. |
||||
* More details in AN5289 |
||||
*/ |
||||
#define CFG_HW_CLK48_CONFIG_SEMID 5U |
||||
#define CFG_HW_RCC_CRRCR_CCIPR_SEMID CFG_HW_CLK48_CONFIG_SEMID |
||||
|
||||
/* Index of the semaphore used to manage the entry Stop Mode procedure */ |
||||
#define CFG_HW_ENTRY_STOP_MODE_SEMID 4U |
||||
#define CFG_HW_ENTRY_STOP_MODE_MASK_SEMID (1U << CFG_HW_ENTRY_STOP_MODE_SEMID) |
||||
|
||||
/* Index of the semaphore used to access the RCC */ |
||||
#define CFG_HW_RCC_SEMID 3U |
||||
|
||||
/* Index of the semaphore used to access the FLASH */ |
||||
#define CFG_HW_FLASH_SEMID 2U |
||||
|
||||
/* Index of the semaphore used to access the PKA */ |
||||
#define CFG_HW_PKA_SEMID 1U |
||||
|
||||
/* Index of the semaphore used to access the RNG */ |
||||
#define CFG_HW_RNG_SEMID 0U |
||||
|
||||
/** Index of the semaphore used to access GPIO */ |
||||
#define CFG_HW_GPIO_SEMID 8U |
||||
|
||||
/** Index of the semaphore used to access the EXTI */ |
||||
#define CFG_HW_EXTI_SEMID 9U |
||||
|
||||
/** Index of the semaphore for CPU1 mailbox */ |
||||
#define CFG_HW_IPM_CPU1_SEMID 10U |
||||
|
||||
/** Index of the semaphore for CPU2 mailbox */ |
||||
#define CFG_HW_IPM_CPU2_SEMID 11U |
||||
|
||||
#elif defined(CONFIG_SOC_SERIES_STM32MP1X) |
||||
/** HW semaphore from STM32MP1
|
||||
* EXTI and GPIO are inherited from STM32MP1 Linux. |
||||
* Other SEMID are not used by linux and must not be used here, |
||||
* but reserved for MPU. |
||||
*/ |
||||
/** Index of the semaphore used to access GPIO */ |
||||
#define CFG_HW_GPIO_SEMID 0U |
||||
|
||||
/** Index of the semaphore used to access the EXTI */ |
||||
#define CFG_HW_EXTI_SEMID 1U |
||||
|
||||
#else |
||||
/** Fake semaphore ID definition for compilation purpose only */ |
||||
#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID 0U |
||||
#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID 0U |
||||
#define CFG_HW_CLK48_CONFIG_SEMID 0U |
||||
#define CFG_HW_RCC_CRRCR_CCIPR_SEMID 0U |
||||
#define CFG_HW_ENTRY_STOP_MODE_SEMID 0U |
||||
#define CFG_HW_RCC_SEMID 0U |
||||
#define CFG_HW_FLASH_SEMID 0U |
||||
#define CFG_HW_PKA_SEMID 0U |
||||
#define CFG_HW_RNG_SEMID 0U |
||||
#define CFG_HW_GPIO_SEMID 0U |
||||
#define CFG_HW_EXTI_SEMID 0U |
||||
#define CFG_HW_IPM_CPU1_SEMID 0U |
||||
#define CFG_HW_IPM_CPU2_SEMID 0U |
||||
|
||||
#endif /* CONFIG_SOC_SERIES_STM32WBX || CONFIG_STM32H7_DUAL_CORE */ |
||||
|
||||
/** Hardware Semaphore wait forever value */ |
||||
#define HSEM_LOCK_WAIT_FOREVER 0xFFFFFFFFU |
||||
/** Hardware Semaphore default retry value */ |
||||
#define HSEM_LOCK_DEFAULT_RETRY 0x100000U |
||||
|
||||
/**
|
||||
* @brief Lock Hardware Semaphore |
||||
*/ |
||||
static inline void z_stm32_hsem_lock(uint32_t hsem, uint32_t retry) |
||||
{ |
||||
#if defined(CONFIG_SOC_SERIES_STM32WBX) || defined(CONFIG_STM32H7_DUAL_CORE) \ |
||||
|| defined(CONFIG_SOC_SERIES_STM32MP1X) |
||||
|
||||
while (LL_HSEM_1StepLock(HSEM, hsem)) { |
||||
if (retry != HSEM_LOCK_WAIT_FOREVER) { |
||||
retry--; |
||||
if (retry == 0) { |
||||
k_panic(); |
||||
} |
||||
} |
||||
} |
||||
#endif /* CONFIG_SOC_SERIES_STM32WBX || CONFIG_STM32H7_DUAL_CORE || ... */ |
||||
} |
||||
|
||||
/**
|
||||
* @brief Try to lock Hardware Semaphore |
||||
*/ |
||||
static inline int z_stm32_hsem_try_lock(uint32_t hsem) |
||||
{ |
||||
#if defined(CONFIG_SOC_SERIES_STM32WBX) || defined(CONFIG_STM32H7_DUAL_CORE) \ |
||||
|| defined(CONFIG_SOC_SERIES_STM32MP1X) |
||||
|
||||
if (LL_HSEM_1StepLock(HSEM, hsem)) { |
||||
return -EAGAIN; |
||||
} |
||||
#endif /* CONFIG_SOC_SERIES_STM32WBX || CONFIG_STM32H7_DUAL_CORE || ... */ |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Release Hardware Semaphore |
||||
*/ |
||||
static inline void z_stm32_hsem_unlock(uint32_t hsem) |
||||
{ |
||||
#if defined(CONFIG_SOC_SERIES_STM32WBX) || defined(CONFIG_STM32H7_DUAL_CORE) \ |
||||
|| defined(CONFIG_SOC_SERIES_STM32MP1X) |
||||
LL_HSEM_ReleaseLock(HSEM, hsem, 0); |
||||
#endif /* CONFIG_SOC_SERIES_STM32WBX || CONFIG_STM32H7_DUAL_CORE || ... */ |
||||
} |
||||
|
||||
/**
|
||||
* @brief Indicates whether Hardware Semaphore is owned by this core |
||||
*/ |
||||
static inline bool z_stm32_hsem_is_owned(uint32_t hsem) |
||||
{ |
||||
bool owned = false; |
||||
|
||||
#if defined(CONFIG_SOC_SERIES_STM32WBX) || defined(CONFIG_STM32H7_DUAL_CORE) \ |
||||
|| defined(CONFIG_SOC_SERIES_STM32MP1X) |
||||
|
||||
owned = LL_HSEM_GetCoreId(HSEM, hsem) == LL_HSEM_COREID; |
||||
#endif /* CONFIG_SOC_SERIES_STM32WBX || CONFIG_STM32H7_DUAL_CORE || ... */ |
||||
|
||||
return owned; |
||||
} |
||||
|
||||
#endif /* ZEPHYR_INCLUDE_DRIVERS_HSEM_STM32_HSEM_H_ */ |
||||
@ -1,53 +0,0 @@
@@ -1,53 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2018, I-SENSE group of ICCS |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
|
||||
/**
|
||||
* @file |
||||
* @brief Zephyr's implementation for STM32Cube HAL core initialization |
||||
* functions. These functions are declared as __weak in |
||||
* STM32Cube HAL in order to be overwritten in case of other |
||||
* implementations. |
||||
*/ |
||||
|
||||
#include <zephyr/kernel.h> |
||||
#include <soc.h> |
||||
/**
|
||||
* @brief This function configures the source of stm32cube time base. |
||||
* Cube HAL expects a 1ms tick which matches with k_uptime_get_32. |
||||
* Tick interrupt priority is not used |
||||
* @return HAL status |
||||
*/ |
||||
uint32_t HAL_GetTick(void) |
||||
{ |
||||
return k_uptime_get_32(); |
||||
} |
||||
|
||||
/**
|
||||
* @brief This function provides minimum delay (in milliseconds) based |
||||
* on variable incremented. |
||||
* @param Delay: specifies the delay time length, in milliseconds. |
||||
* @return None |
||||
*/ |
||||
void HAL_Delay(__IO uint32_t Delay) |
||||
{ |
||||
k_msleep(Delay); |
||||
} |
||||
|
||||
#ifdef CONFIG_USE_STM32_ASSERT |
||||
/**
|
||||
* @brief Generates an assert on STM32Cube HAL/LL assert trigger. |
||||
* @param file: specifies the file name where assert expression failed. |
||||
* @param line: specifies the line number where assert expression failed. |
||||
* @return None |
||||
*/ |
||||
void assert_failed(uint8_t *file, uint32_t line) |
||||
{ |
||||
/* Assert condition have been verified at Cube level, force
|
||||
* generation here. |
||||
*/ |
||||
__ASSERT(false, "Invalid value line %d @ %s\n", line, file); |
||||
} |
||||
#endif /* CONFIG_USE_STM32_ASSERT */ |
||||
Loading…
Reference in new issue