soc: xtensa: intel_adsp: move and convert to HWMv2

Move and convert soc/xtensa/intel_adsp SoC family configurations
to HWMv2 with its SoC series:
`ace` (INTEL_ACE) and `cavs` (INTEL_ADSP_CAVS).

Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>

soc/intel/intel_adsp/CMakeLists.txt

@@ -1,13 +1,17 @@
 # Intel ADSP SoCs family CMake file
 #
-# Copyright (c) 2020 Intel Corporation
+# Copyright (c) 2020-2024 Intel Corporation
 # SPDX-License-Identifier: Apache-2.0
 
+zephyr_include_directories(common)
+
 add_subdirectory(common)
 if(CONFIG_SOC_SERIES_INTEL_ACE)
+	zephyr_include_directories(ace)
 	add_subdirectory(ace)
 endif()
 if(CONFIG_INTEL_ADSP_CAVS)
+	zephyr_include_directories(cavs)
 	add_subdirectory(cavs)
 endif()
 zephyr_include_directories(common/include)

soc/intel/intel_adsp/Kconfig

@@ -1,6 +1,6 @@
 # Intel CAVS SoC family configuration options
 #
-# Copyright (c) 2020 Intel Corporation
+# Copyright (c) 2020-2024 Intel Corporation
 # SPDX-License-Identifier: Apache-2.0
 
 config SOC_FAMILY_INTEL_ADSP
@@ -9,16 +9,8 @@ config SOC_FAMILY_INTEL_ADSP
 	select CPU_HAS_DCACHE
 	select ARCH_HAS_USERSPACE if XTENSA_MMU
 	select CPU_CACHE_INCOHERENT
-	bool
-
-if SOC_FAMILY_INTEL_ADSP
 
-config SOC_FAMILY
+rsource "*/Kconfig"
-	string
-	default "intel_adsp"
-
-# Select SoC Part No. and configuration options
-source "soc/soc_legacy/xtensa/intel_adsp/*/Kconfig.soc"
 
 DT_COMPAT_INTEL_ADSP_HOST_IPC := intel,adsp-host-ipc
 DT_COMPAT_INTEL_ADSP_IDC := intel,adsp-idc
@@ -134,5 +126,3 @@ config ADSP_IDLE_CLOCK_GATING
 	  HW configuration of a DSP. Evry time core goes to the WAITI state
 	  (wait for interrupt) during idle, the clock can be gated (however, this
 	  does not mean that this will happen).
-
-endif # SOC_FAMILY_INTEL_ADSP

soc/intel/intel_adsp/Kconfig.defconfig

@@ -1,11 +1,11 @@
 # Intel CAVS SoC family default configuration options
 #
-# Copyright (c) 2020 Intel Corporation
+# Copyright (c) 2020-2024 Intel Corporation
 # SPDX-License-Identifier: Apache-2.0
 
 if SOC_FAMILY_INTEL_ADSP
-source "soc/soc_legacy/xtensa/intel_adsp/*/Kconfig.defconfig.series"
 
+rsource "*/Kconfig.defconfig.series"
 
 config XTENSA_RPO_CACHE
 	def_bool y

soc/intel/intel_adsp/Kconfig.soc

@@ -0,0 +1,12 @@
+# Intel CAVS SoC series selection
+#
+# Copyright (c) 2020-2024 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_INTEL_ADSP
+	bool
+
+config SOC_FAMILY
+	default "intel_adsp" if SOC_FAMILY_INTEL_ADSP
+
+rsource "*/Kconfig.soc"

soc/intel/intel_adsp/ace/Kconfig

@@ -0,0 +1,28 @@
+# Copyright (c) 2022-2024 Intel Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_INTEL_ACE
+	select SOC_FAMILY_INTEL_ADSP
+	select XTENSA
+	select XTENSA_HAL if (("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc") && ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang"))
+	select ATOMIC_OPERATIONS_BUILTIN if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc"
+	select ARCH_HAS_COHERENCE
+	select SCHED_IPI_SUPPORTED
+	select DW_ICTL_ACE
+	select SOC_HAS_RUNTIME_NUM_CPUS
+	select HAS_PM
+
+config SOC_INTEL_ACE15_MTPM
+	select SOC_SERIES_INTEL_ACE
+
+config SOC_INTEL_ACE20_LNL
+	select SOC_SERIES_INTEL_ACE
+
+config SOC_INTEL_COMM_WIDGET
+	bool "Intel Communication Widget driver"
+	default y
+	depends on DT_HAS_INTEL_ADSP_COMMUNICATION_WIDGET_ENABLED
+	help
+	  Select this to enable Intel Communication Widget driver.
+	  DSP Communication Widget is a device for generic sideband message transmit/receive.

soc/intel/intel_adsp/ace/Kconfig.defconfig.ace15_mtpm

@@ -1,13 +1,9 @@
-# Copyright (c) 2022 Intel Corporation
+# Copyright (c) 2022-2024 Intel Corporation
 # SPDX-License-Identifier: Apache-2.0
 
 
 if SOC_INTEL_ACE15_MTPM
 
-config SOC
-	string
-	default "intel_ace15_mtpm"
-
 config MP_MAX_NUM_CPUS
 	default 3
 

soc/intel/intel_adsp/ace/Kconfig.defconfig.ace20_lnl

@@ -1,13 +1,9 @@
-# Copyright (c) 2022 Intel Corporation
+# Copyright (c) 2022-2024 Intel Corporation
 # SPDX-License-Identifier: Apache-2.0
 
 
 if SOC_INTEL_ACE20_LNL
 
-config SOC
-	string
-	default "intel_ace20_lnl"
-
 config MP_MAX_NUM_CPUS
 	default 5
 

soc/intel/intel_adsp/ace/Kconfig.defconfig.series

@@ -1,16 +1,8 @@
-# Copyright (c) 2022 Intel Corporation
+# Copyright (c) 2022-2024 Intel Corporation
 # SPDX-License-Identifier: Apache-2.0
 
 if SOC_SERIES_INTEL_ACE
 
-config SOC_SERIES
-	string
-	default "ace"
-
-config SOC_TOOLCHAIN_NAME
-	string
-	default "intel_ace15_mtpm"
-
 config SMP
 	default y
 
@@ -68,6 +60,6 @@ config LOG_BACKEND_ADSP
 
 endif # LOG
 
-source "soc/soc_legacy/xtensa/intel_adsp/ace/Kconfig.defconfig.ace*"
+rsource "Kconfig.defconfig.ace*"
 
 endif # SOC_SERIES_INTEL_ACE

soc/intel/intel_adsp/ace/Kconfig.soc

@@ -0,0 +1,28 @@
+# Copyright (c) 2022-2024 Intel Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_INTEL_ACE
+	bool
+	help
+	  Intel ADSP ACE
+
+config SOC_SERIES
+	default "ace" if SOC_SERIES_INTEL_ACE
+
+config SOC_TOOLCHAIN_NAME
+	default "intel_ace15_mtpm" if SOC_SERIES_INTEL_ACE
+
+config SOC_INTEL_ACE15_MTPM
+	bool
+	help
+	  ACE 1.5 Meteor Lake PCH M
+
+config SOC_INTEL_ACE20_LNL
+	bool
+	help
+	  ACE 2.0 Lunar Lake PCH
+
+config SOC
+	default "intel_ace15_mtpm" if SOC_INTEL_ACE15_MTPM
+	default "intel_ace20_lnl" if SOC_INTEL_ACE20_LNL

soc/intel/intel_adsp/cavs/Kconfig

@@ -1,8 +1,8 @@
-# Copyright (c) 2017,2022 Intel Corporation
+# Copyright (c) 2017,2022-2024 Intel Corporation
+#
 # SPDX-License-Identifier: Apache-2.0
 
 config SOC_SERIES_INTEL_ADSP_CAVS
-	bool "Intel CAVS"
 	select SOC_FAMILY_INTEL_ADSP
 	select XTENSA
 	select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang"))
@@ -12,5 +12,8 @@ config SOC_SERIES_INTEL_ADSP_CAVS
 	select ATOMIC_OPERATIONS_ARCH if "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "xcc"
 	select ARCH_HAS_COHERENCE
 	select HAS_PM
-	help
+
-	  Intel ADSP CAVS
+config SOC_INTEL_CAVS_V25
+	select SOC_SERIES_INTEL_ADSP_CAVS
+	select XTENSA_WAITI_BUG
+	select SCHED_IPI_SUPPORTED

soc/intel/intel_adsp/cavs/Kconfig.defconfig.cavs_v25

@@ -1,15 +1,8 @@
-# Copyright (c) 2020,2022 Intel Corporation
+# Copyright (c) 2020,2022-2024 Intel Corporation
 # SPDX-License-Identifier: Apache-2.0
 
 if SOC_INTEL_CAVS_V25
 
-config SOC_TOOLCHAIN_NAME
-	string
-	default "intel_tgl_adsp"
-
-config SOC
-	default "intel_tgl_adsp"
-
 # For backward compatibility, to be removed
 config SOC_SERIES_INTEL_CAVS_V25
 	def_bool y

soc/intel/intel_adsp/cavs/Kconfig.defconfig.series

@@ -1,16 +1,13 @@
-# Copyright (c) 2020 Intel Corporation
+# Copyright (c) 2020-2024 Intel Corporation
+#
 # SPDX-License-Identifier: Apache-2.0
 
 if SOC_SERIES_INTEL_ADSP_CAVS
 
-config SOC_SERIES
-	string
-	default "cavs"
-
 config INTEL_ADSP_CAVS
 	def_bool y
 
-source "soc/soc_legacy/xtensa/intel_adsp/cavs/Kconfig.defconfig.cavs*"
+rsource "Kconfig.defconfig.cavs*"
 
 config DMA_INTEL_ADSP_GPDMA
 	default y

soc/intel/intel_adsp/cavs/Kconfig.soc

@@ -0,0 +1,22 @@
+# Copyright (c) 2020-2024 Intel Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_INTEL_ADSP_CAVS
+	bool
+	help
+	  Intel ADSP CAVS
+
+config SOC_SERIES
+	default "cavs" if SOC_SERIES_INTEL_ADSP_CAVS
+
+config SOC_INTEL_CAVS_V25
+	bool
+	help
+	  Intel Tiger Lake
+
+config SOC
+	default "intel_tgl_adsp" if SOC_INTEL_CAVS_V25
+
+config SOC_TOOLCHAIN_NAME
+	default "intel_tgl_adsp" if SOC_INTEL_CAVS_V25

soc/intel/intel_adsp/common/CMakeLists.txt

@@ -1,6 +1,6 @@
 # Intel CAVS SoC family CMake file
 #
-# Copyright (c) 2020-2022 Intel Corporation
+# Copyright (c) 2020-2024 Intel Corporation
 # SPDX-License-Identifier: Apache-2.0
 
 zephyr_interface_library_named(INTEL_ADSP_COMMON)
@@ -129,7 +129,7 @@ add_custom_target(zephyr.ri ALL
 
 # Parameters after the double dash -- are passed through to rimage.  For
 # other ways to override default rimage parameters check
-# boards/xtensa/intel_adsp_cavs25/doc/intel_adsp_generic.rst
+# boards/intel/intel_adsp_cavs25/doc/intel_adsp_generic.rst
 
 # Warning: because `west sign` can also be used interactively, using
 # ${WEST_SIGN_OPTS} like this has _higher_ precedence than `west config

soc/intel/intel_adsp/soc.yml

@@ -0,0 +1,10 @@
+family:
+  - name: intel_adsp
+    series:
+      - name: ace
+        socs:
+          - name: intel_ace15_mtpm
+          - name: intel_ace20_lnl
+      - name: cavs
+        socs:
+          - name: intel_tgl_adsp

soc/intel/intel_adsp/tools/cavstwist.sh

@@ -1,5 +1,5 @@
 #!/bin/sh
-# Copyright (c) 2022 Intel Corporation
+# Copyright (c) 2022-2024 Intel Corporation
 # SPDX-License-Identifier: Apache-2.0
 set -e
 
@@ -13,8 +13,8 @@ set -e
 #  export CAVS_RIMAGE=$HOME/rimage
 #
 #  twister -p intel_adsp_cavs25 --device-testing \
-#     --device-serial-pty=$ZEPHYR_BASE/soc/soc_legacy/xtensa/intel_adsp/tools/cavstwist.sh \
+#     --device-serial-pty=$ZEPHYR_BASE/soc/intel/intel_adsp/tools/cavstwist.sh \
-#     --west-flash=$ZEPHYR_BASE/soc/soc_legacy/xtensa/intel_adsp/tools/cavstwist.sh
+#     --west-flash=$ZEPHYR_BASE/soc/intel/intel_adsp/tools/cavstwist.sh
 #
 # The CAVS_OLD_FLASHER is necessary because now the client-server-based
 # cavstool works by default. This is to tell the build system to use
@@ -80,7 +80,7 @@ fi
 
 ########################################################################
 
-CAVSTOOL=$ZEPHYR_BASE/soc/soc_legacy/xtensa/intel_adsp/tools/cavstool.py
+CAVSTOOL=$ZEPHYR_BASE/soc/intel/intel_adsp/tools/cavstool.py
 IMAGE=$ZEPHYR_BASE/_cavstmp.ri
 IMAGE2=$ZEPHYR_BASE/_cavstmp2.ri
 

soc/soc_legacy/xtensa/intel_adsp/Kconfig.soc

@@ -1,6 +0,0 @@
-# Intel CAVS SoC series selection
-#
-# Copyright (c) 2020 Intel Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-source "soc/soc_legacy/xtensa/intel_adsp/*/Kconfig.series"

soc/soc_legacy/xtensa/intel_adsp/ace/Kconfig.series

@@ -1,16 +0,0 @@
-# Copyright (c) 2022 Intel Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_SERIES_INTEL_ACE
-	bool "Intel ACE"
-	select SOC_FAMILY_INTEL_ADSP
-	select XTENSA
-	select XTENSA_HAL if (("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc") && ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang"))
-	select ATOMIC_OPERATIONS_BUILTIN if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc"
-	select ARCH_HAS_COHERENCE
-	select SCHED_IPI_SUPPORTED
-	select DW_ICTL_ACE
-	select SOC_HAS_RUNTIME_NUM_CPUS
-	select HAS_PM
-	help
-	  Intel ADSP ACE

soc/soc_legacy/xtensa/intel_adsp/ace/Kconfig.soc

@@ -1,23 +0,0 @@
-# Copyright (c) 2022 Intel Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-choice
-	prompt "Intel ADSP SoC Selection"
-
-	config SOC_INTEL_ACE15_MTPM
-		bool "ACE 1.5 Meteor PCH M"
-		depends on SOC_SERIES_INTEL_ACE
-
-	config SOC_INTEL_ACE20_LNL
-		bool "ACE 2.0 Lunar Lake PCH"
-		depends on SOC_SERIES_INTEL_ACE
-
-endchoice
-
-config SOC_INTEL_COMM_WIDGET
-	bool "Intel Communication Widget driver"
-	default y
-	depends on DT_HAS_INTEL_ADSP_COMMUNICATION_WIDGET_ENABLED
-	help
-	  Select this to enable Intel Communication Widget driver.
-	  DSP Communication Widget is a device for generic sideband message transmit/receive.

soc/soc_legacy/xtensa/intel_adsp/cavs/Kconfig.soc

@@ -1,13 +0,0 @@
-# Copyright (c) 2020 Intel Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-choice
-	prompt "Intel CAVS SoC Selection"
-	depends on SOC_SERIES_INTEL_ADSP_CAVS
-
-config SOC_INTEL_CAVS_V25
-	bool "Intel Tiger Lake"
-	select XTENSA_WAITI_BUG
-	select SCHED_IPI_SUPPORTED
-
-endchoice