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38 lines
993 B
38 lines
993 B
/* Copyright (c) 2022 Intel Corporation |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#ifndef ZEPHYR_SOC_INTEL_ADSP_ACE_IMR_LAYOUT_H_ |
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#define ZEPHYR_SOC_INTEL_ADSP_ACE_IMR_LAYOUT_H_ |
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/* These structs and macros are from from the ROM code header |
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* on cAVS platforms, please keep them immutable |
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*/ |
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/* |
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* A magic that tells ROM to jump to imr_restore_vector instead of normal boot |
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*/ |
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#define ADSP_IMR_MAGIC_VALUE 0x02468ACE |
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#define IMR_LAYOUT_OFFSET 0x20000 |
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#define IMR_LAYOUT_ADDRESS (L3_MEM_BASE_ADDR + IMR_LAYOUT_OFFSET) |
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struct imr_header { |
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uint32_t adsp_imr_magic; |
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uint32_t structure_version; |
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uint32_t structure_size; |
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uint32_t imr_state; |
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uint32_t imr_size; |
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void *imr_restore_vector; |
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void *imr_auth_api_vector; |
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uint8_t *imr_ram_storage; |
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}; |
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struct imr_state { |
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struct imr_header header; |
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uint8_t reserved[0x1000 - sizeof(struct imr_header)]; |
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}; |
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struct imr_layout { |
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struct imr_state imr_state; |
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}; |
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#endif /* ZEPHYR_SOC_INTEL_ADSP_ACE_IMR_LAYOUT_H_ */
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