soc: espressif_esp32: Port to HWMv2

Ports the SoC configuration to hardware model version 2

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>

Kconfig.zephyr

@@ -905,7 +905,7 @@ config BOOTLOADER_SRAM_SIZE_DEPRECATED
 
 config BOOTLOADER_ESP_IDF
 	bool "ESP-IDF bootloader support"
-	depends on SOC_FAMILY_ESP32 && !BOOTLOADER_MCUBOOT && !MCUBOOT
+	depends on SOC_FAMILY_ESPRESSIF_ESP32 && !BOOTLOADER_MCUBOOT && !MCUBOOT
 	default	y
 	help
 	  This option will trigger the compilation of the ESP-IDF bootloader

drivers/hwinfo/Kconfig

@@ -159,7 +159,7 @@ config HWINFO_SMARTBOND
 config HWINFO_ESP32
 	bool "ESP32 device ID"
 	default y
-	depends on SOC_FAMILY_ESP32
+	depends on SOC_FAMILY_ESPRESSIF_ESP32
 	help
 	  Enable ESP32 hwinfo driver.
 

drivers/interrupt_controller/Kconfig.esp32

@@ -5,7 +5,7 @@
 
 config INTC_ESP32
 	bool "Interrupt allocator for Xtensa-based Espressif SoCs"
-	default y if SOC_FAMILY_ESP32 && !SOC_SERIES_ESP32C3
+	default y if SOC_FAMILY_ESPRESSIF_ESP32 && !SOC_SERIES_ESP32C3
 	help
 	  Enable custom interrupt allocator for Espressif SoCs based on Xtensa
 	  architecture.

modules/Kconfig.esp32

@@ -3,4 +3,4 @@
 
 config HAS_ESPRESSIF_HAL
 	bool
-	depends on SOC_FAMILY_ESP32
+	depends on SOC_FAMILY_ESPRESSIF_ESP32

soc/espressif/CMakeLists.txt

@@ -1,5 +1,5 @@
 # Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
 # SPDX-License-Identifier: Apache-2.0
 
-add_subdirectory(${SOC_SERIES})
 add_subdirectory(common)
+add_subdirectory(${SOC_SERIES})

soc/espressif/Kconfig

@@ -1,4 +1,8 @@
 # Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
 # SPDX-License-Identifier: Apache-2.0
 
-source "soc/soc_legacy/xtensa/espressif_esp32/*/Kconfig.series"
+if SOC_FAMILY_ESPRESSIF_ESP32
+
+rsource "*/Kconfig"
+
+endif # SOC_FAMILY_ESPRESSIF_ESP32

soc/espressif/Kconfig.defconfig

@@ -1,5 +1,8 @@
 # Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
 # SPDX-License-Identifier: Apache-2.0
 
-add_subdirectory(${SOC_SERIES})
+if SOC_FAMILY_ESPRESSIF_ESP32
-add_subdirectory(common)
+
+rsource "*/Kconfig.defconfig"
+
+endif # SOC_FAMILY_ESPRESSIF_ESP32

soc/espressif/Kconfig.soc

@@ -0,0 +1,10 @@
+# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_ESPRESSIF_ESP32
+	bool
+
+config SOC_FAMILY
+	default "espressif_esp32" if SOC_FAMILY_ESPRESSIF_ESP32
+
+rsource "*/Kconfig.soc"

soc/espressif/common/CMakeLists.txt

@@ -0,0 +1,6 @@
+# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_SOC_SERIES_ESP32 OR CONFIG_SOC_SERIES_ESP32S2 OR CONFIG_SOC_SERIES_ESP32S3)
+  zephyr_include_directories(include)
+endif()

soc/espressif/common/Kconfig

@@ -1,8 +1,6 @@
 # Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
 # SPDX-License-Identifier: Apache-2.0
 
-if SOC_FAMILY_ESP32
-
 config ESPTOOLPY_FLASHFREQ_80M
 	bool
 
@@ -12,6 +10,8 @@ config FLASH_SIZE
 config FLASH_BASE_ADDRESS
 	hex
 
+if SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
+
 config ESP_SPIRAM
 	bool "Support for external, SPI-connected RAM"
 	help
@@ -212,4 +212,4 @@ config SPIRAM
 
 endmenu # SPI RAM config
 
-endif # SOC_FAMILY_ESP32
+endif # SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3

soc/espressif/common/Kconfig.defconfig

@@ -0,0 +1,103 @@
+# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_ESP32C3
+
+config GEN_ISR_TABLES
+	default y
+
+config GEN_SW_ISR_TABLE
+	default y
+
+config GEN_IRQ_VECTOR_TABLE
+	default n
+
+config DYNAMIC_INTERRUPTS
+	default y
+
+config ISR_STACK_SIZE
+	default 2048
+
+config ATOMIC_OPERATIONS_C
+	default y
+
+config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE
+	default n
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 16000000
+
+config SYS_CLOCK_TICKS_PER_SEC
+	default 1000
+
+config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE
+	default n
+
+config CLOCK_CONTROL
+	default y
+
+if BOOTLOADER_MCUBOOT
+
+config HAS_FLASH_LOAD_OFFSET
+	default y
+
+config MCUBOOT_GENERATE_UNSIGNED_IMAGE
+	default y
+
+config MCUBOOT_GENERATE_CONFIRMED_IMAGE
+	default y
+
+config ROM_START_OFFSET
+	default 0x20
+
+endif # BOOTLOADER_MCUBOOT
+
+endif # SOC_SERIES_ESP32C3
+
+# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
+
+# Xtensa default options for ESP32 family
+config XTENSA_RESET_VECTOR
+	default n
+
+config XTENSA_USE_CORE_CRT1
+	default n
+
+config GEN_ISR_TABLES
+	default y
+
+config GEN_IRQ_VECTOR_TABLE
+	default n
+
+config CLOCK_CONTROL
+	default y
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
+
+config XTENSA_CCOUNT_HZ
+	default SYS_CLOCK_HW_CYCLES_PER_SEC
+
+config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE
+	default n
+
+if BOOTLOADER_MCUBOOT
+
+config HAS_FLASH_LOAD_OFFSET
+	default y
+
+config MCUBOOT_GENERATE_UNSIGNED_IMAGE
+	default y
+
+config MCUBOOT_GENERATE_CONFIRMED_IMAGE
+	default y
+
+config ROM_START_OFFSET
+	default 0x20
+
+endif # BOOTLOADER_MCUBOOT
+
+endif # SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3

soc/espressif/esp32/CMakeLists.txt

@@ -10,6 +10,8 @@ else()
     )
 endif()
 
+zephyr_include_directories(.)
+
 zephyr_library_sources_ifdef(CONFIG_NEWLIB_LIBC newlib_fix.c)
 
 zephyr_library_sources_ifdef(CONFIG_GDBSTUB gdbstub.c)
@@ -69,11 +71,9 @@ if(CONFIG_BOOTLOADER_ESP_IDF)
   board_finalize_runner_args(esp32 "--esp-flash-partition_table=${espidf_build_dir}/partitions_singleapp.bin")
 
   board_finalize_runner_args(esp32 "--esp-partition-table-address=0x8000")
-
 endif()
 
 if(CONFIG_MCUBOOT OR CONFIG_BOOTLOADER_ESP_IDF)
-
   if(CONFIG_BUILD_OUTPUT_BIN)
     set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
       COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/esptool_py/esptool/esptool.py
@@ -85,12 +85,10 @@ if(CONFIG_MCUBOOT OR CONFIG_BOOTLOADER_ESP_IDF)
   if(CONFIG_MCUBOOT)
     board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin")
   endif()
-
 endif()
 
 ## When building for APPCPU
 if(CONFIG_SOC_ESP32_APPCPU)
-
   if(CONFIG_BUILD_OUTPUT_BIN)
     set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
       COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/esp_bin2c_array.py
@@ -98,7 +96,6 @@ if (CONFIG_SOC_ESP32_APPCPU)
       -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.c
       -a "esp32_appcpu_fw_array")
   endif()
-
 else()
   set_property(TARGET bintools PROPERTY disassembly_flag_inline_source)
 

soc/espressif/esp32/Kconfig

@@ -1,60 +1,25 @@
 # Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
 # SPDX-License-Identifier: Apache-2.0
 
+config SOC_SERIES_ESP32
+	select XTENSA
+	select CLOCK_CONTROL
+	select DYNAMIC_INTERRUPTS
+	select ARCH_HAS_GDBSTUB
+	select ARCH_SUPPORTS_COREDUMP
+	select PINCTRL
+	select XIP if !MCUBOOT
+	select HAS_ESPRESSIF_HAL
+	select CPU_HAS_FPU
+	select HAS_PM
+	select HAS_POWEROFF
+
 if SOC_SERIES_ESP32
 
 config IDF_TARGET_ESP32
 	bool "ESP32 as target board"
 	default y
 
-config SOC_TOOLCHAIN_NAME
-	string
-	default "espressif_esp32"
-
-choice SOC_PART_NUMBER
-	prompt "ESP32 SOC/SIP Selection"
-
-	# SoC with/without embedded flash
-	config SOC_ESP32_D0WD_V3
-		bool "ESP32_D0WD_V3"
-	config SOC_ESP32_D0WDR2_V3
-		bool "ESP32_D0WDR2_V3"
-	config SOC_ESP32_U4WDH
-		bool "ESP32_U4WDH"
-	config SOC_ESP32_PICO_V3
-		bool "ESP32_PICO_V3"
-	config SOC_ESP32_PICO_V3_02
-		bool "ESP32_PICO_V3_02"
-	config SOC_ESP32_PICO_D4
-		bool "ESP32_PICO_D4"
-	# SiP with external flash / psram
-	config SOC_ESP32_WROOM_DA_N4
-		bool "ESP32_WROOM_DA_N4"
-	config SOC_ESP32_WROOM_DA_N8
-		bool "ESP32_WROOM_DA_N8"
-	config SOC_ESP32_WROOM_DA_N16
-		bool "ESP32_WROOM_DA_N16"
-	config SOC_ESP32_WROOM_32UE_N4
-		bool "ESP32_WROOM_32UE_N4"
-	config SOC_ESP32_WROOM_32UE_N8
-		bool "ESP32_WROOM_32UE_N8"
-	config SOC_ESP32_WROOM_32UE_N16
-		bool "ESP32_WROOM_32UE_N16"
-	config SOC_ESP32_WROVER_E_N4R2
-		bool "ESP32_WROVER_E_N4R2"
-	config SOC_ESP32_WROVER_E_N8R2
-		bool "ESP32_WROVER_E_N8R2"
-	config SOC_ESP32_WROVER_E_N16R2
-		bool "ESP32_WROVER_E_N16R2"
-	config SOC_ESP32_WROVER_E_N4R8
-		bool "ESP32_WROVER_E_N4R8"
-	config SOC_ESP32_WROVER_E_N8R8
-		bool "ESP32_WROVER_E_N8R8"
-	config SOC_ESP32_WROVER_E_N16R8
-		bool "ESP32_WROVER_E_N16R8"
-
-endchoice # SOC_PART_NUMBER
-
 config ESP32_APPCPU_IRAM
 	hex "ESP32 APPCPU IRAM size"
 	depends on SOC_ESP32_PROCPU || SOC_ESP32_APPCPU
@@ -69,6 +34,23 @@ config ESP32_APPCPU_DRAM
 	help
 	  Defines APPCPU DRAM area in bytes.
 
+config SOC_ESP32_PROCPU
+	bool
+	help
+	  This hidden configuration defines that build is targeted for PROCPU (core 0).
+
+config SOC_ESP32_APPCPU
+	bool
+	help
+	  This hidden configuration defines that build is targeted for APPCPU (core 1).
+
+config SOC_ENABLE_APPCPU
+	bool
+	default y
+	depends on IPM && SOC_ESP32_PROCPU
+	help
+	  This hidden configuration lets PROCPU core to map and start APPCPU whenever IPM is enabled.
+
 config ESP_SYSTEM_RTC_EXT_XTAL
 	bool
 
@@ -278,4 +260,4 @@ config ETH_DMA_TX_BUFFER_NUM
 
 endif # ESP32_EMAC config
 
-endif # SOC_SERIES_ESP32 config
+endif # SOC_SERIES_ESP32

soc/espressif/esp32/Kconfig.defconfig

@@ -3,9 +3,6 @@
 
 if SOC_SERIES_ESP32
 
-config SOC_SERIES
-	default "esp32"
-
 config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE
 	default n
 

soc/espressif/esp32/Kconfig.soc

@@ -0,0 +1,153 @@
+# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_ESP32
+	bool
+	select SOC_FAMILY_ESPRESSIF_ESP32
+	help
+	  ESP32 Series
+
+config SOC_ESP32_D0WD_V3
+	bool
+	select SOC_ESP32
+	help
+	  ESP32_D0WD_V3
+
+config SOC_ESP32_D0WDR2_V3
+	bool
+	select SOC_ESP32
+	help
+	  ESP32_D0WDR2_V3
+
+config SOC_ESP32_U4WDH
+	bool
+	select SOC_ESP32
+	help
+	  ESP32_U4WDH
+
+config SOC_ESP32_PICO_V3
+	bool
+	select SOC_ESP32
+	help
+	  ESP32_PICO_V3
+
+config SOC_ESP32_PICO_V3_02
+	bool
+	select SOC_ESP32
+	help
+	  ESP32_PICO_V3_02
+
+config SOC_ESP32_PICO_D4
+	bool
+	select SOC_ESP32
+	help
+	  ESP32_PICO_D4
+
+# SiP with external flash / psram
+config SOC_ESP32_WROOM_DA_N4
+	bool
+	select SOC_ESP32
+	help
+	  ESP32_WROOM_DA_N4
+
+config SOC_ESP32_WROOM_DA_N8
+	bool
+	select SOC_ESP32
+	help
+	  ESP32_WROOM_DA_N8
+
+config SOC_ESP32_WROOM_DA_N16
+	bool
+	select SOC_ESP32
+	help
+	  ESP32_WROOM_DA_N16
+
+config SOC_ESP32_WROOM_32UE_N4
+	bool
+	select SOC_ESP32
+	help
+	  ESP32_WROOM_32UE_N4
+
+config SOC_ESP32_WROOM_32UE_N8
+	bool
+	select SOC_ESP32
+	help
+	  ESP32_WROOM_32UE_N8
+
+config SOC_ESP32_WROOM_32UE_N16
+	bool
+	select SOC_ESP32
+	help
+	  ESP32_WROOM_32UE_N16
+
+config SOC_ESP32_WROVER_E_N4R2
+	bool
+	select SOC_ESP32
+	help
+	  ESP32_WROVER_E_N4R2
+
+config SOC_ESP32_WROVER_E_N8R2
+	bool
+	select SOC_ESP32
+	help
+	  ESP32_WROVER_E_N8R2
+
+config SOC_ESP32_WROVER_E_N16R2
+	bool
+	select SOC_ESP32
+	help
+	  ESP32_WROVER_E_N16R2
+
+config SOC_ESP32_WROVER_E_N4R8
+	bool
+	select SOC_ESP32
+	help
+	  ESP32_WROVER_E_N4R8
+
+config SOC_ESP32_WROVER_E_N8R8
+	bool
+	select SOC_ESP32
+	help
+	  ESP32_WROVER_E_N8R8
+
+config SOC_ESP32_WROVER_E_N16R8
+	bool
+	select SOC_ESP32
+	help
+	  ESP32_WROVER_E_N16R8
+
+config SOC_ESP32
+	bool
+	select SOC_SERIES_ESP32
+	help
+	  ESP32
+
+config SOC_SERIES
+	default "esp32" if SOC_SERIES_ESP32
+
+config SOC
+	default "esp32" if SOC_SERIES_ESP32
+
+config SOC_PART_NUMBER
+	default "ESP32_D0WD_V3" if SOC_ESP32_D0WD_V3
+	default "ESP32_D0WDR2_V3" if SOC_ESP32_D0WDR2_V3
+	default "ESP32_U4WDH" if SOC_ESP32_U4WDH
+	default "ESP32_PICO_V3" if SOC_ESP32_PICO_V3
+	default "ESP32_PICO_V3_02" if SOC_ESP32_PICO_V3_02
+	default "ESP32_PICO_D4" if SOC_ESP32_PICO_D4
+	default "ESP32_WROOM_DA_N4" if SOC_ESP32_WROOM_DA_N4
+	default "ESP32_WROOM_DA_N8" if SOC_ESP32_WROOM_DA_N8
+	default "ESP32_WROOM_DA_N16" if SOC_ESP32_WROOM_DA_N16
+	default "ESP32_WROOM_32UE_N4" if SOC_ESP32_WROOM_32UE_N4
+	default "ESP32_WROOM_32UE_N8" if SOC_ESP32_WROOM_32UE_N8
+	default "ESP32_WROOM_32UE_N16" if SOC_ESP32_WROOM_32UE_N16
+	default "ESP32_WROVER_E_N4R2" if SOC_ESP32_WROVER_E_N4R2
+	default "ESP32_WROVER_E_N8R2" if SOC_ESP32_WROVER_E_N8R2
+	default "ESP32_WROVER_E_N16R2" if SOC_ESP32_WROVER_E_N16R2
+	default "ESP32_WROVER_E_N4R8" if SOC_ESP32_WROVER_E_N4R8
+	default "ESP32_WROVER_E_N8R8" if SOC_ESP32_WROVER_E_N8R8
+	default "ESP32_WROVER_E_N16R8" if SOC_ESP32_WROVER_E_N16R8
+
+config SOC_TOOLCHAIN_NAME
+	string
+	default "espressif_esp32" if SOC_SERIES_ESP32

soc/espressif/esp32/default.ld

@@ -18,7 +18,7 @@
 #include <zephyr/linker/linker-tool.h>
 
 #define RAMABLE_REGION dram0_0_seg
-#ifndef CONFIG_SOC_ESP32_PROCPU
+#ifndef CONFIG_SOC_ENABLE_APPCPU
 #define RAMABLE_REGION_1 dram0_1_seg
 #else
 #define RAMABLE_REGION_1 dram0_0_seg
@@ -57,7 +57,7 @@ MEMORY
   metadata (RX): org = 0x20, len = 0x20
   ROM (RX): org = 0x40, len = FLASH_SIZE - 0x40
 
-  #ifdef CONFIG_SOC_ESP32_PROCPU
+  #ifdef CONFIG_SOC_ENABLE_APPCPU
   iram0_0_seg(RX): org = 0x40080000, len = 0x08000
   #else
   iram0_0_seg(RX): org = 0x40080000, len = IRAM_SEG_LEN
@@ -78,7 +78,7 @@ MEMORY
    */
   dram0_0_seg(RW): org = 0x3FFB0000 + CONFIG_ESP32_BT_RESERVE_DRAM, len = 0x2c200 - CONFIG_ESP32_BT_RESERVE_DRAM
 
-  #ifdef CONFIG_SOC_ESP32_PROCPU
+  #ifdef CONFIG_SOC_ENABLE_APPCPU
   dram0_shm0_seg(RW): org = 0x3FFE5230, len = 2K /* shared RAM reserved for IPM */
   dram0_sem0_seg(RW): org = 0x3FFE5A30, len = 8 /* shared data reserved for IPM data header */
   dram0_1_seg(RW): org = 0x3FFE5A38, len = 0K /* for AMP builds dram0_1 is reserved for network core */

soc/espressif/esp32/soc.c

@@ -31,9 +31,9 @@
 #include "esp_app_format.h"
 #include "hal/wdt_hal.h"
 
-#ifndef CONFIG_SOC_ESP32_PROCPU
+#ifndef CONFIG_SOC_ENABLE_APPCPU
 #include "esp_clk_internal.h"
-#endif /* CONFIG_SOC_ESP32_PROCPU */
+#endif /* CONFIG_SOC_ENABLE_APPCPU */
 
 #ifdef CONFIG_MCUBOOT
 #include "bootloader_init.h"
@@ -43,7 +43,7 @@
 extern void z_cstart(void);
 extern void esp_reset_reason_init(void);
 
-#ifdef CONFIG_SOC_ESP32_PROCPU
+#ifdef CONFIG_SOC_ENABLE_APPCPU
 extern const unsigned char esp32_appcpu_fw_array[];
 
 void IRAM_ATTR esp_start_appcpu(void)
@@ -80,7 +80,7 @@ void IRAM_ATTR esp_start_appcpu(void)
 
 	esp_appcpu_start((void *)entry_addr);
 }
-#endif /* CONFIG_SOC_ESP32_PROCPU */
+#endif /* CONFIG_SOC_ENABLE_APPCPU */
 
 /*
  * This is written in C rather than assembly since, during the port bring up,
@@ -135,7 +135,7 @@ void __attribute__((section(".iram1"))) __esp_platform_start(void)
 	wdt_hal_disable(&rtc_wdt_ctx);
 	wdt_hal_write_protect_enable(&rtc_wdt_ctx);
 
-#ifndef CONFIG_SOC_ESP32_PROCPU
+#ifdef CONFIG_SOC_ESP32_APPCPU
 	/* Configures the CPU clock, RTC slow and fast clocks, and performs
 	 * RTC slow clock calibration.
 	 */
@@ -144,7 +144,7 @@ void __attribute__((section(".iram1"))) __esp_platform_start(void)
 
 	esp_timer_early_init();
 
-#if CONFIG_SOC_ESP32_PROCPU
+#if CONFIG_SOC_ENABLE_APPCPU
 	/* start the ESP32 APP CPU */
 	esp_start_appcpu();
 #endif

soc/espressif/esp32c3/CMakeLists.txt

@@ -8,6 +8,8 @@ zephyr_sources(
   loader.c
   )
 
+zephyr_include_directories(.)
+
 zephyr_library_sources_ifdef(CONFIG_PM power.c)
 zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c)
 

soc/espressif/esp32c3/Kconfig

@@ -1,29 +1,27 @@
 # Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
 # SPDX-License-Identifier: Apache-2.0
 
+config SOC_SERIES_ESP32C3
+	select RISCV
+	select RISCV_GP
+	select DYNAMIC_INTERRUPTS
+	select CLOCK_CONTROL
+	select PINCTRL
+	select RISCV_ISA_RV32I
+	select RISCV_ISA_EXT_M
+	select RISCV_ISA_EXT_C
+	select RISCV_ISA_EXT_ZICSR
+	select HAS_ESPRESSIF_HAL
+	select XIP if !MCUBOOT
+	select HAS_PM
+	select HAS_POWEROFF
+
 if SOC_SERIES_ESP32C3
 
 config IDF_TARGET_ESP32C3
 	bool "ESP32C3 as target board"
 	default y
 
-choice SOC_PART_NUMBER
-	prompt "ESP32-C3 SOC Selection"
-	depends on SOC_SERIES_ESP32C3
-
-	config SOC_ESP32C3
-		bool "ESP32C3"
-	config SOC_ESP32C3_FX4
-		bool "ESP32C3_FX4"
-	config SOC_ESP32C3_MINI_N4
-		bool "ESP32C3_MINI_N4"
-	config SOC_ESP32C3_WROOM_02_N4
-		bool "ESP32C3_WROOM_02_N4"
-	config SOC_ESP32C3_WROOM_02_N8
-		bool "ESP32C3_WROOM_02_N8"
-
-endchoice # SOC_PART_NUMBER
-
 config ESP_SYSTEM_RTC_EXT_XTAL
 	bool
 

soc/espressif/esp32c3/Kconfig.defconfig

@@ -3,9 +3,6 @@
 
 if SOC_SERIES_ESP32C3
 
-config SOC_SERIES
-	default "esp32c3"
-
 config NUM_IRQS
 	default 62
 

soc/espressif/esp32c3/Kconfig.soc

@@ -0,0 +1,51 @@
+# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_ESP32C3
+	bool
+	select SOC_FAMILY_ESPRESSIF_ESP32
+	help
+	  ESP32C3
+
+config SOC_ESP32C3_FX4
+	bool
+	select SOC_ESP32C3
+	help
+	  ESP32C3_FX4
+
+config SOC_ESP32C3_MINI_N4
+	bool
+	select SOC_ESP32C3
+	help
+	  ESP32C3_MINI_N4
+
+config SOC_ESP32C3_WROOM_02_N4
+	bool
+	select SOC_ESP32C3
+	help
+	  ESP32C3_WROOM_02_N4
+
+config SOC_ESP32C3_WROOM_02_N8
+	bool
+	select SOC_ESP32C3
+	help
+	  ESP32C3_WROOM_02_N8
+
+config SOC_ESP32C3
+	bool
+	select SOC_SERIES_ESP32C3
+	help
+	  ESP32C3
+
+config SOC_SERIES
+	default "esp32c3" if SOC_SERIES_ESP32C3
+
+config SOC
+	default "esp32c3" if SOC_SERIES_ESP32C3
+
+config SOC_PART_NUMBER
+	default "ESP32C3_FX4" if SOC_ESP32C3_FX4
+	default "ESP32C3_MINI_N4" if SOC_ESP32C3_MINI_N4
+	default "ESP32C3_WROOM_02_N4" if SOC_ESP32C3_WROOM_02_N4
+	default "ESP32C3_WROOM_02_N8" if SOC_ESP32C3_WROOM_02_N8
+	default "ESP32C3" if SOC_ESP32C3

soc/espressif/esp32s2/CMakeLists.txt

@@ -6,6 +6,8 @@ zephyr_sources(
   loader.c
   )
 
+zephyr_include_directories(.)
+
 zephyr_library_sources_ifdef(CONFIG_NEWLIB_LIBC newlib_fix.c)
 
 zephyr_library_sources_ifdef(CONFIG_PM power.c)

soc/espressif/esp32s2/Kconfig

@@ -1,55 +1,24 @@
 # Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
 # SPDX-License-Identifier: Apache-2.0
 
+config SOC_SERIES_ESP32S2
+	select XTENSA
+	select ATOMIC_OPERATIONS_C
+	select DYNAMIC_INTERRUPTS
+	select CLOCK_CONTROL
+	select PINCTRL
+	select XIP if !MCUBOOT
+	select HAS_ESPRESSIF_HAL
+	select ARCH_SUPPORTS_COREDUMP
+	select HAS_PM
+	select HAS_POWEROFF
+
 if SOC_SERIES_ESP32S2
 
 config IDF_TARGET_ESP32S2
 	bool "ESP32S2 as target SOC"
 	default y
 
-config SOC_TOOLCHAIN_NAME
-	string
-	default "espressif_esp32s2"
-
-choice SOC_PART_NUMBER
-	prompt "ESP32-S2 SOC Selection"
-	depends on SOC_SERIES_ESP32S2
-
-	# SoC with/without embedded flash
-	config SOC_ESP32S2
-		bool "ESP32S2"
-	config SOC_ESP32S2_R2
-		bool "ESP32S2_R2"
-	config SOC_ESP32S2_FH2
-		bool "ESP32S2_FH2"
-	config SOC_ESP32S2_FH4
-		bool "ESP32S2_FH4"
-	config SOC_ESP32S2_FN4R2
-		bool "ESP32S2_FN4R2"
-	# SiP with external flash / psram
-	config SOC_ESP32S2_SOLO_N4
-		bool "ESP32S2_SOLO_N4"
-	config SOC_ESP32S2_SOLO_N8
-		bool "ESP32S2_SOLO_N8"
-	config SOC_ESP32S2_SOLO_N16
-		bool "ESP32S2_SOLO_N16"
-	config SOC_ESP32S2_SOLO_N4R2
-		bool "ESP32S2_SOLO_N4R2"
-	config SOC_ESP32S2_MINI_N4
-		bool "ESP32S2_MINI_N4"
-	config SOC_ESP32S2_MINI_N4R2
-		bool "ESP32S2_MINI_N4R2"
-	config SOC_ESP32S2_WROOM
-		bool "ESP32S2_WROOM"
-	config SOC_ESP32S2_WROVER_N4R2
-		bool "ESP32S2_WROVER_N4R2"
-	config SOC_ESP32S2_WROVER_N8R2
-		bool "ESP32S2_WROVER_N8R2"
-	config SOC_ESP32S2_WROVER_N16R2
-		bool "ESP32S2_WROVER_N16R2"
-
-endchoice # SOC_PART_NUMBER
-
 config ESP_SYSTEM_RTC_EXT_XTAL
 	bool
 

soc/espressif/esp32s2/Kconfig.defconfig

@@ -0,0 +1,24 @@
+# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_ESP32S2
+
+config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE
+	default n
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
+
+config XTENSA_CCOUNT_HZ
+	default SYS_CLOCK_HW_CYCLES_PER_SEC
+
+config ESPTOOLPY_FLASHFREQ_80M
+	default y
+
+config FLASH_SIZE
+	default $(dt_node_reg_size_int,/soc/flash-controller@3f402000/flash@0,0)
+
+config FLASH_BASE_ADDRESS
+	default $(dt_node_reg_addr_hex,/soc/flash-controller@3f402000/flash@0)
+
+endif # SOC_SERIES_ESP32S3

soc/espressif/esp32s2/Kconfig.defconfig.series

@@ -3,9 +3,6 @@
 
 if SOC_SERIES_ESP32S2
 
-config SOC_SERIES
-	default "esp32s2"
-
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
 

soc/espressif/esp32s2/Kconfig.soc

@@ -0,0 +1,126 @@
+# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_ESP32S2
+	bool
+	select SOC_FAMILY_ESPRESSIF_ESP32
+	help
+	  ESP32-S2 Series
+
+config SOC_ESP32S2_R2
+	bool
+	select SOC_ESP32S2
+	help
+	  ESP32S2_R2
+
+config SOC_ESP32S2_FH2
+	bool
+	select SOC_ESP32S2
+	help
+	  ESP32S2_FH2
+
+config SOC_ESP32S2_FH4
+	bool
+	select SOC_ESP32S2
+	help
+	  ESP32S2_FH4
+
+config SOC_ESP32S2_FN4R2
+	bool
+	select SOC_ESP32S2
+	help
+	  ESP32S2_FN4R2
+
+# SiP with external flash / psram
+config SOC_ESP32S2_SOLO_N4
+	bool
+	select SOC_ESP32S2
+	help
+	  ESP32S2_SOLO_N4
+
+config SOC_ESP32S2_SOLO_N8
+	bool
+	select SOC_ESP32S2
+	help
+	  ESP32S2_SOLO_N8
+
+config SOC_ESP32S2_SOLO_N16
+	bool
+	select SOC_ESP32S2
+	help
+	  ESP32S2_SOLO_N16
+
+config SOC_ESP32S2_SOLO_N4R2
+	bool
+	select SOC_ESP32S2
+	help
+	  ESP32S2_SOLO_N4R2
+
+config SOC_ESP32S2_MINI_N4
+	bool
+	select SOC_ESP32S2
+	help
+	  ESP32S2_MINI_N4
+
+config SOC_ESP32S2_MINI_N4R2
+	bool
+	select SOC_ESP32S2
+	help
+	  ESP32S2_MINI_N4R2
+
+config SOC_ESP32S2_WROOM
+	bool
+	select SOC_ESP32S2
+	help
+	  ESP32S2_WROOM
+
+config SOC_ESP32S2_WROVER_N4R2
+	bool
+	select SOC_ESP32S2
+	help
+	  ESP32S2_WROVER_N4R2
+
+config SOC_ESP32S2_WROVER_N8R2
+	bool
+	select SOC_ESP32S2
+	help
+	  ESP32S2_WROVER_N8R2
+
+config SOC_ESP32S2_WROVER_N16R2
+	bool
+	select SOC_ESP32S2
+	help
+	  ESP32S2_WROVER_N16R2
+
+config SOC_ESP32S2
+	bool
+	select SOC_SERIES_ESP32S2
+	help
+	  ESP32S2
+
+config SOC_SERIES
+	default "esp32s2" if SOC_SERIES_ESP32S2
+
+config SOC
+	default "esp32s2" if SOC_SERIES_ESP32S2
+
+config SOC_PART_NUMBER
+	default "ESP32S2" if SOC_ESP32S2
+	default "ESP32S2_R2" if SOC_ESP32S2_R2
+	default "ESP32S2_FH2" if SOC_ESP32S2_FH2
+	default "ESP32S2_FH4" if SOC_ESP32S2_FH4
+	default "ESP32S2_FN4R2" if SOC_ESP32S2_FN4R2
+	default "ESP32S2_SOLO_N4" if SOC_ESP32S2_SOLO_N4
+	default "ESP32S2_SOLO_N8" if SOC_ESP32S2_SOLO_N8
+	default "ESP32S2_SOLO_N16" if SOC_ESP32S2_SOLO_N16
+	default "ESP32S2_SOLO_N4R2" if SOC_ESP32S2_SOLO_N4R2
+	default "ESP32S2_MINI_N4" if SOC_ESP32S2_MINI_N4
+	default "ESP32S2_MINI_N4R2" if SOC_ESP32S2_MINI_N4R2
+	default "ESP32S2_WROOM" if SOC_ESP32S2_WROOM
+	default "ESP32S2_WROVER_N4R2" if SOC_ESP32S2_WROVER_N4R2
+	default "ESP32S2_WROVER_N8R2" if SOC_ESP32S2_WROVER_N8R2
+	default "ESP32S2_WROVER_N16R2" if SOC_ESP32S2_WROVER_N16R2
+
+config SOC_TOOLCHAIN_NAME
+	string
+	default "espressif_esp32s2" if SOC_SERIES_ESP32S2

soc/espressif/esp32s3/CMakeLists.txt

@@ -11,6 +11,8 @@ else()
     )
 endif()
 
+zephyr_include_directories(.)
+
 zephyr_library_sources_ifdef(CONFIG_NEWLIB_LIBC newlib_fix.c)
 
 # get flash size to use in esptool as string
@@ -69,7 +71,6 @@ if(CONFIG_BOOTLOADER_ESP_IDF)
 endif()
 
 if(CONFIG_MCUBOOT OR CONFIG_BOOTLOADER_ESP_IDF)
-
   if(CONFIG_BUILD_OUTPUT_BIN)
     set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
       COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/esptool_py/esptool/esptool.py
@@ -81,12 +82,10 @@ if(CONFIG_MCUBOOT OR CONFIG_BOOTLOADER_ESP_IDF)
   if(CONFIG_MCUBOOT)
     board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin")
   endif()
-
 endif()
 
 ## When building for APPCPU
 if(CONFIG_SOC_ESP32S3_APPCPU)
-
   if(CONFIG_BUILD_OUTPUT_BIN)
     set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
       COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/esp_bin2c_array.py
@@ -94,9 +93,7 @@ if (CONFIG_SOC_ESP32S3_APPCPU)
       -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.c
       -a "esp32s3_appcpu_fw_array")
   endif()
-
 else()
-
   set_property(TARGET bintools PROPERTY disassembly_flag_inline_source)
 
   # get code-partition slot0 address
@@ -110,7 +107,6 @@ else()
   board_finalize_runner_args(esp32 "--esp-boot-address=${boot_off}")
 
   board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}")
-
 endif()
 
 if(CONFIG_MCUBOOT)

soc/espressif/esp32s3/Kconfig

@@ -1,58 +1,22 @@
 # Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
 # SPDX-License-Identifier: Apache-2.0
 
+config SOC_SERIES_ESP32S3
+	select XTENSA
+	select DYNAMIC_INTERRUPTS
+	select ARCH_SUPPORTS_COREDUMP
+	select CLOCK_CONTROL
+	select PINCTRL
+	select XIP if !MCUBOOT
+	select HAS_ESPRESSIF_HAL
+	select CPU_HAS_FPU
+
 if SOC_SERIES_ESP32S3
 
 config IDF_TARGET_ESP32S3
 	bool "ESP32S3 as target SOC"
 	default y
 
-config SOC_TOOLCHAIN_NAME
-	string
-	default "espressif_esp32s3"
-
-choice SOC_PART_NUMBER
-	prompt "ESP32-S3 SOC Selection"
-
-	# SoC with/without embedded flash
-	config SOC_ESP32S3_R2
-		bool "ESP32S3_R2"
-	config SOC_ESP32S3_R8
-		bool "ESP32S3_R8"
-	config SOC_ESP32S3_R8V
-		bool "ESP32S3_R8V"
-	config SOC_ESP32S3_FN8
-		bool "ESP32S3_FN8"
-	config SOC_ESP32S3_PICO_N8R2
-		bool "ESP32S3_PICO_N8R2"
-	config SOC_ESP32S3_PICO_N8R8
-		bool "ESP32S3_PICO_N8R8"
-	# SiP with flash and/or psram
-	config SOC_ESP32S3_MINI_N8
-		bool "ESP32S3_MINI_N8"
-	config SOC_ESP32S3_MINI_N4R2
-		bool "ESP32S3_MINI_N4R2"
-	config SOC_ESP32S3_WROOM_N4
-		bool "ESP32S3_WROOM_N4"
-	config SOC_ESP32S3_WROOM_N8
-		bool "ESP32S3_WROOM_N8"
-	config SOC_ESP32S3_WROOM_N16
-		bool "ESP32S3_WROOM_N16"
-	config SOC_ESP32S3_WROOM_N4R8
-		bool "ESP32S3_WROOM_N4R8"
-	config SOC_ESP32S3_WROOM_N8R8
-		bool "ESP32S3_WROOM_N8R8"
-	config SOC_ESP32S3_WROOM_N16R8
-		bool "ESP32S3_WROOM_N16R8"
-	config SOC_ESP32S3_WROOM_N4R2
-		bool "ESP32S3_WROOM_N4R2"
-	config SOC_ESP32S3_WROOM_N8R2
-		bool "ESP32S3_WROOM_N8R2"
-	config SOC_ESP32S3_WROOM_N16R2
-		bool "ESP32S3_WROOM_N16R2"
-
-endchoice # SOC_PART_NUMBER
-
 config ESP32S3_APPCPU_IRAM
 	hex "ESP32S3 APPCPU IRAM size"
 	depends on SOC_ESP32S3_PROCPU || SOC_ESP32S3_APPCPU
@@ -67,6 +31,23 @@ config ESP32S3_APPCPU_DRAM
 	help
 	  Defines APPCPU DRAM area in bytes.
 
+config SOC_ESP32S3_PROCPU
+	bool
+	help
+	  This hidden configuration defines that build is targeted for PROCPU (core 0).
+
+config SOC_ESP32S3_APPCPU
+	bool
+	help
+	  This hidden configuration defines that build is targeted for APPCPU (core 1).
+
+config SOC_ENABLE_APPCPU
+	bool
+	default y
+	depends on IPM && SOC_ESP32S3_PROCPU
+	help
+	  This hidden configuration lets PROCPU core to map and start APPCPU whenever IPM is enabled.
+
 choice ESP32S3_RTC_CLK_SRC
 	prompt "RTC clock source"
 	default ESP32S3_RTC_CLK_SRC_INT_RC

soc/espressif/esp32s3/Kconfig.defconfig

@@ -3,9 +3,6 @@
 
 if SOC_SERIES_ESP32S3
 
-config SOC_SERIES
-	default "esp32s3"
-
 config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE
 	default n
 

soc/espressif/esp32s3/Kconfig.soc

@@ -0,0 +1,146 @@
+# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_ESP32S3
+	bool
+	select SOC_FAMILY_ESPRESSIF_ESP32
+	help
+	  ESP32-S3 Series
+
+config SOC_ESP32S3_R2
+	bool
+	select SOC_ESP32S3
+	help
+	  ESP32S3_R2
+
+config SOC_ESP32S3_R8
+	bool
+	select SOC_ESP32S3
+	help
+	  ESP32S3_R8
+
+config SOC_ESP32S3_R8V
+	bool
+	select SOC_ESP32S3
+	help
+	  ESP32S3_R8V
+
+config SOC_ESP32S3_FN8
+	bool
+	select SOC_ESP32S3
+	help
+	  ESP32S3_FN8
+
+config SOC_ESP32S3_PICO_N8R2
+	bool
+	select SOC_ESP32S3
+	help
+	  ESP32S3_PICO_N8R2
+
+config SOC_ESP32S3_PICO_N8R8
+	bool
+	select SOC_ESP32S3
+	help
+	  ESP32S3_PICO_N8R8
+
+# SiP with flash and/or psram
+config SOC_ESP32S3_MINI_N8
+	bool
+	select SOC_ESP32S3
+	help
+	  ESP32S3_MINI_N8
+
+config SOC_ESP32S3_MINI_N4R2
+	bool
+	select SOC_ESP32S3
+	help
+	  ESP32S3_MINI_N4R2
+
+config SOC_ESP32S3_WROOM_N4
+	bool
+	select SOC_ESP32S3
+	help
+	  ESP32S3_WROOM_N4
+
+config SOC_ESP32S3_WROOM_N8
+	bool
+	select SOC_ESP32S3
+	help
+	  ESP32S3_WROOM_N8
+
+config SOC_ESP32S3_WROOM_N16
+	bool
+	select SOC_ESP32S3
+	help
+	  ESP32S3_WROOM_N16
+
+config SOC_ESP32S3_WROOM_N4R8
+	bool
+	select SOC_ESP32S3
+	help
+	  ESP32S3_WROOM_N4R8
+
+config SOC_ESP32S3_WROOM_N8R8
+	bool
+	select SOC_ESP32S3
+	help
+	  ESP32S3_WROOM_N8R8
+
+config SOC_ESP32S3_WROOM_N16R8
+	bool
+	select SOC_ESP32S3
+	help
+	  ESP32S3_WROOM_N16R8
+
+config SOC_ESP32S3_WROOM_N4R2
+	bool
+	select SOC_ESP32S3
+	help
+	  ESP32S3_WROOM_N4R2
+
+config SOC_ESP32S3_WROOM_N8R2
+	bool
+	select SOC_ESP32S3
+	help
+	  ESP32S3_WROOM_N8R2
+
+config SOC_ESP32S3_WROOM_N16R2
+	bool
+	select SOC_ESP32S3
+	help
+	  ESP32S3_WROOM_N16R2
+
+config SOC_ESP32S3
+	bool
+	select SOC_SERIES_ESP32S3
+	help
+	  ESP32S3
+
+config SOC_SERIES
+	default "esp32s3" if SOC_SERIES_ESP32S3
+
+config SOC
+	default "esp32s3" if SOC_SERIES_ESP32S3
+
+config SOC_PART_NUMBER
+	default "ESP32S3_R2" if SOC_ESP32S3_R2
+	default "ESP32S3_R8" if SOC_ESP32S3_R8
+	default "ESP32S3_R8V" if SOC_ESP32S3_R8V
+	default "ESP32S3_FN8" if SOC_ESP32S3_FN8
+	default "ESP32S3_PICO_N8R2" if SOC_ESP32S3_PICO_N8R2
+	default "ESP32S3_PICO_N8R8" if SOC_ESP32S3_PICO_N8R8
+	default "ESP32S3_MINI_N8" if SOC_ESP32S3_MINI_N8
+	default "ESP32S3_MINI_N4R2" if SOC_ESP32S3_MINI_N4R2
+	default "ESP32S3_WROOM_N4" if SOC_ESP32S3_WROOM_N4
+	default "ESP32S3_WROOM_N8" if SOC_ESP32S3_WROOM_N8
+	default "ESP32S3_WROOM_N16" if SOC_ESP32S3_WROOM_N16
+	default "ESP32S3_WROOM_N4R8" if SOC_ESP32S3_WROOM_N4R8
+	default "ESP32S3_WROOM_N8R8" if SOC_ESP32S3_WROOM_N8R8
+	default "ESP32S3_WROOM_N16R8" if SOC_ESP32S3_WROOM_N16R8
+	default "ESP32S3_WROOM_N4R2" if SOC_ESP32S3_WROOM_N4R2
+	default "ESP32S3_WROOM_N8R2" if SOC_ESP32S3_WROOM_N8R2
+	default "ESP32S3_WROOM_N16R2" if SOC_ESP32S3_WROOM_N16R2
+
+config SOC_TOOLCHAIN_NAME
+	string
+	default "espressif_esp32s3" if SOC_SERIES_ESP32S3

soc/espressif/esp32s3/default.ld

@@ -57,7 +57,7 @@
 #define IROM_SEG_LEN FLASH_SIZE
 #endif
 
-#ifdef CONFIG_SOC_ESP32S3_PROCPU
+#ifdef CONFIG_SOC_ENABLE_APPCPU
 #define APPCPU_IRAM_SIZE CONFIG_ESP32S3_APPCPU_IRAM
 #define APPCPU_DRAM_SIZE CONFIG_ESP32S3_APPCPU_DRAM
 #else

soc/espressif/esp32s3/soc.c

@@ -49,7 +49,7 @@ extern int _ext_ram_bss_end;
 extern void z_cstart(void);
 extern void esp_reset_reason_init(void);
 
-#ifdef CONFIG_SOC_ESP32S3_PROCPU
+#if CONFIG_SOC_ENABLE_APPCPU
 extern const unsigned char esp32s3_appcpu_fw_array[];
 
 void IRAM_ATTR esp_start_appcpu(void)
@@ -86,7 +86,7 @@ void IRAM_ATTR esp_start_appcpu(void)
 
 	esp_appcpu_start((void *)entry_addr);
 }
-#endif /* CONFIG_SOC_ESP32S3_PROCPU*/
+#endif /* CONFIG_SOC_ENABLE_APPCPU */
 
 #ifndef CONFIG_MCUBOOT
 /*
@@ -191,7 +191,7 @@ void IRAM_ATTR __esp_platform_start(void)
 
 	esp_timer_early_init();
 
-#if CONFIG_SOC_ESP32S3_PROCPU
+#if CONFIG_SOC_ENABLE_APPCPU
 	/* start the ESP32S3 APP CPU */
 	esp_start_appcpu();
 #endif

soc/espressif/soc.yml

@@ -0,0 +1,21 @@
+family:
+- name: espressif_esp32
+  series:
+  - name: esp32
+    socs:
+    - name: esp32
+      cpuclusters:
+      - name: procpu
+      - name: appcpu
+  - name: esp32s2
+    socs:
+    - name: esp32s2
+  - name: esp32s3
+    socs:
+    - name: esp32s3
+      cpuclusters:
+      - name: procpu
+      - name: appcpu
+  - name: esp32c3
+    socs:
+    - name: esp32c3

soc/soc_legacy/riscv/espressif_esp32/Kconfig

@@ -1,16 +0,0 @@
-# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_FAMILY_ESP32
-	bool
-
-if SOC_FAMILY_ESP32
-
-config SOC_FAMILY
-	string
-	default "espressif_esp32"
-
-source "soc/soc_legacy/riscv/espressif_esp32/common/Kconfig.soc"
-source "soc/soc_legacy/riscv/espressif_esp32/*/Kconfig.soc"
-
-endif # SOC_FAMILY_ESP32

soc/soc_legacy/riscv/espressif_esp32/Kconfig.defconfig

@@ -1,5 +0,0 @@
-# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
-# SPDX-License-Identifier: Apache-2.0
-
-source "soc/soc_legacy/riscv/espressif_esp32/common/Kconfig.defconfig.series"
-source "soc/soc_legacy/riscv/espressif_esp32/*/Kconfig.defconfig.series"

soc/soc_legacy/riscv/espressif_esp32/Kconfig.soc

@@ -1,4 +0,0 @@
-# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
-# SPDX-License-Identifier: Apache-2.0
-
-source "soc/soc_legacy/riscv/espressif_esp32/*/Kconfig.series"

soc/soc_legacy/riscv/espressif_esp32/common/CMakeLists.txt

@@ -1,2 +0,0 @@
-# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
-# SPDX-License-Identifier: Apache-2.0

soc/soc_legacy/riscv/espressif_esp32/common/Kconfig.defconfig.series

@@ -1,52 +0,0 @@
-# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_FAMILY_ESP32
-
-config GEN_ISR_TABLES
-	default y
-
-config GEN_SW_ISR_TABLE
-	default y
-
-config GEN_IRQ_VECTOR_TABLE
-	default n
-
-config DYNAMIC_INTERRUPTS
-	default y
-
-config ISR_STACK_SIZE
-	default 2048
-
-config ATOMIC_OPERATIONS_C
-	default y
-
-config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE
-	default n
-
-config SYS_CLOCK_HW_CYCLES_PER_SEC
-	default 16000000
-
-config SYS_CLOCK_TICKS_PER_SEC
-	default 1000
-
-config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE
-	default n
-
-config CLOCK_CONTROL
-	default y
-
-if BOOTLOADER_MCUBOOT
-
-	config HAS_FLASH_LOAD_OFFSET
-		default y
-	config MCUBOOT_GENERATE_UNSIGNED_IMAGE
-		default y
-	config MCUBOOT_GENERATE_CONFIRMED_IMAGE
-		default y
-	config ROM_START_OFFSET
-		default 0x20
-
-endif # BOOTLOADER_MCUBOOT config
-
-endif # SOC_FAMILY_ESP32

soc/soc_legacy/riscv/espressif_esp32/common/Kconfig.soc

@@ -1,15 +0,0 @@
-# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_FAMILY_ESP32
-
-config ESPTOOLPY_FLASHFREQ_80M
-	bool
-
-config FLASH_SIZE
-	int
-
-config FLASH_BASE_ADDRESS
-	hex
-
-endif # SOC_FAMILY_ESP32

soc/soc_legacy/riscv/espressif_esp32/esp32c3/Kconfig.series

@@ -1,21 +0,0 @@
-# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_SERIES_ESP32C3
-	bool "ESP32C3"
-	select RISCV
-	select RISCV_GP
-	select DYNAMIC_INTERRUPTS
-	select CLOCK_CONTROL
-	select PINCTRL
-	select RISCV_ISA_RV32I
-	select RISCV_ISA_EXT_M
-	select RISCV_ISA_EXT_C
-	select RISCV_ISA_EXT_ZICSR
-	select HAS_ESPRESSIF_HAL
-	select SOC_FAMILY_ESP32
-	select XIP if !MCUBOOT
-	select HAS_PM
-	select HAS_POWEROFF
-	help
-	  Enable support for Espressif ESP32-C3

soc/soc_legacy/xtensa/espressif_esp32/Kconfig

@@ -1,16 +0,0 @@
-# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_FAMILY_ESP32
-	bool
-
-if SOC_FAMILY_ESP32
-
-config SOC_FAMILY
-	string
-	default "espressif_esp32"
-
-source "soc/soc_legacy/xtensa/espressif_esp32/common/Kconfig.soc"
-source "soc/soc_legacy/xtensa/espressif_esp32/*/Kconfig.soc"
-
-endif # SOC_FAMILY_ESP32

soc/soc_legacy/xtensa/espressif_esp32/Kconfig.defconfig

@@ -1,5 +0,0 @@
-# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
-# SPDX-License-Identifier: Apache-2.0
-
-source "soc/soc_legacy/xtensa/espressif_esp32/common/Kconfig.defconfig.series"
-source "soc/soc_legacy/xtensa/espressif_esp32/*/Kconfig.defconfig.series"

soc/soc_legacy/xtensa/espressif_esp32/common/CMakeLists.txt

@@ -1,4 +0,0 @@
-# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
-# SPDX-License-Identifier: Apache-2.0
-
-zephyr_include_directories(include)

soc/soc_legacy/xtensa/espressif_esp32/common/Kconfig.defconfig.series

@@ -1,44 +0,0 @@
-# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_FAMILY_ESP32
-
-# Xtensa default options for ESP32 family
-config XTENSA_RESET_VECTOR
-	default n
-
-config XTENSA_USE_CORE_CRT1
-	default n
-
-config GEN_ISR_TABLES
-	default y
-
-config GEN_IRQ_VECTOR_TABLE
-	default n
-
-config CLOCK_CONTROL
-	default y
-
-config SYS_CLOCK_HW_CYCLES_PER_SEC
-	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
-
-config XTENSA_CCOUNT_HZ
-	default SYS_CLOCK_HW_CYCLES_PER_SEC
-
-config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE
-	default n
-
-if BOOTLOADER_MCUBOOT
-
-	config HAS_FLASH_LOAD_OFFSET
-		default y
-	config MCUBOOT_GENERATE_UNSIGNED_IMAGE
-		default y
-	config MCUBOOT_GENERATE_CONFIRMED_IMAGE
-		default y
-	config ROM_START_OFFSET
-		default 0x20
-
-endif # BOOTLOADER_MCUBOOT
-
-endif # SOC_FAMILY_ESP32

soc/soc_legacy/xtensa/espressif_esp32/esp32/Kconfig.series

@@ -1,33 +0,0 @@
-# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_SERIES_ESP32
-	bool "ESP32 Series"
-	select XTENSA
-	select SOC_FAMILY_ESP32
-	select CLOCK_CONTROL
-	select DYNAMIC_INTERRUPTS
-	select ARCH_HAS_GDBSTUB
-	select ARCH_SUPPORTS_COREDUMP
-	select PINCTRL
-	select XIP if !MCUBOOT
-	select HAS_ESPRESSIF_HAL
-	select CPU_HAS_FPU
-	select HAS_PM
-	select HAS_POWEROFF
-	help
-	  Enable support for Espressif ESP32
-
-config SOC_ESP32_PROCPU
-	bool "Application runs in ESP32 PROCPU (core 0)"
-	depends on SOC_SERIES_ESP32
-	help
-	  When this SOC is enabled, it will run application on PROCPU (core 0). It will automatically
-	  enable AMP support by building, flashing and loading APPCPU (core 1) image if exists.
-
-config SOC_ESP32_APPCPU
-	bool "Application runs in ESP32 APPCPU (core 1)"
-	depends on SOC_SERIES_ESP32
-	help
-	  When this SOC is enabled, it will run application on APPCPU (core 1). It is expected that
-	  there is another image running on PROCPU (core 0) to trigger the AMP support.

soc/soc_legacy/xtensa/espressif_esp32/esp32s2/Kconfig.series

@@ -1,18 +0,0 @@
-# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_SERIES_ESP32S2
-	bool "ESP32-S2 Series"
-	select XTENSA
-	select SOC_FAMILY_ESP32
-	select ATOMIC_OPERATIONS_C
-	select DYNAMIC_INTERRUPTS
-	select CLOCK_CONTROL
-	select PINCTRL
-	select XIP if !MCUBOOT
-	select HAS_ESPRESSIF_HAL
-	select ARCH_SUPPORTS_COREDUMP
-	select HAS_PM
-	select HAS_POWEROFF
-	help
-	  Enable support for Espressif ESP32-S2

soc/soc_legacy/xtensa/espressif_esp32/esp32s3/Kconfig.series

@@ -1,28 +0,0 @@
-# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_SERIES_ESP32S3
-	bool "ESP32-S3 Series"
-	select XTENSA
-	select SOC_FAMILY_ESP32
-	select DYNAMIC_INTERRUPTS
-	select ARCH_SUPPORTS_COREDUMP
-	select CLOCK_CONTROL
-	select PINCTRL
-	select XIP if !MCUBOOT
-	select HAS_ESPRESSIF_HAL
-	select CPU_HAS_FPU
-
-config SOC_ESP32S3_PROCPU
-	bool "Application runs in ESP32S3 PROCPU (core 0)"
-	depends on SOC_SERIES_ESP32S3
-	help
-	  When this SOC is enabled, it will run application on PROCPU (core 0). It will automatically
-	  enable AMP support by building, flashing and loading APPCPU (core 1) image if exists.
-
-config SOC_ESP32S3_APPCPU
-	bool "Application runs in ESP32S3 APPCPU (core 1)"
-	depends on SOC_SERIES_ESP32S3
-	help
-	  When this SOC is enabled, it will run application on APPCPU (core 1). It is expected that
-	  there is another image running on PROCPU (core 0) to trigger the AMP support.