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81 lines
2.4 KiB
81 lines
2.4 KiB
/* |
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* Copyright (c) 2017 Intel Corporation |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#ifndef __SOC_H__ |
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#define __SOC_H__ |
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#include <soc/dport_reg.h> |
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#include <soc/rtc_cntl_reg.h> |
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#include <soc/soc_caps.h> |
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#include <esp32s3/rom/ets_sys.h> |
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#include <esp32s3/rom/spi_flash.h> |
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#include "esp32s3/rom/cache.h" |
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#include <esp_rom_uart.h> |
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#include "soc/extmem_reg.h" |
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#include "soc/cache_memory.h" |
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#include "hal/cpu_hal.h" |
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#include "hal/cpu_types.h" |
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#include <esp_rom_sys.h> |
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#include <zephyr/types.h> |
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#include <stdbool.h> |
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#include <zephyr/arch/xtensa/arch.h> |
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#include <xtensa/core-macros.h> |
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#include <esp32s3/clk.h> |
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void __esp_platform_start(void); |
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static inline void esp32_set_mask32(uint32_t v, uint32_t mem_addr) |
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{ |
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sys_write32(sys_read32(mem_addr) | v, mem_addr); |
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} |
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static inline void esp32_clear_mask32(uint32_t v, uint32_t mem_addr) |
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{ |
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sys_write32(sys_read32(mem_addr) & ~v, mem_addr); |
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} |
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static inline uint32_t esp_core_id(void) |
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{ |
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uint32_t id; |
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__asm__ volatile ( |
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"rsr.prid %0\n" |
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"extui %0,%0,13,1" : "=r" (id)); |
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return id; |
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} |
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extern void esp_rom_intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); |
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extern int esp_rom_gpio_matrix_in(uint32_t gpio, uint32_t signal_index, |
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bool inverted); |
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extern int esp_rom_gpio_matrix_out(uint32_t gpio, uint32_t signal_index, |
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bool out_inverted, |
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bool out_enabled_inverted); |
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extern void esp_rom_uart_attach(void); |
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extern void esp_rom_uart_tx_wait_idle(uint8_t uart_no); |
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extern int esp_rom_uart_tx_one_char(uint8_t chr); |
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extern int esp_rom_uart_rx_one_char(uint8_t *chr); |
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extern void esp_rom_uart_set_clock_baudrate(uint8_t uart_no, uint32_t clock_hz, uint32_t baud_rate); |
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extern void esp_rom_ets_set_appcpu_boot_addr(void *addr); |
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void esp_appcpu_start(void *entry_point); |
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extern int esp_rom_Cache_Dbus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, |
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uint32_t psize, uint32_t num, uint32_t fixed); |
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extern int esp_rom_Cache_Ibus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, |
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uint32_t psize, uint32_t num, uint32_t fixed); |
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/* ROM functions which read/write internal i2c control bus for PLL, APLL */ |
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extern uint8_t esp_rom_i2c_readReg(uint8_t block, uint8_t host_id, uint8_t reg_add); |
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extern void esp_rom_i2c_writeReg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data); |
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/* cache initialization functions */ |
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void esp_config_instruction_cache_mode(void); |
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void esp_config_data_cache_mode(void); |
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#endif /* __SOC_H__ */
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