TI MSPM0 SoC series has General Purpose Timer and Advanced control timers
with Compare block which is used to generate time expiry and output
waveform like PWM. Add driver support for MSPM0 PWM output.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
Add PWM driver for the Timer peripheral on Series 2.
The TIMER uses the high-frequency EM01 Group A clock, and has
a 16- or 32-bit counter. It supports PWM period and pulse capture
on channel 0, and PWM output on all channels.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Add PWM driver for the Low Energy Timer peripheral on Series 2.
The LETIMER runs at up to 32 kHz and has a 24-bit counter. It
only supports PWM output, it does not support input capture.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Currently there is a mismatch between the naming of the hardware and
the drivers targetting the hardware. nrf2_ is used instead of
the actual bindings names, like nrf2_audiopll instead of
nrfs_audiopll. This makes it hard to map drivers to the hardware
they are targetting.
There is historical reason for some of this, namely the same binding
name was used for different hardware, which is why nrf2_ was used
on newer platforms. This is no longer the case though, so drivers
and configs can be named according to the hardware without conflict.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
IDLEOUT presence in PWM means that there are 3 sources from which
PWM pin can be driven:
- GPIO setting when PWM peripheral is disabled.
- IDLEOUT setting when PWM is enabled.
- PWM Sequence when it is in use.
IDLEOUT setting cannot be changed after enabling PWM so it is
configured to the initial state of the pin. It means that if duty
cycle is 100%, GPIO output is set to 1 but initial pin state was 0
(IDLEOUT setting) there will be a glitch between disabling a PWM
sequence and disabling a PWM peripheral.
By default, PWM driver tries to disable PWM peripheral if all channels
are 0% or 100% duty cycle to safe power. When IDLEOUT feature is
present there will be a short glitch on channels with 100% duty cycle.
In order to avoid that CONFIG_PWM_NRFX_NO_GLITCH_DUTY_100 option is
added (enabled by default). When option is enabled 100% duty cycle
is achieved by PWM sequence and not by driving a GPIO pin. It will
consume more power in cases where all channels are 0% or 100% with
at least one channel set to 100% duty cycle.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
The period is the reload register plus 1. Adjust. Note that the
earlier code handles the cases where the pulse time is zero or equal
to the period.
Signed-off-by: Michael Hope <michaelh@juju.nz>
RC_FAST needs to be enabled and calibrated in order to be used
as clock source. Otherwise, clock source is selected but no
PWM is generated.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Add a workaround for NRF52 anomaly 78: "High current consumption when
using timer STOP task only. Use the SHUTDOWN task instead."
Signed-off-by: Sven Depoorter <svndepoorter@gmail.com>
eMios_Icu_Ip_IndexInChState is changed to
eMios_Icu_Ip_u8IndexInChState and EMIOS_ICU_BUS_F
is removed in RTD 2.0.1
Signed-off-by: Tu Nguyen Van <tu.nguyenvan@nxp.com>
Change PWM to use buffers registers instead of writing period
and compare directly. This addressses an issue when updating
period to a value less than current counter, as demonstrated
in the blinky_pwm sample running on the CYW920829M2EVK_02
board.
Signed-off-by: John Batch <john.batch@infineon.com>
The GPTM is a general purpose module with a 16 bit prescaler, 16 bit
counter, and 4 compare units that can be used for PWM generation.
Use the same style as gd32 where the timer is a counter and the PWM
mode is a child node.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Do not allow CONFIG_PM_DEVICE_SYSTEM_MANAGED when fast PWM instance
is used.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
When using low PWM frequency i.e 50Hz the resolution of pulse_cycles
got lost from converting pulse_cycles to duty cycle % and then back to
pulse_cycles again.
Furthermore TPM_UpdateChnlEdgeLevelSelect call would restart the pwm
constantly on a mcux_tpm_set_cycles call now only call
TPM_UpdateChnlEdgeLevelSelect when changing the polarity
Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
Drivers update to use shared interrupt allocator for Xtensa
and RISCV devices.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
On IMX9596 the AON/WU clocks aren't controllable are on by default.
But TPM1 and TPM3 uses the clocks, by not enabling these clocks
on both TPM1/TPM3 will initialize succesfully.
Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
- The current code will cause stall if some other subsystem (like subg)
also needs to manage pm states.
- So add a check to only re-enable suspend if it was disabled by PWM.
Signed-off-by: Ayush Singh <ayush@beagleboard.org>
Since the RA2L1 uses the macro "ICU_EVENT" instead of
"ELC_EVENT" (which is currently used) to input into
the IELSR register, the ek_ra2l1 board cannot assign
any interrupts for any driver.
This commit aim to correct the Event macro to input correct
value for IELSR register on all the Renesas SoC by using
"BSP_PRV_IELS_ENUM" macro.
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Fast PWM120 prevents GPIO from driving pin with low/high
state when PWM duty is 0% or 100%. In such case, regular
PWM signal generation needs to be used.
Signed-off-by: Michał Stasiak <michal.stasiak@nordicsemi.no>
Drop few redundant device_is_ready for functions that are only used as
argument to shell_device_filter, as shell_device_filter checks for that
alrady.
Suggested-by: Yishai Jaffe <yishai1999@gmail.com>
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add inverted flag to bindings, as pwms field is supposed
to be used by application only.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Include condition to block pwm_set operation when the same timer
is shared but a different frequency is requested. First set
operation will take precedence.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Cleanup and functions organization. Clock source selection added
to init to allow proper setting of default level when signal is
inverted.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Disable PWM output for duty 0% or 100%, to allow using max timers
resolution. Move timer reset to init function in order to ensure
smooth frequency transitions.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
At driver init channels frequency are unknown, thus timer config
may take place only at set_cycles(). To avoid phase shifts,
timers are only reconfigured if a new frequency is requested.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Set pwm init state to value defined in flags field.
Furthermore 100 percent is now actually 100 percent and not 99.
Signed-off-by: Armin Kessler <ake@espros.com>
This PR enables the PWM to be inverted by making use of the
`PWM_POLARITY_INVERTED` flag.
It also fixes an overflow bug when setting duty-cycle to 100 percent.
Signed-off-by: Armin Kessler <ake@espros.com>
This adds support PWM EMIOS for NXP S32Z SoC, both PWM pulse
generate and pulse capture are supported
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Removing period, duty and polarity configuration from
channel devicetree. At boot time, only minimal setup like
pinctrl, prescaler, etc should be initialized. PWM signal
is produced by using pwm_set* API
Also after this change, PWM period, duty are changed at the
next counter period boundary
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Refactor and merge the SoC support files for the Atmel SAM E70 and SAM V71
product series. These SoCs are part of a larger product family (SAM
E70/S70/V70/V71) and share a common set of peripherals.
Support for the two remaining product series (SAM S70/V70) is not part of
this refactoring as these will require further additions to the Atmel HAL.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Pieter De Gendt
Steven Chang
Saravanan Sekar
Aksel Skauge Mellbye
Phi Tran
Benjamin Cabé
Bjarki Arge Andreasen
Khanh Nguyen
Krzysztof Chruściński
Fin Maaß
Michael Hope
Raffael Rostagno
Sven Depoorter
Tu Nguyen Van
cyliang tw
Ruibin Chang
John Batch
Henrik Brix Andersen
Titan Chen
Peter van der Perk
Ayush Singh
Sai Santhosh Malae
Khoa Nguyen
Hieu Nguyen
Michał Stasiak
Fabio Baltieri
Armin Kessler
Dat Nguyen Duy