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The GPTM is a general purpose module with a 16 bit prescaler, 16 bit counter, and 4 compare units that can be used for PWM generation. Use the same style as gd32 where the timer is a counter and the PWM mode is a child node. Signed-off-by: Michael Hope <michaelh@juju.nz>pull/89506/head
Michael Hope
1 year ago
committed by
Benjamin Cabé
7 changed files with 236 additions and 0 deletions
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# Copyright (c) 2025 Michael Hope <michaelh@juju.nz> |
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# SPDX-License-Identifier: Apache-2.0 |
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config PWM_WCH_GPTM |
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bool "WCH General-purpose Timer (GPTM) for PWM" |
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default y |
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depends on DT_HAS_WCH_GPTM_PWM_ENABLED |
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select PINCTRL |
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help |
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PWM driver for the WCH GPTM, such as TIM2 on the CH32V003. |
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/*
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* Copyright (c) 2025 Michael Hope <michaelh@juju.nz> |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#define DT_DRV_COMPAT wch_gptm_pwm |
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#include <zephyr/drivers/clock_control.h> |
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#include <zephyr/drivers/pinctrl.h> |
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#include <zephyr/drivers/pwm.h> |
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#include <zephyr/dt-bindings/pwm/pwm.h> |
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#include <ch32fun.h> |
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/* Each of the 4 channels uses 1 byte of CHCTLR{1,2} */ |
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#define CHCTLR_CHANNEL_MASK 0xFF |
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/* 'Invalid', i.e. low before any inversion. */ |
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#define CHCTLR_OCXM_INVALID 0x04 |
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/* 'Valid', i.e. high before any inversion. */ |
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#define CHCTLR_OCXM_VALID 0x05 |
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#define CHCTLR_OCXM_PWM_MODE1 0x06 |
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/* Start bit offset for OC{1,3}M */ |
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#define CHCTLR_OCXM_ODD_SHIFT 4 |
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/* Start bit offset for OC{2,4}M */ |
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#define CHCTLR_OCXM_EVEN_SHIFT 12 |
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/* Each of the 4 channels uses 1 nibble of CCER */ |
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#define CCER_MASK (TIM_CC1P | TIM_CC1E) |
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struct pwm_wch_gptm_config { |
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TIM_TypeDef *regs; |
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const struct device *clock_dev; |
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uint8_t clock_id; |
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uint16_t prescaler; |
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const struct pinctrl_dev_config *pin_cfg; |
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}; |
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static int pwm_wch_gptm_set_cycles(const struct device *dev, uint32_t channel, |
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uint32_t period_cycles, uint32_t pulse_cycles, pwm_flags_t flags) |
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{ |
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const struct pwm_wch_gptm_config *config = dev->config; |
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TIM_TypeDef *regs = config->regs; |
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uint16_t ocxm; |
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if (period_cycles > UINT16_MAX) { |
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return -EINVAL; |
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} |
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if (period_cycles == 0) { |
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ocxm = CHCTLR_OCXM_INVALID; |
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} else if (pulse_cycles >= period_cycles) { |
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/*
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* If pulse_cycles == period_cycles then there is a one cycle glitch in the output. |
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* Mitigate by setting the output to 'always on'. |
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*/ |
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ocxm = CHCTLR_OCXM_VALID; |
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} else { |
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ocxm = CHCTLR_OCXM_PWM_MODE1; |
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} |
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switch (channel) { |
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case 0: |
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regs->CH1CVR = pulse_cycles; |
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regs->CHCTLR1 = (regs->CHCTLR1 & ~TIM_OC1M) | (ocxm << CHCTLR_OCXM_ODD_SHIFT); |
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break; |
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case 1: |
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regs->CH2CVR = pulse_cycles; |
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regs->CHCTLR1 = (regs->CHCTLR1 & ~TIM_OC2M) | (ocxm << CHCTLR_OCXM_EVEN_SHIFT); |
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break; |
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case 2: |
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regs->CH3CVR = pulse_cycles; |
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regs->CHCTLR2 = (regs->CHCTLR2 & ~TIM_OC3M) | (ocxm << CHCTLR_OCXM_ODD_SHIFT); |
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break; |
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case 3: |
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regs->CH4CVR = pulse_cycles; |
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regs->CHCTLR2 = (regs->CHCTLR2 & ~TIM_OC4M) | (ocxm << CHCTLR_OCXM_EVEN_SHIFT); |
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break; |
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default: |
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return -EINVAL; |
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} |
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if (period_cycles != 0) { |
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regs->ATRLR = period_cycles; |
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} |
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/* Set the polarity and enable */ |
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uint16_t shift = 4 * channel; |
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if ((flags & PWM_POLARITY_INVERTED) != 0) { |
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regs->CCER = |
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(regs->CCER & ~(CCER_MASK << shift)) | ((TIM_CC1P | TIM_CC1E) << shift); |
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} else { |
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regs->CCER = (regs->CCER & ~(CCER_MASK << shift)) | (TIM_CC1E << shift); |
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} |
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return 0; |
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} |
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static int pwm_wch_gptm_get_cycles_per_sec(const struct device *dev, uint32_t channel, |
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uint64_t *cycles) |
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{ |
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const struct pwm_wch_gptm_config *config = dev->config; |
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clock_control_subsys_t clock_sys = (clock_control_subsys_t *)(uintptr_t)config->clock_id; |
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uint32_t clock_rate; |
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int err; |
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err = clock_control_get_rate(config->clock_dev, clock_sys, &clock_rate); |
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if (err != 0) { |
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return err; |
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} |
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*cycles = clock_rate / (config->prescaler + 1); |
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return 0; |
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} |
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static const struct pwm_driver_api pwm_wch_gptm_driver_api = { |
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.set_cycles = pwm_wch_gptm_set_cycles, |
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.get_cycles_per_sec = pwm_wch_gptm_get_cycles_per_sec, |
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}; |
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static int pwm_wch_gptm_init(const struct device *dev) |
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{ |
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const struct pwm_wch_gptm_config *config = dev->config; |
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TIM_TypeDef *regs = config->regs; |
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int err; |
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clock_control_on(config->clock_dev, (clock_control_subsys_t *)(uintptr_t)config->clock_id); |
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err = pinctrl_apply_state(config->pin_cfg, PINCTRL_STATE_DEFAULT); |
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if (err != 0) { |
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return err; |
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} |
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/* Disable and configure the counter */ |
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regs->CTLR1 = TIM_ARPE; |
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regs->PSC = config->prescaler; |
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regs->CTLR1 |= TIM_CEN; |
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return 0; |
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} |
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#define PWM_WCH_GPTM_INIT(idx) \ |
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PINCTRL_DT_INST_DEFINE(idx); \ |
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\ |
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static const struct pwm_wch_gptm_config pwm_wch_gptm_##idx##_config = { \ |
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.regs = (TIM_TypeDef *)DT_REG_ADDR(DT_INST_PARENT(idx)), \ |
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.prescaler = DT_PROP(DT_INST_PARENT(idx), prescaler), \ |
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.clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_INST_PARENT(idx))), \ |
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.clock_id = DT_CLOCKS_CELL(DT_INST_PARENT(idx), id), \ |
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.pin_cfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx), \ |
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}; \ |
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\ |
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DEVICE_DT_INST_DEFINE(idx, &pwm_wch_gptm_init, NULL, NULL, &pwm_wch_gptm_##idx##_config, \ |
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POST_KERNEL, CONFIG_PWM_INIT_PRIORITY, &pwm_wch_gptm_driver_api); |
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DT_INST_FOREACH_STATUS_OKAY(PWM_WCH_GPTM_INIT) |
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# Copyright (c) 2025 Michael Hope <michaelh@juju.nz> |
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# SPDX-License-Identifier: Apache-2.0 |
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description: WCH General-purpose Timer (GPTM) for PWM |
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compatible: "wch,gptm" |
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include: [base.yaml] |
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properties: |
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reg: |
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required: true |
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clocks: |
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required: true |
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channels: |
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type: int |
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required: true |
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description: Number of timer channels. |
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prescaler: |
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type: int |
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default: 0 |
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description: | |
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Counter prescaler from 0 to 65535. The clock frequency to the counter |
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is the input frequency divided by (prescaler + 1). For example, if the |
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input clock is 48 MHz and the desired counter clock is 1 MHz, set this |
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property to 47. |
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# Copyright (c) 2025 Michael Hope <michaelh@juju.nz> |
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# SPDX-License-Identifier: Apache-2.0 |
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description: WCH General-purpose Timer (GPTM) for PWM |
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compatible: "wch,gptm-pwm" |
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include: [base.yaml, pwm-controller.yaml, pinctrl-device.yaml] |
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properties: |
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"#pwm-cells": |
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const: 3 |
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pwm-cells: |
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- channel |
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- period |
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- flags |
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