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dts: arm: nxp: add support pwm emios for nxp s32z SoC 

This adds support PWM EMIOS for NXP S32Z SoC, both PWM pulse
generate and pulse capture are supported

Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
pull/84185/head
Dat Nguyen Duy 10 months ago committed by Benjamin Cabé
parent
e72af321d5
commit
5014a204cf
3 changed files with 177 additions and 1 deletions
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  1. 4
      drivers/pwm/pwm_nxp_s32_emios.c
  2. 172
      dts/arm/nxp/nxp_s32z27x_r52.dtsi
  3. 2
      west.yml

4
drivers/pwm/pwm_nxp_s32_emios.c
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@ -23,6 +23,10 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME, CONFIG_PWM_LOG_LEVEL); @@ -23,6 +23,10 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME, CONFIG_PWM_LOG_LEVEL);
#define DT_DRV_COMPAT nxp_s32_emios_pwm
#if !defined(EMIOS_PWM_IP_NUM_OF_CHANNELS_USED)
#define EMIOS_PWM_IP_NUM_OF_CHANNELS_USED EMIOS_PWM_IP_NUM_OF_CHANNELS_USED_U8
#endif
/*
* Need to fill to this array at runtime, cannot do at build time like
* the HAL over configuration tool due to limitation of the integration

172
dts/arm/nxp/nxp_s32z27x_r52.dtsi
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@ -1259,5 +1259,177 @@ @@ -1259,5 +1259,177 @@
status = "disabled";
};
emios0: emios@420b0000 {
compatible = "nxp,s32-emios";
reg = <0x420b0000 0x4000>;
clocks = <&clock NXP_S32_P4_REG_INTF_CLK>;
internal-cnt = <0xFFFFFFFF>;
interrupts = <GIC_SPI 284 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 285 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 286 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 287 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 288 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 289 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 290 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 291 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 292 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 293 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 294 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 295 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 296 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 297 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 298 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 299 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 300 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 301 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 302 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 303 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 304 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 305 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 306 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 307 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 308 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 309 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 310 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 311 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 312 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
interrupt-names = "0_CH0", "0_CH1", "0_CH2", "0_CH3", "0_CH4",
"0_CH5", "0_CH6", "0_CH7", "0_CH8", "0_CH9",
"0_CH10", "0_CH12", "0_CH14", "0_CH16",
"0_CH17", "0_CH18", "0_CH19", "0_CH20",
"0_CH21", "0_CH22", "0_CH23", "0_CH24",
"0_CH25", "0_CH26", "0_CH27", "0_CH28",
"0_CH29", "0_CH30", "0_CH31";
status = "disabled";
master_bus {
emios0_bus_a: emios0_bus_a {
channel = <23>;
bus-type = "BUS_A";
channel-mask = <0xFF7FFFFF>;
status = "disabled";
};
emios0_bus_b: emios0_bus_b {
channel = <0>;
bus-type = "BUS_B";
channel-mask = <0x000000FE>;
status = "disabled";
};
emios0_bus_c: emios0_bus_c {
channel = <8>;
bus-type = "BUS_C";
channel-mask = <0x0000FE00>;
status = "disabled";
};
emios0_bus_d: emios0_bus_d {
channel = <16>;
bus-type = "BUS_D";
channel-mask = <0x00FE0000>;
status = "disabled";
};
emios0_bus_e: emios0_bus_e {
channel = <24>;
bus-type = "BUS_E";
channel-mask = <0xFE000000>;
status = "disabled";
};
};
pwm {
compatible = "nxp,s32-emios-pwm";
#pwm-cells = <3>;
status = "disabled";
};
};
emios1: emios@400b0000 {
compatible = "nxp,s32-emios";
reg = <0x400b0000 0x4000>;
clocks = <&clock NXP_S32_P0_REG_INTF_CLK>;
internal-cnt = <0xFFFFFFFF>;
interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 315 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 316 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 317 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 318 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 319 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 320 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 321 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 322 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 323 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 324 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 325 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 326 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 327 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 328 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 329 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 330 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 331 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 332 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 333 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 334 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 335 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 336 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 337 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 338 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 339 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 340 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 341 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
interrupt-names = "1_CH0", "1_CH1", "1_CH2", "1_CH3", "1_CH4",
"1_CH5", "1_CH6", "1_CH7", "1_CH8", "1_CH10",
"1_CH12", "1_CH14", "1_CH16", "1_CH17",
"1_CH18", "1_CH19", "1_CH20", "1_CH21",
"1_CH22", "1_CH23", "1_CH24", "1_CH25",
"1_CH26", "1_CH27", "1_CH28", "1_CH29",
"1_CH30", "1_CH31";
status = "disabled";
master_bus {
emios1_bus_a: emios1_bus_a {
channel = <23>;
bus-type = "BUS_A";
channel-mask = <0xFF7FFFFF>;
status = "disabled";
};
emios1_bus_b: emios1_bus_b {
channel = <0>;
bus-type = "BUS_B";
channel-mask = <0x000000FE>;
status = "disabled";
};
emios1_bus_c: emios1_bus_c {
channel = <8>;
bus-type = "BUS_C";
channel-mask = <0x0000FE00>;
status = "disabled";
};
emios1_bus_d: emios1_bus_d {
channel = <16>;
bus-type = "BUS_D";
channel-mask = <0x00FE0000>;
status = "disabled";
};
emios1_bus_e: emios1_bus_e {
channel = <24>;
channel-mask = <0xFE000000>;
bus-type = "BUS_E";
status = "disabled";
};
};
pwm {
compatible = "nxp,s32-emios-pwm";
#pwm-cells = <3>;
status = "disabled";
};
};
};
};

2
west.yml
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@ -203,7 +203,7 @@ manifest: @@ -203,7 +203,7 @@ manifest:
groups:
- hal
- name: hal_nxp
revision: c15dd51d7af27593e38b65b1443a350e9d2de64f
revision: dad9b28b80c68c4e124dd3a61eb3821df387bf0e
path: modules/hal/nxp
groups:
- hal

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