drivers: gicv3: clang-format

Formatting files for compliance

Signed-off-by: Adam Openshaw <quic_adamo@quicinc.com>

drivers/interrupt_controller/intc_gic_common_priv.h

@@ -41,8 +41,7 @@
 #if CONFIG_GIC_VER <= 2
 #define GET_DIST_BASE(intid) GIC_DIST_BASE
 #else
-#define GET_DIST_BASE(intid)	((intid < GIC_SPI_INT_BASE) ? \
-				(gic_get_rdist() + GICR_SGI_BASE_OFF) \
-				: GIC_DIST_BASE)
+#define GET_DIST_BASE(intid)                                                                       \
+	((intid < GIC_SPI_INT_BASE) ? (gic_get_rdist() + GICR_SGI_BASE_OFF) : GIC_DIST_BASE)
 #endif
 #endif /* ZEPHYR_INCLUDE_DRIVERS_INTC_GIC_COMMON_PRIV_H */

drivers/interrupt_controller/intc_gicv3.c

@@ -44,9 +44,7 @@ struct gic_reg_region {
  * GIC register regions info table
  */
 static struct gic_reg_region gic_reg_regions[] = {
-	LISTIFY(DT_NUM_REGS(GIC_V3_NODE), GIC_REG_REGION, (,), GIC_V3_NODE)
-};
-
+	LISTIFY(DT_NUM_REGS(GIC_V3_NODE), GIC_REG_REGION, (,), GIC_V3_NODE) };
 
 /* Redistributor base addresses for each core */
 mem_addr_t gic_rdists[CONFIG_MP_MAX_NUM_CPUS];
@@ -152,8 +150,7 @@ static inline void arm_gic_write_irouter(uint64_t val, unsigned int intid)
 }
 #endif
 
-void arm_gic_irq_set_priority(unsigned int intid,
-			      unsigned int prio, uint32_t flags)
+void arm_gic_irq_set_priority(unsigned int intid, unsigned int prio, uint32_t flags)
 {
 #ifdef CONFIG_GIC_V3_ITS
 	if (intid >= 8192) {
@@ -301,8 +298,7 @@ void arm_gic_eoi(unsigned int intid)
 	write_sysreg(intid, ICC_EOIR1_EL1);
 }
 
-void gic_raise_sgi(unsigned int sgi_id, uint64_t target_aff,
-		   uint16_t target_list)
+void gic_raise_sgi(unsigned int sgi_id, uint64_t target_aff, uint16_t target_list)
 {
 	uint32_t aff3, aff2, aff1;
 	uint64_t sgi_val;
@@ -318,8 +314,7 @@ void gic_raise_sgi(unsigned int sgi_id, uint64_t target_aff,
 #else
 	aff3 = MPIDR_AFFLVL(target_aff, 3);
 #endif
-	sgi_val = GICV3_SGIR_VALUE(aff3, aff2, aff1, sgi_id,
-				   SGIR_IRM_TO_AFF, target_list);
+	sgi_val = GICV3_SGIR_VALUE(aff3, aff2, aff1, sgi_id, SGIR_IRM_TO_AFF, target_list);
 
 	barrier_dsync_fence_full();
 	write_sysreg(sgi_val, ICC_SGI1R);
@@ -361,8 +356,8 @@ static void gicv3_rdist_enable(mem_addr_t rdist)
  */
 static void gicv3_rdist_setup_lpis(mem_addr_t rdist)
 {
-	unsigned int lpi_id_bits = MIN(GICD_TYPER_IDBITS(sys_read32(GICD_TYPER)),
-				       ITS_MAX_LPI_NRBITS);
+	unsigned int lpi_id_bits =
+		MIN(GICD_TYPER_IDBITS(sys_read32(GICD_TYPER)), ITS_MAX_LPI_NRBITS);
 	uintptr_t lpi_pend_table;
 	uint64_t reg;
 	uint32_t ctlr;
@@ -393,8 +388,7 @@ static void gicv3_rdist_setup_lpis(mem_addr_t rdist)
 	reg = (GIC_BASER_SHARE_INNER << GITR_PENDBASER_SHAREABILITY_SHIFT) |
 	      (GIC_BASER_CACHE_RAWAWB << GITR_PENDBASER_INNER_CACHE_SHIFT) |
 	      (lpi_pend_table & (GITR_PENDBASER_ADDR_MASK << GITR_PENDBASER_ADDR_SHIFT)) |
-	      (GIC_BASER_CACHE_INNERLIKE << GITR_PENDBASER_OUTER_CACHE_SHIFT) |
-	      GITR_PENDBASER_PTZ;
+	      (GIC_BASER_CACHE_INNERLIKE << GITR_PENDBASER_OUTER_CACHE_SHIFT) | GITR_PENDBASER_PTZ;
 	sys_write64(reg, rdist + GICR_PENDBASER);
 	/* TOFIX: check SHAREABILITY validity */
 
@@ -434,8 +428,7 @@ static void gicv3_cpuif_init(void)
 	/*
 	 * Configure default priorities for SGI 0:15 and PPI 0:15.
 	 */
-	for (intid = 0; intid < GIC_SPI_INT_BASE;
-	     intid += GIC_NUM_PRI_PER_REG) {
+	for (intid = 0; intid < GIC_SPI_INT_BASE; intid += GIC_NUM_PRI_PER_REG) {
 		sys_write32(GIC_INT_DEF_PRI_X4, IPRIORITYR(base, intid));
 	}
 
@@ -451,8 +444,8 @@ static void gicv3_cpuif_init(void)
 	icc_sre = read_sysreg(ICC_SRE_EL1);
 
 	if (!(icc_sre & ICC_SRE_ELx_SRE_BIT)) {
-		icc_sre = (icc_sre | ICC_SRE_ELx_SRE_BIT |
-			   ICC_SRE_ELx_DIB_BIT | ICC_SRE_ELx_DFB_BIT);
+		icc_sre =
+			(icc_sre | ICC_SRE_ELx_SRE_BIT | ICC_SRE_ELx_DIB_BIT | ICC_SRE_ELx_DFB_BIT);
 		write_sysreg(icc_sre, ICC_SRE_EL1);
 		icc_sre = read_sysreg(ICC_SRE_EL1);
 
@@ -507,40 +500,32 @@ static void gicv3_dist_init(void)
 	/*
 	 * Default configuration of all SPIs
 	 */
-	for (intid = GIC_SPI_INT_BASE; intid < num_ints;
-	     intid += GIC_NUM_INTR_PER_REG) {
+	for (intid = GIC_SPI_INT_BASE; intid < num_ints; intid += GIC_NUM_INTR_PER_REG) {
 		idx = intid / GIC_NUM_INTR_PER_REG;
 		/* Disable interrupt */
-		sys_write32(BIT64_MASK(GIC_NUM_INTR_PER_REG),
-			    ICENABLER(base, idx));
+		sys_write32(BIT64_MASK(GIC_NUM_INTR_PER_REG), ICENABLER(base, idx));
 		/* Clear pending */
-		sys_write32(BIT64_MASK(GIC_NUM_INTR_PER_REG),
-			    ICPENDR(base, idx));
+		sys_write32(BIT64_MASK(GIC_NUM_INTR_PER_REG), ICPENDR(base, idx));
 		sys_write32(IGROUPR_VAL, IGROUPR(base, idx));
-		sys_write32(BIT64_MASK(GIC_NUM_INTR_PER_REG),
-			    IGROUPMODR(base, idx));
-
+		sys_write32(BIT64_MASK(GIC_NUM_INTR_PER_REG), IGROUPMODR(base, idx));
 	}
 	/* wait for rwp on GICD */
 	gic_wait_rwp(GIC_SPI_INT_BASE);
 
 	/* Configure default priorities for all SPIs. */
-	for (intid = GIC_SPI_INT_BASE; intid < num_ints;
-	     intid += GIC_NUM_PRI_PER_REG) {
+	for (intid = GIC_SPI_INT_BASE; intid < num_ints; intid += GIC_NUM_PRI_PER_REG) {
 		sys_write32(GIC_INT_DEF_PRI_X4, IPRIORITYR(base, intid));
 	}
 
 	/* Configure all SPIs as active low, level triggered by default */
-	for (intid = GIC_SPI_INT_BASE; intid < num_ints;
-	     intid += GIC_NUM_CFG_PER_REG) {
+	for (intid = GIC_SPI_INT_BASE; intid < num_ints; intid += GIC_NUM_CFG_PER_REG) {
 		idx = intid / GIC_NUM_CFG_PER_REG;
 		sys_write32(0, ICFGR(base, idx));
 	}
 
 #ifdef CONFIG_ARMV8_A_NS
 	/* Enable distributor with ARE */
-	sys_write32(BIT(GICD_CTRL_ARE_NS) | BIT(GICD_CTLR_ENABLE_G1NS),
-		    GICD_CTLR);
+	sys_write32(BIT(GICD_CTRL_ARE_NS) | BIT(GICD_CTLR_ENABLE_G1NS), GICD_CTLR);
 #elif defined(CONFIG_GIC_SINGLE_SECURITY_STATE)
 	/*
 	 * For GIC single security state, the config GIC_SINGLE_SECURITY_STATE
@@ -552,8 +537,7 @@ static void gicv3_dist_init(void)
 	 * similarly the GICD_CTLR_ENABLE_G1 and GICD_CTLR_ENABLE_G1NS share
 	 * BIT(1), we can reuse them.
 	 */
-	sys_write32(BIT(GICD_CTRL_ARE_S) | BIT(GICD_CTLR_ENABLE_G1NS),
-		    GICD_CTLR);
+	sys_write32(BIT(GICD_CTRL_ARE_S) | BIT(GICD_CTLR_ENABLE_G1NS), GICD_CTLR);
 #else
 	/* enable Group 1 secure interrupts */
 	sys_set_bit(GICD_CTLR, GICD_CTLR_ENABLE_G1S);
@@ -668,8 +652,8 @@ int arm_gic_init(const struct device *dev)
 
 	return 0;
 }
-DEVICE_DT_INST_DEFINE(0, arm_gic_init, NULL, NULL, NULL,
-		      PRE_KERNEL_1, CONFIG_INTC_INIT_PRIORITY, NULL);
+DEVICE_DT_INST_DEFINE(0, arm_gic_init, NULL, NULL, NULL, PRE_KERNEL_1, CONFIG_INTC_INIT_PRIORITY,
+		      NULL);
 
 #ifdef CONFIG_SMP
 void arm_gic_secondary_init(void)

include/zephyr/drivers/interrupt_controller/gic.h

@@ -167,7 +167,6 @@
  */
 #define GICC_EOIR (GIC_CPU_BASE + 0x10)
 
-
 /*
  * Helper Constants
  */
@@ -185,9 +184,8 @@
 #define GICC_CTLR_FIQBYPDISGRP1 BIT(7)
 #define GICC_CTLR_IRQBYPDISGRP1 BIT(8)
 
-#define GICC_CTLR_BYPASS_MASK	(GICC_CTLR_FIQBYPDISGRP0 | \
-				 GICC_CTLR_IRQBYPDISGRP1 | \
-				 GICC_CTLR_FIQBYPDISGRP1 | \
+#define GICC_CTLR_BYPASS_MASK                                                                      \
+	(GICC_CTLR_FIQBYPDISGRP0 | GICC_CTLR_IRQBYPDISGRP1 | GICC_CTLR_FIQBYPDISGRP1 |             \
 	 GICC_CTLR_IRQBYPDISGRP1)
 
 #endif /* CONFIG_GIC_V2 */
@@ -208,7 +206,6 @@
 
 #endif /* CONFIG_GIC_VER <= 2 */
 
-
 /* GICD_ICFGR */
 #define GICD_ICFGR_MASK BIT_MASK(2)
 #define GICD_ICFGR_TYPE BIT(1)
@@ -225,16 +222,13 @@
 #define GIC_SGI_INT_BASE 0
 #define GIC_PPI_INT_BASE 16
 
-#define GIC_IS_SGI(intid)		(((intid) >= GIC_SGI_INT_BASE) && \
-					 ((intid) < GIC_PPI_INT_BASE))
-
+#define GIC_IS_SGI(intid) (((intid) >= GIC_SGI_INT_BASE) && ((intid) < GIC_PPI_INT_BASE))
 
 #define GIC_SPI_INT_BASE 32
 
 #define GIC_SPI_MAX_INTID 1019
 
-#define GIC_IS_SPI(intid)		(((intid) >= GIC_SPI_INT_BASE) && \
-					((intid) <= GIC_SPI_MAX_INTID))
+#define GIC_IS_SPI(intid) (((intid) >= GIC_SPI_INT_BASE) && ((intid) <= GIC_SPI_MAX_INTID))
 
 #define GIC_NUM_INTR_PER_REG 32
 
@@ -323,8 +317,7 @@ void arm_gic_irq_clear_pending(unsigned int irq);
  * @param prio interrupt priority
  * @param flags interrupt flags
  */
-void arm_gic_irq_set_priority(
-	unsigned int irq, unsigned int prio, unsigned int flags);
+void arm_gic_irq_set_priority(unsigned int irq, unsigned int prio, unsigned int flags);
 
 /**
  * @brief Get active interrupt ID
@@ -355,8 +348,7 @@ void arm_gic_secondary_init(void);
  *                    Aff level 1 2 3 will be extracted by api.
  * @param target_list bitmask of target cores
  */
-void gic_raise_sgi(unsigned int sgi_id, uint64_t target_aff,
-		   uint16_t target_list);
+void gic_raise_sgi(unsigned int sgi_id, uint64_t target_aff, uint16_t target_list);
 
 #endif /* !_ASMLANGUAGE */