diff --git a/drivers/interrupt_controller/intc_gic_common_priv.h b/drivers/interrupt_controller/intc_gic_common_priv.h index f07d66a7cf5..0dc38e03939 100644 --- a/drivers/interrupt_controller/intc_gic_common_priv.h +++ b/drivers/interrupt_controller/intc_gic_common_priv.h @@ -8,29 +8,29 @@ #define ZEPHYR_INCLUDE_DRIVERS_INTC_GIC_COMMON_PRIV_H_ /* Offsets from GICD base or GICR(n) SGI_base */ -#define GIC_DIST_IGROUPR 0x0080 -#define GIC_DIST_ISENABLER 0x0100 -#define GIC_DIST_ICENABLER 0x0180 -#define GIC_DIST_ISPENDR 0x0200 -#define GIC_DIST_ICPENDR 0x0280 -#define GIC_DIST_ISACTIVER 0x0300 -#define GIC_DIST_ICACTIVER 0x0380 -#define GIC_DIST_IPRIORITYR 0x0400 -#define GIC_DIST_ITARGETSR 0x0800 -#define GIC_DIST_ICFGR 0x0c00 -#define GIC_DIST_IGROUPMODR 0x0d00 -#define GIC_DIST_SGIR 0x0f00 +#define GIC_DIST_IGROUPR 0x0080 +#define GIC_DIST_ISENABLER 0x0100 +#define GIC_DIST_ICENABLER 0x0180 +#define GIC_DIST_ISPENDR 0x0200 +#define GIC_DIST_ICPENDR 0x0280 +#define GIC_DIST_ISACTIVER 0x0300 +#define GIC_DIST_ICACTIVER 0x0380 +#define GIC_DIST_IPRIORITYR 0x0400 +#define GIC_DIST_ITARGETSR 0x0800 +#define GIC_DIST_ICFGR 0x0c00 +#define GIC_DIST_IGROUPMODR 0x0d00 +#define GIC_DIST_SGIR 0x0f00 /* GICD GICR common access macros */ -#define IGROUPR(base, n) (base + GIC_DIST_IGROUPR + (n) * 4) -#define ISENABLER(base, n) (base + GIC_DIST_ISENABLER + (n) * 4) -#define ICENABLER(base, n) (base + GIC_DIST_ICENABLER + (n) * 4) -#define ISPENDR(base, n) (base + GIC_DIST_ISPENDR + (n) * 4) -#define ICPENDR(base, n) (base + GIC_DIST_ICPENDR + (n) * 4) -#define IPRIORITYR(base, n) (base + GIC_DIST_IPRIORITYR + n) -#define ITARGETSR(base, n) (base + GIC_DIST_ITARGETSR + (n) * 4) -#define ICFGR(base, n) (base + GIC_DIST_ICFGR + (n) * 4) -#define IGROUPMODR(base, n) (base + GIC_DIST_IGROUPMODR + (n) * 4) +#define IGROUPR(base, n) (base + GIC_DIST_IGROUPR + (n) * 4) +#define ISENABLER(base, n) (base + GIC_DIST_ISENABLER + (n) * 4) +#define ICENABLER(base, n) (base + GIC_DIST_ICENABLER + (n) * 4) +#define ISPENDR(base, n) (base + GIC_DIST_ISPENDR + (n) * 4) +#define ICPENDR(base, n) (base + GIC_DIST_ICPENDR + (n) * 4) +#define IPRIORITYR(base, n) (base + GIC_DIST_IPRIORITYR + n) +#define ITARGETSR(base, n) (base + GIC_DIST_ITARGETSR + (n) * 4) +#define ICFGR(base, n) (base + GIC_DIST_ICFGR + (n) * 4) +#define IGROUPMODR(base, n) (base + GIC_DIST_IGROUPMODR + (n) * 4) /* * selects redistributor SGI_base for current core for PPI and SGI @@ -39,10 +39,9 @@ */ #if CONFIG_GIC_VER <= 2 -#define GET_DIST_BASE(intid) GIC_DIST_BASE +#define GET_DIST_BASE(intid) GIC_DIST_BASE #else -#define GET_DIST_BASE(intid) ((intid < GIC_SPI_INT_BASE) ? \ - (gic_get_rdist() + GICR_SGI_BASE_OFF) \ - : GIC_DIST_BASE) +#define GET_DIST_BASE(intid) \ + ((intid < GIC_SPI_INT_BASE) ? (gic_get_rdist() + GICR_SGI_BASE_OFF) : GIC_DIST_BASE) #endif #endif /* ZEPHYR_INCLUDE_DRIVERS_INTC_GIC_COMMON_PRIV_H */ diff --git a/drivers/interrupt_controller/intc_gicv3.c b/drivers/interrupt_controller/intc_gicv3.c index 50e36f1e87a..a8a6f70e805 100644 --- a/drivers/interrupt_controller/intc_gicv3.c +++ b/drivers/interrupt_controller/intc_gicv3.c @@ -21,15 +21,15 @@ #define DT_DRV_COMPAT arm_gic_v3 -#define GIC_V3_NODE DT_COMPAT_GET_ANY_STATUS_OKAY(DT_DRV_COMPAT) +#define GIC_V3_NODE DT_COMPAT_GET_ANY_STATUS_OKAY(DT_DRV_COMPAT) -#define GIC_REDISTRIBUTOR_STRIDE DT_PROP_OR(GIC_V3_NODE, redistributor_stride, 0) -#define GIC_NUM_REDISTRIBUTOR_REGIONS DT_PROP_OR(GIC_V3_NODE, redistributor_regions, 1) +#define GIC_REDISTRIBUTOR_STRIDE DT_PROP_OR(GIC_V3_NODE, redistributor_stride, 0) +#define GIC_NUM_REDISTRIBUTOR_REGIONS DT_PROP_OR(GIC_V3_NODE, redistributor_regions, 1) -#define GIC_REG_REGION(idx, node_id) \ - { \ - .base = DT_REG_ADDR_BY_IDX(node_id, idx), \ - .size = DT_REG_SIZE_BY_IDX(node_id, idx), \ +#define GIC_REG_REGION(idx, node_id) \ + { \ + .base = DT_REG_ADDR_BY_IDX(node_id, idx), \ + .size = DT_REG_SIZE_BY_IDX(node_id, idx), \ } /* @@ -44,17 +44,15 @@ struct gic_reg_region { * GIC register regions info table */ static struct gic_reg_region gic_reg_regions[] = { - LISTIFY(DT_NUM_REGS(GIC_V3_NODE), GIC_REG_REGION, (,), GIC_V3_NODE) -}; - + LISTIFY(DT_NUM_REGS(GIC_V3_NODE), GIC_REG_REGION, (,), GIC_V3_NODE) }; /* Redistributor base addresses for each core */ mem_addr_t gic_rdists[CONFIG_MP_MAX_NUM_CPUS]; #if defined(CONFIG_ARMV8_A_NS) || defined(CONFIG_GIC_SINGLE_SECURITY_STATE) -#define IGROUPR_VAL 0xFFFFFFFFU +#define IGROUPR_VAL 0xFFFFFFFFU #else -#define IGROUPR_VAL 0x0U +#define IGROUPR_VAL 0x0U #endif /* @@ -62,10 +60,10 @@ mem_addr_t gic_rdists[CONFIG_MP_MAX_NUM_CPUS]; * deal with (one configuration byte per interrupt). PENDBASE has to * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI). */ -#define ITS_MAX_LPI_NRBITS 16 /* 64K LPIs */ +#define ITS_MAX_LPI_NRBITS 16 /* 64K LPIs */ -#define LPI_PROPBASE_SZ(nrbits) ROUND_UP(BIT(nrbits), KB(64)) -#define LPI_PENDBASE_SZ(nrbits) ROUND_UP(BIT(nrbits) / 8, KB(64)) +#define LPI_PROPBASE_SZ(nrbits) ROUND_UP(BIT(nrbits), KB(64)) +#define LPI_PENDBASE_SZ(nrbits) ROUND_UP(BIT(nrbits) / 8, KB(64)) #ifdef CONFIG_GIC_V3_ITS static uintptr_t lpi_prop_table; @@ -152,8 +150,7 @@ static inline void arm_gic_write_irouter(uint64_t val, unsigned int intid) } #endif -void arm_gic_irq_set_priority(unsigned int intid, - unsigned int prio, uint32_t flags) +void arm_gic_irq_set_priority(unsigned int intid, unsigned int prio, uint32_t flags) { #ifdef CONFIG_GIC_V3_ITS if (intid >= 8192) { @@ -301,8 +298,7 @@ void arm_gic_eoi(unsigned int intid) write_sysreg(intid, ICC_EOIR1_EL1); } -void gic_raise_sgi(unsigned int sgi_id, uint64_t target_aff, - uint16_t target_list) +void gic_raise_sgi(unsigned int sgi_id, uint64_t target_aff, uint16_t target_list) { uint32_t aff3, aff2, aff1; uint64_t sgi_val; @@ -318,8 +314,7 @@ void gic_raise_sgi(unsigned int sgi_id, uint64_t target_aff, #else aff3 = MPIDR_AFFLVL(target_aff, 3); #endif - sgi_val = GICV3_SGIR_VALUE(aff3, aff2, aff1, sgi_id, - SGIR_IRM_TO_AFF, target_list); + sgi_val = GICV3_SGIR_VALUE(aff3, aff2, aff1, sgi_id, SGIR_IRM_TO_AFF, target_list); barrier_dsync_fence_full(); write_sysreg(sgi_val, ICC_SGI1R); @@ -361,8 +356,8 @@ static void gicv3_rdist_enable(mem_addr_t rdist) */ static void gicv3_rdist_setup_lpis(mem_addr_t rdist) { - unsigned int lpi_id_bits = MIN(GICD_TYPER_IDBITS(sys_read32(GICD_TYPER)), - ITS_MAX_LPI_NRBITS); + unsigned int lpi_id_bits = + MIN(GICD_TYPER_IDBITS(sys_read32(GICD_TYPER)), ITS_MAX_LPI_NRBITS); uintptr_t lpi_pend_table; uint64_t reg; uint32_t ctlr; @@ -393,8 +388,7 @@ static void gicv3_rdist_setup_lpis(mem_addr_t rdist) reg = (GIC_BASER_SHARE_INNER << GITR_PENDBASER_SHAREABILITY_SHIFT) | (GIC_BASER_CACHE_RAWAWB << GITR_PENDBASER_INNER_CACHE_SHIFT) | (lpi_pend_table & (GITR_PENDBASER_ADDR_MASK << GITR_PENDBASER_ADDR_SHIFT)) | - (GIC_BASER_CACHE_INNERLIKE << GITR_PENDBASER_OUTER_CACHE_SHIFT) | - GITR_PENDBASER_PTZ; + (GIC_BASER_CACHE_INNERLIKE << GITR_PENDBASER_OUTER_CACHE_SHIFT) | GITR_PENDBASER_PTZ; sys_write64(reg, rdist + GICR_PENDBASER); /* TOFIX: check SHAREABILITY validity */ @@ -434,8 +428,7 @@ static void gicv3_cpuif_init(void) /* * Configure default priorities for SGI 0:15 and PPI 0:15. */ - for (intid = 0; intid < GIC_SPI_INT_BASE; - intid += GIC_NUM_PRI_PER_REG) { + for (intid = 0; intid < GIC_SPI_INT_BASE; intid += GIC_NUM_PRI_PER_REG) { sys_write32(GIC_INT_DEF_PRI_X4, IPRIORITYR(base, intid)); } @@ -451,8 +444,8 @@ static void gicv3_cpuif_init(void) icc_sre = read_sysreg(ICC_SRE_EL1); if (!(icc_sre & ICC_SRE_ELx_SRE_BIT)) { - icc_sre = (icc_sre | ICC_SRE_ELx_SRE_BIT | - ICC_SRE_ELx_DIB_BIT | ICC_SRE_ELx_DFB_BIT); + icc_sre = + (icc_sre | ICC_SRE_ELx_SRE_BIT | ICC_SRE_ELx_DIB_BIT | ICC_SRE_ELx_DFB_BIT); write_sysreg(icc_sre, ICC_SRE_EL1); icc_sre = read_sysreg(ICC_SRE_EL1); @@ -501,46 +494,38 @@ static void gicv3_dist_init(void) */ sys_set_bit(GICD_CTLR, GICD_CTRL_NS); __ASSERT(sys_test_bit(GICD_CTLR, GICD_CTRL_NS), - "Current GIC does not support single security state"); + "Current GIC does not support single security state"); #endif /* * Default configuration of all SPIs */ - for (intid = GIC_SPI_INT_BASE; intid < num_ints; - intid += GIC_NUM_INTR_PER_REG) { + for (intid = GIC_SPI_INT_BASE; intid < num_ints; intid += GIC_NUM_INTR_PER_REG) { idx = intid / GIC_NUM_INTR_PER_REG; /* Disable interrupt */ - sys_write32(BIT64_MASK(GIC_NUM_INTR_PER_REG), - ICENABLER(base, idx)); + sys_write32(BIT64_MASK(GIC_NUM_INTR_PER_REG), ICENABLER(base, idx)); /* Clear pending */ - sys_write32(BIT64_MASK(GIC_NUM_INTR_PER_REG), - ICPENDR(base, idx)); + sys_write32(BIT64_MASK(GIC_NUM_INTR_PER_REG), ICPENDR(base, idx)); sys_write32(IGROUPR_VAL, IGROUPR(base, idx)); - sys_write32(BIT64_MASK(GIC_NUM_INTR_PER_REG), - IGROUPMODR(base, idx)); - + sys_write32(BIT64_MASK(GIC_NUM_INTR_PER_REG), IGROUPMODR(base, idx)); } /* wait for rwp on GICD */ gic_wait_rwp(GIC_SPI_INT_BASE); /* Configure default priorities for all SPIs. */ - for (intid = GIC_SPI_INT_BASE; intid < num_ints; - intid += GIC_NUM_PRI_PER_REG) { + for (intid = GIC_SPI_INT_BASE; intid < num_ints; intid += GIC_NUM_PRI_PER_REG) { sys_write32(GIC_INT_DEF_PRI_X4, IPRIORITYR(base, intid)); } /* Configure all SPIs as active low, level triggered by default */ - for (intid = GIC_SPI_INT_BASE; intid < num_ints; - intid += GIC_NUM_CFG_PER_REG) { + for (intid = GIC_SPI_INT_BASE; intid < num_ints; intid += GIC_NUM_CFG_PER_REG) { idx = intid / GIC_NUM_CFG_PER_REG; sys_write32(0, ICFGR(base, idx)); } #ifdef CONFIG_ARMV8_A_NS /* Enable distributor with ARE */ - sys_write32(BIT(GICD_CTRL_ARE_NS) | BIT(GICD_CTLR_ENABLE_G1NS), - GICD_CTLR); + sys_write32(BIT(GICD_CTRL_ARE_NS) | BIT(GICD_CTLR_ENABLE_G1NS), GICD_CTLR); #elif defined(CONFIG_GIC_SINGLE_SECURITY_STATE) /* * For GIC single security state, the config GIC_SINGLE_SECURITY_STATE @@ -552,8 +537,7 @@ static void gicv3_dist_init(void) * similarly the GICD_CTLR_ENABLE_G1 and GICD_CTLR_ENABLE_G1NS share * BIT(1), we can reuse them. */ - sys_write32(BIT(GICD_CTRL_ARE_S) | BIT(GICD_CTLR_ENABLE_G1NS), - GICD_CTLR); + sys_write32(BIT(GICD_CTRL_ARE_S) | BIT(GICD_CTLR_ENABLE_G1NS), GICD_CTLR); #else /* enable Group 1 secure interrupts */ sys_set_bit(GICD_CTLR, GICD_CTLR_ENABLE_G1S); @@ -668,8 +652,8 @@ int arm_gic_init(const struct device *dev) return 0; } -DEVICE_DT_INST_DEFINE(0, arm_gic_init, NULL, NULL, NULL, - PRE_KERNEL_1, CONFIG_INTC_INIT_PRIORITY, NULL); +DEVICE_DT_INST_DEFINE(0, arm_gic_init, NULL, NULL, NULL, PRE_KERNEL_1, CONFIG_INTC_INIT_PRIORITY, + NULL); #ifdef CONFIG_SMP void arm_gic_secondary_init(void) diff --git a/drivers/interrupt_controller/intc_gicv3_priv.h b/drivers/interrupt_controller/intc_gicv3_priv.h index 30c7a6fa84d..986b0225043 100644 --- a/drivers/interrupt_controller/intc_gicv3_priv.h +++ b/drivers/interrupt_controller/intc_gicv3_priv.h @@ -13,263 +13,263 @@ #include /* Cache and Share ability for ITS & Redistributor LPI state tables */ -#define GIC_BASER_CACHE_NGNRNE 0x0UL /* Device-nGnRnE */ -#define GIC_BASER_CACHE_INNERLIKE 0x0UL /* Same as Inner Cacheability. */ -#define GIC_BASER_CACHE_NCACHEABLE 0x1UL /* Non-cacheable */ -#define GIC_BASER_CACHE_RAWT 0x2UL /* Cacheable R-allocate, W-through */ -#define GIC_BASER_CACHE_RAWB 0x3UL /* Cacheable R-allocate, W-back */ -#define GIC_BASER_CACHE_WAWT 0x4UL /* Cacheable W-allocate, W-through */ -#define GIC_BASER_CACHE_WAWB 0x5UL /* Cacheable W-allocate, W-back */ -#define GIC_BASER_CACHE_RAWAWT 0x6UL /* Cacheable R-allocate, W-allocate, W-through */ -#define GIC_BASER_CACHE_RAWAWB 0x7UL /* Cacheable R-allocate, W-allocate, W-back */ -#define GIC_BASER_SHARE_NO 0x0UL /* Non-shareable */ -#define GIC_BASER_SHARE_INNER 0x1UL /* Inner Shareable */ -#define GIC_BASER_SHARE_OUTER 0x2UL /* Outer Shareable */ +#define GIC_BASER_CACHE_NGNRNE 0x0UL /* Device-nGnRnE */ +#define GIC_BASER_CACHE_INNERLIKE 0x0UL /* Same as Inner Cacheability. */ +#define GIC_BASER_CACHE_NCACHEABLE 0x1UL /* Non-cacheable */ +#define GIC_BASER_CACHE_RAWT 0x2UL /* Cacheable R-allocate, W-through */ +#define GIC_BASER_CACHE_RAWB 0x3UL /* Cacheable R-allocate, W-back */ +#define GIC_BASER_CACHE_WAWT 0x4UL /* Cacheable W-allocate, W-through */ +#define GIC_BASER_CACHE_WAWB 0x5UL /* Cacheable W-allocate, W-back */ +#define GIC_BASER_CACHE_RAWAWT 0x6UL /* Cacheable R-allocate, W-allocate, W-through */ +#define GIC_BASER_CACHE_RAWAWB 0x7UL /* Cacheable R-allocate, W-allocate, W-back */ +#define GIC_BASER_SHARE_NO 0x0UL /* Non-shareable */ +#define GIC_BASER_SHARE_INNER 0x1UL /* Inner Shareable */ +#define GIC_BASER_SHARE_OUTER 0x2UL /* Outer Shareable */ /* SGI base is at 64K offset from Redistributor */ -#define GICR_SGI_BASE_OFF 0x10000 +#define GICR_SGI_BASE_OFF 0x10000 /* GICR registers offset from RD_base(n) */ -#define GICR_CTLR 0x0000 -#define GICR_IIDR 0x0004 -#define GICR_TYPER 0x0008 -#define GICR_STATUSR 0x0010 -#define GICR_WAKER 0x0014 -#define GICR_PWRR 0x0024 -#define GICR_PROPBASER 0x0070 -#define GICR_PENDBASER 0x0078 +#define GICR_CTLR 0x0000 +#define GICR_IIDR 0x0004 +#define GICR_TYPER 0x0008 +#define GICR_STATUSR 0x0010 +#define GICR_WAKER 0x0014 +#define GICR_PWRR 0x0024 +#define GICR_PROPBASER 0x0070 +#define GICR_PENDBASER 0x0078 /* Register bit definitions */ /* GICD_CTLR Interrupt group definitions */ -#define GICD_CTLR_ENABLE_G0 0 -#define GICD_CTLR_ENABLE_G1NS 1 -#define GICD_CTLR_ENABLE_G1S 2 -#define GICD_CTRL_ARE_S 4 -#define GICD_CTRL_ARE_NS 5 -#define GICD_CTRL_NS 6 -#define GICD_CGRL_E1NWF 7 +#define GICD_CTLR_ENABLE_G0 0 +#define GICD_CTLR_ENABLE_G1NS 1 +#define GICD_CTLR_ENABLE_G1S 2 +#define GICD_CTRL_ARE_S 4 +#define GICD_CTRL_ARE_NS 5 +#define GICD_CTRL_NS 6 +#define GICD_CGRL_E1NWF 7 /* GICD_CTLR Register write progress bit */ -#define GICD_CTLR_RWP 31 +#define GICD_CTLR_RWP 31 /* GICR_CTLR */ -#define GICR_CTLR_ENABLE_LPIS BIT(0) -#define GICR_CTLR_RWP 3 +#define GICR_CTLR_ENABLE_LPIS BIT(0) +#define GICR_CTLR_RWP 3 /* GICR_IIDR */ -#define GICR_IIDR_PRODUCT_ID_SHIFT 24 -#define GICR_IIDR_PRODUCT_ID_MASK 0xFFUL -#define GICR_IIDR_PRODUCT_ID_GET(_val) MASK_GET(_val, GICR_IIDR_PRODUCT_ID) +#define GICR_IIDR_PRODUCT_ID_SHIFT 24 +#define GICR_IIDR_PRODUCT_ID_MASK 0xFFUL +#define GICR_IIDR_PRODUCT_ID_GET(_val) MASK_GET(_val, GICR_IIDR_PRODUCT_ID) /* GICR_TYPER */ -#define GICR_TYPER_AFFINITY_VALUE_SHIFT 32 -#define GICR_TYPER_AFFINITY_VALUE_MASK 0xFFFFFFFFUL -#define GICR_TYPER_AFFINITY_VALUE_GET(_val) MASK_GET(_val, GICR_TYPER_AFFINITY_VALUE) -#define GICR_TYPER_LAST_SHIFT 4 -#define GICR_TYPER_LAST_MASK 0x1UL -#define GICR_TYPER_LAST_GET(_val) MASK_GET(_val, GICR_TYPER_LAST) -#define GICR_TYPER_PROCESSOR_NUMBER_SHIFT 8 -#define GICR_TYPER_PROCESSOR_NUMBER_MASK 0xFFFFUL -#define GICR_TYPER_PROCESSOR_NUMBER_GET(_val) MASK_GET(_val, GICR_TYPER_PROCESSOR_NUMBER) +#define GICR_TYPER_AFFINITY_VALUE_SHIFT 32 +#define GICR_TYPER_AFFINITY_VALUE_MASK 0xFFFFFFFFUL +#define GICR_TYPER_AFFINITY_VALUE_GET(_val) MASK_GET(_val, GICR_TYPER_AFFINITY_VALUE) +#define GICR_TYPER_LAST_SHIFT 4 +#define GICR_TYPER_LAST_MASK 0x1UL +#define GICR_TYPER_LAST_GET(_val) MASK_GET(_val, GICR_TYPER_LAST) +#define GICR_TYPER_PROCESSOR_NUMBER_SHIFT 8 +#define GICR_TYPER_PROCESSOR_NUMBER_MASK 0xFFFFUL +#define GICR_TYPER_PROCESSOR_NUMBER_GET(_val) MASK_GET(_val, GICR_TYPER_PROCESSOR_NUMBER) /* GICR_WAKER */ -#define GICR_WAKER_PS 1 -#define GICR_WAKER_CA 2 +#define GICR_WAKER_PS 1 +#define GICR_WAKER_CA 2 /* GICR_PWRR */ -#define GICR_PWRR_RDPD 0 -#define GICR_PWRR_RDAG 1 -#define GICR_PWRR_RDGPO 3 +#define GICR_PWRR_RDPD 0 +#define GICR_PWRR_RDAG 1 +#define GICR_PWRR_RDGPO 3 /* GICR_PROPBASER */ -#define GITR_PROPBASER_ID_BITS_MASK 0x1fUL -#define GITR_PROPBASER_INNER_CACHE_SHIFT 7 -#define GITR_PROPBASER_INNER_CACHE_MASK 0x7UL -#define GITR_PROPBASER_SHAREABILITY_SHIFT 10 -#define GITR_PROPBASER_SHAREABILITY_MASK 0x3UL -#define GITR_PROPBASER_ADDR_SHIFT 12 -#define GITR_PROPBASER_ADDR_MASK 0xFFFFFFFFFFUL -#define GITR_PROPBASER_OUTER_CACHE_SHIFT 56 -#define GITR_PROPBASER_OUTER_CACHE_MASK 0x7UL +#define GITR_PROPBASER_ID_BITS_MASK 0x1fUL +#define GITR_PROPBASER_INNER_CACHE_SHIFT 7 +#define GITR_PROPBASER_INNER_CACHE_MASK 0x7UL +#define GITR_PROPBASER_SHAREABILITY_SHIFT 10 +#define GITR_PROPBASER_SHAREABILITY_MASK 0x3UL +#define GITR_PROPBASER_ADDR_SHIFT 12 +#define GITR_PROPBASER_ADDR_MASK 0xFFFFFFFFFFUL +#define GITR_PROPBASER_OUTER_CACHE_SHIFT 56 +#define GITR_PROPBASER_OUTER_CACHE_MASK 0x7UL /* GICR_PENDBASER */ -#define GITR_PENDBASER_INNER_CACHE_SHIFT 7 -#define GITR_PENDBASER_INNER_CACHE_MASK 0x7UL -#define GITR_PENDBASER_SHAREABILITY_SHIFT 10 -#define GITR_PENDBASER_SHAREABILITY_MASK 0x3UL -#define GITR_PENDBASER_ADDR_SHIFT 16 -#define GITR_PENDBASER_ADDR_MASK 0xFFFFFFFFFUL -#define GITR_PENDBASER_OUTER_CACHE_SHIFT 56 -#define GITR_PENDBASER_OUTER_CACHE_MASK 0x7UL -#define GITR_PENDBASER_PTZ BIT64(62) +#define GITR_PENDBASER_INNER_CACHE_SHIFT 7 +#define GITR_PENDBASER_INNER_CACHE_MASK 0x7UL +#define GITR_PENDBASER_SHAREABILITY_SHIFT 10 +#define GITR_PENDBASER_SHAREABILITY_MASK 0x3UL +#define GITR_PENDBASER_ADDR_SHIFT 16 +#define GITR_PENDBASER_ADDR_MASK 0xFFFFFFFFFUL +#define GITR_PENDBASER_OUTER_CACHE_SHIFT 56 +#define GITR_PENDBASER_OUTER_CACHE_MASK 0x7UL +#define GITR_PENDBASER_PTZ BIT64(62) /* GITCD_IROUTER */ -#define GIC_DIST_IROUTER 0x6000 -#define IROUTER(base, n) (base + GIC_DIST_IROUTER + (n) * 8) +#define GIC_DIST_IROUTER 0x6000 +#define IROUTER(base, n) (base + GIC_DIST_IROUTER + (n) * 8) /* * ITS registers, offsets from ITS_base */ -#define GITS_CTLR 0x0000 -#define GITS_IIDR 0x0004 -#define GITS_TYPER 0x0008 -#define GITS_STATUSR 0x0040 -#define GITS_UMSIR 0x0048 -#define GITS_CBASER 0x0080 -#define GITS_CWRITER 0x0088 -#define GITS_CREADR 0x0090 -#define GITS_BASER(n) (0x0100 + ((n) * 8)) - -#define GITS_TRANSLATER 0x10040 +#define GITS_CTLR 0x0000 +#define GITS_IIDR 0x0004 +#define GITS_TYPER 0x0008 +#define GITS_STATUSR 0x0040 +#define GITS_UMSIR 0x0048 +#define GITS_CBASER 0x0080 +#define GITS_CWRITER 0x0088 +#define GITS_CREADR 0x0090 +#define GITS_BASER(n) (0x0100 + ((n) * 8)) + +#define GITS_TRANSLATER 0x10040 /* ITS CTLR register */ -#define GITS_CTLR_ENABLED_SHIFT 0 -#define GITS_CTLR_ENABLED_MASK 0x1UL -#define GITS_CTLR_ITS_NUMBER_SHIFT 4 -#define GITS_CTLR_ITS_NUMBER_MASK 0xfUL -#define GITS_CTLR_QUIESCENT_SHIFT 31 -#define GITS_CTLR_QUIESCENT_MASK 0x1UL +#define GITS_CTLR_ENABLED_SHIFT 0 +#define GITS_CTLR_ENABLED_MASK 0x1UL +#define GITS_CTLR_ITS_NUMBER_SHIFT 4 +#define GITS_CTLR_ITS_NUMBER_MASK 0xfUL +#define GITS_CTLR_QUIESCENT_SHIFT 31 +#define GITS_CTLR_QUIESCENT_MASK 0x1UL -#define GITS_CTLR_ENABLED_GET(_val) MASK_GET(_val, GITS_CTLR_ENABLED) -#define GITS_CTLR_QUIESCENT_GET(_val) MASK_GET(_val, GITS_CTLR_QUIESCENT) +#define GITS_CTLR_ENABLED_GET(_val) MASK_GET(_val, GITS_CTLR_ENABLED) +#define GITS_CTLR_QUIESCENT_GET(_val) MASK_GET(_val, GITS_CTLR_QUIESCENT) /* ITS TYPER register */ -#define GITS_TYPER_PHY_SHIFT 0 -#define GITS_TYPER_PHY_MASK 0x1UL -#define GITS_TYPER_VIRT_SHIFT 1 -#define GITS_TYPER_VIRT_MASK 0x1UL -#define GITS_TYPER_ITT_ENTRY_SIZE_SHIFT 4 -#define GITS_TYPER_ITT_ENTRY_SIZE_MASK 0xfUL -#define GITS_TYPER_IDBITS_SHIFT 8 -#define GITS_TYPER_IDBITS_MASK 0x1fUL -#define GITS_TYPER_DEVBITS_SHIFT 13 -#define GITS_TYPER_DEVBITS_MASK 0x1fUL -#define GITS_TYPER_SEIS_SHIFT 18 -#define GITS_TYPER_SEIS_MASK 0x1UL -#define GITS_TYPER_PTA_SHIFT 19 -#define GITS_TYPER_PTA_MASK 0x1UL -#define GITS_TYPER_HCC_SHIFT 24 -#define GITS_TYPER_HCC_MASK 0xffUL -#define GITS_TYPER_CIDBITS_SHIFT 32 -#define GITS_TYPER_CIDBITS_MASK 0xfUL -#define GITS_TYPER_CIL_SHIFT 36 -#define GITS_TYPER_CIL_MASK 0x1UL - -#define GITS_TYPER_ITT_ENTRY_SIZE_GET(_val) MASK_GET(_val, GITS_TYPER_ITT_ENTRY_SIZE) -#define GITS_TYPER_PTA_GET(_val) MASK_GET(_val, GITS_TYPER_PTA) -#define GITS_TYPER_HCC_GET(_val) MASK_GET(_val, GITS_TYPER_HCC) -#define GITS_TYPER_DEVBITS_GET(_val) MASK_GET(_val, GITS_TYPER_DEVBITS) +#define GITS_TYPER_PHY_SHIFT 0 +#define GITS_TYPER_PHY_MASK 0x1UL +#define GITS_TYPER_VIRT_SHIFT 1 +#define GITS_TYPER_VIRT_MASK 0x1UL +#define GITS_TYPER_ITT_ENTRY_SIZE_SHIFT 4 +#define GITS_TYPER_ITT_ENTRY_SIZE_MASK 0xfUL +#define GITS_TYPER_IDBITS_SHIFT 8 +#define GITS_TYPER_IDBITS_MASK 0x1fUL +#define GITS_TYPER_DEVBITS_SHIFT 13 +#define GITS_TYPER_DEVBITS_MASK 0x1fUL +#define GITS_TYPER_SEIS_SHIFT 18 +#define GITS_TYPER_SEIS_MASK 0x1UL +#define GITS_TYPER_PTA_SHIFT 19 +#define GITS_TYPER_PTA_MASK 0x1UL +#define GITS_TYPER_HCC_SHIFT 24 +#define GITS_TYPER_HCC_MASK 0xffUL +#define GITS_TYPER_CIDBITS_SHIFT 32 +#define GITS_TYPER_CIDBITS_MASK 0xfUL +#define GITS_TYPER_CIL_SHIFT 36 +#define GITS_TYPER_CIL_MASK 0x1UL + +#define GITS_TYPER_ITT_ENTRY_SIZE_GET(_val) MASK_GET(_val, GITS_TYPER_ITT_ENTRY_SIZE) +#define GITS_TYPER_PTA_GET(_val) MASK_GET(_val, GITS_TYPER_PTA) +#define GITS_TYPER_HCC_GET(_val) MASK_GET(_val, GITS_TYPER_HCC) +#define GITS_TYPER_DEVBITS_GET(_val) MASK_GET(_val, GITS_TYPER_DEVBITS) /* ITS COMMON BASER / CBASER register */ /* ITS CBASER register */ -#define GITS_CBASER_SIZE_SHIFT 0 -#define GITS_CBASER_SIZE_MASK 0xffUL -#define GITS_CBASER_SHAREABILITY_SHIFT 10 -#define GITS_CBASER_SHAREABILITY_MASK 0x3UL -#define GITS_CBASER_ADDR_SHIFT 12 -#define GITS_CBASER_ADDR_MASK 0xfffffffffUL -#define GITS_CBASER_OUTER_CACHE_SHIFT 53 -#define GITS_CBASER_OUTER_CACHE_MASK 0x7UL -#define GITS_CBASER_INNER_CACHE_SHIFT 59 -#define GITS_CBASER_INNER_CACHE_MASK 0x7UL -#define GITS_CBASER_VALID_SHIFT 63 -#define GITS_CBASER_VALID_MASK 0x1UL +#define GITS_CBASER_SIZE_SHIFT 0 +#define GITS_CBASER_SIZE_MASK 0xffUL +#define GITS_CBASER_SHAREABILITY_SHIFT 10 +#define GITS_CBASER_SHAREABILITY_MASK 0x3UL +#define GITS_CBASER_ADDR_SHIFT 12 +#define GITS_CBASER_ADDR_MASK 0xfffffffffUL +#define GITS_CBASER_OUTER_CACHE_SHIFT 53 +#define GITS_CBASER_OUTER_CACHE_MASK 0x7UL +#define GITS_CBASER_INNER_CACHE_SHIFT 59 +#define GITS_CBASER_INNER_CACHE_MASK 0x7UL +#define GITS_CBASER_VALID_SHIFT 63 +#define GITS_CBASER_VALID_MASK 0x1UL /* ITS BASER register */ -#define GITS_BASER_SIZE_SHIFT 0 -#define GITS_BASER_SIZE_MASK 0xffUL -#define GITS_BASER_PAGE_SIZE_SHIFT 8 -#define GITS_BASER_PAGE_SIZE_MASK 0x3UL -#define GITS_BASER_PAGE_SIZE_4K 0 -#define GITS_BASER_PAGE_SIZE_16K 1 -#define GITS_BASER_PAGE_SIZE_64K 2 -#define GITS_BASER_SHAREABILITY_SHIFT 10 -#define GITS_BASER_SHAREABILITY_MASK 0x3UL -#define GITS_BASER_ADDR_SHIFT 12 -#define GITS_BASER_ADDR_MASK 0xfffffffff -#define GITS_BASER_ENTRY_SIZE_SHIFT 48 -#define GITS_BASER_ENTRY_SIZE_MASK 0x1fUL -#define GITS_BASER_OUTER_CACHE_SHIFT 53 -#define GITS_BASER_OUTER_CACHE_MASK 0x7UL -#define GITS_BASER_TYPE_SHIFT 56 -#define GITS_BASER_TYPE_MASK 0x7UL -#define GITS_BASER_INNER_CACHE_SHIFT 59 -#define GITS_BASER_INNER_CACHE_MASK 0x7UL -#define GITS_BASER_INDIRECT_SHIFT 62 -#define GITS_BASER_INDIRECT_MASK 0x1UL -#define GITS_BASER_VALID_SHIFT 63 -#define GITS_BASER_VALID_MASK 0x1UL - -#define GITS_BASER_TYPE_NONE 0 -#define GITS_BASER_TYPE_DEVICE 1 -#define GITS_BASER_TYPE_COLLECTION 4 - -#define GITS_BASER_TYPE_GET(_val) MASK_GET(_val, GITS_BASER_TYPE) -#define GITS_BASER_PAGE_SIZE_GET(_val) MASK_GET(_val, GITS_BASER_PAGE_SIZE) -#define GITS_BASER_ENTRY_SIZE_GET(_val) MASK_GET(_val, GITS_BASER_ENTRY_SIZE) -#define GITS_BASER_INDIRECT_GET(_val) MASK_GET(_val, GITS_BASER_INDIRECT) - -#define GITS_BASER_NR_REGS 8 +#define GITS_BASER_SIZE_SHIFT 0 +#define GITS_BASER_SIZE_MASK 0xffUL +#define GITS_BASER_PAGE_SIZE_SHIFT 8 +#define GITS_BASER_PAGE_SIZE_MASK 0x3UL +#define GITS_BASER_PAGE_SIZE_4K 0 +#define GITS_BASER_PAGE_SIZE_16K 1 +#define GITS_BASER_PAGE_SIZE_64K 2 +#define GITS_BASER_SHAREABILITY_SHIFT 10 +#define GITS_BASER_SHAREABILITY_MASK 0x3UL +#define GITS_BASER_ADDR_SHIFT 12 +#define GITS_BASER_ADDR_MASK 0xfffffffff +#define GITS_BASER_ENTRY_SIZE_SHIFT 48 +#define GITS_BASER_ENTRY_SIZE_MASK 0x1fUL +#define GITS_BASER_OUTER_CACHE_SHIFT 53 +#define GITS_BASER_OUTER_CACHE_MASK 0x7UL +#define GITS_BASER_TYPE_SHIFT 56 +#define GITS_BASER_TYPE_MASK 0x7UL +#define GITS_BASER_INNER_CACHE_SHIFT 59 +#define GITS_BASER_INNER_CACHE_MASK 0x7UL +#define GITS_BASER_INDIRECT_SHIFT 62 +#define GITS_BASER_INDIRECT_MASK 0x1UL +#define GITS_BASER_VALID_SHIFT 63 +#define GITS_BASER_VALID_MASK 0x1UL + +#define GITS_BASER_TYPE_NONE 0 +#define GITS_BASER_TYPE_DEVICE 1 +#define GITS_BASER_TYPE_COLLECTION 4 + +#define GITS_BASER_TYPE_GET(_val) MASK_GET(_val, GITS_BASER_TYPE) +#define GITS_BASER_PAGE_SIZE_GET(_val) MASK_GET(_val, GITS_BASER_PAGE_SIZE) +#define GITS_BASER_ENTRY_SIZE_GET(_val) MASK_GET(_val, GITS_BASER_ENTRY_SIZE) +#define GITS_BASER_INDIRECT_GET(_val) MASK_GET(_val, GITS_BASER_INDIRECT) + +#define GITS_BASER_NR_REGS 8 /* ITS Commands */ -#define GITS_CMD_ID_MOVI 0x01 -#define GITS_CMD_ID_INT 0x03 -#define GITS_CMD_ID_CLEAR 0x04 -#define GITS_CMD_ID_SYNC 0x05 -#define GITS_CMD_ID_MAPD 0x08 -#define GITS_CMD_ID_MAPC 0x09 -#define GITS_CMD_ID_MAPTI 0x0a -#define GITS_CMD_ID_MAPI 0x0b -#define GITS_CMD_ID_INV 0x0c -#define GITS_CMD_ID_INVALL 0x0d -#define GITS_CMD_ID_MOVALL 0x0e -#define GITS_CMD_ID_DISCARD 0x0f - -#define GITS_CMD_ID_OFFSET 0 -#define GITS_CMD_ID_SHIFT 0 -#define GITS_CMD_ID_MASK 0xffUL - -#define GITS_CMD_DEVICEID_OFFSET 0 -#define GITS_CMD_DEVICEID_SHIFT 32 -#define GITS_CMD_DEVICEID_MASK 0xffffffffUL - -#define GITS_CMD_SIZE_OFFSET 1 -#define GITS_CMD_SIZE_SHIFT 0 -#define GITS_CMD_SIZE_MASK 0x1fUL - -#define GITS_CMD_EVENTID_OFFSET 1 -#define GITS_CMD_EVENTID_SHIFT 0 -#define GITS_CMD_EVENTID_MASK 0xffffffffUL - -#define GITS_CMD_PINTID_OFFSET 1 -#define GITS_CMD_PINTID_SHIFT 32 -#define GITS_CMD_PINTID_MASK 0xffffffffUL - -#define GITS_CMD_ICID_OFFSET 2 -#define GITS_CMD_ICID_SHIFT 0 -#define GITS_CMD_ICID_MASK 0xffffUL - -#define GITS_CMD_ITTADDR_OFFSET 2 -#define GITS_CMD_ITTADDR_SHIFT 8 -#define GITS_CMD_ITTADDR_MASK 0xffffffffffUL -#define GITS_CMD_ITTADDR_ALIGN GITS_CMD_ITTADDR_SHIFT -#define GITS_CMD_ITTADDR_ALIGN_SZ (BIT(0) << GITS_CMD_ITTADDR_ALIGN) - -#define GITS_CMD_RDBASE_OFFSET 2 -#define GITS_CMD_RDBASE_SHIFT 16 -#define GITS_CMD_RDBASE_MASK 0xffffffffUL -#define GITS_CMD_RDBASE_ALIGN GITS_CMD_RDBASE_SHIFT - -#define GITS_CMD_VALID_OFFSET 2 -#define GITS_CMD_VALID_SHIFT 63 -#define GITS_CMD_VALID_MASK 0x1UL - -#define MASK(__basename) (__basename##_MASK << __basename##_SHIFT) -#define MASK_SET(__val, __basename) (((__val) & __basename##_MASK) << __basename##_SHIFT) -#define MASK_GET(__reg, __basename) (((__reg) >> __basename##_SHIFT) & __basename##_MASK) +#define GITS_CMD_ID_MOVI 0x01 +#define GITS_CMD_ID_INT 0x03 +#define GITS_CMD_ID_CLEAR 0x04 +#define GITS_CMD_ID_SYNC 0x05 +#define GITS_CMD_ID_MAPD 0x08 +#define GITS_CMD_ID_MAPC 0x09 +#define GITS_CMD_ID_MAPTI 0x0a +#define GITS_CMD_ID_MAPI 0x0b +#define GITS_CMD_ID_INV 0x0c +#define GITS_CMD_ID_INVALL 0x0d +#define GITS_CMD_ID_MOVALL 0x0e +#define GITS_CMD_ID_DISCARD 0x0f + +#define GITS_CMD_ID_OFFSET 0 +#define GITS_CMD_ID_SHIFT 0 +#define GITS_CMD_ID_MASK 0xffUL + +#define GITS_CMD_DEVICEID_OFFSET 0 +#define GITS_CMD_DEVICEID_SHIFT 32 +#define GITS_CMD_DEVICEID_MASK 0xffffffffUL + +#define GITS_CMD_SIZE_OFFSET 1 +#define GITS_CMD_SIZE_SHIFT 0 +#define GITS_CMD_SIZE_MASK 0x1fUL + +#define GITS_CMD_EVENTID_OFFSET 1 +#define GITS_CMD_EVENTID_SHIFT 0 +#define GITS_CMD_EVENTID_MASK 0xffffffffUL + +#define GITS_CMD_PINTID_OFFSET 1 +#define GITS_CMD_PINTID_SHIFT 32 +#define GITS_CMD_PINTID_MASK 0xffffffffUL + +#define GITS_CMD_ICID_OFFSET 2 +#define GITS_CMD_ICID_SHIFT 0 +#define GITS_CMD_ICID_MASK 0xffffUL + +#define GITS_CMD_ITTADDR_OFFSET 2 +#define GITS_CMD_ITTADDR_SHIFT 8 +#define GITS_CMD_ITTADDR_MASK 0xffffffffffUL +#define GITS_CMD_ITTADDR_ALIGN GITS_CMD_ITTADDR_SHIFT +#define GITS_CMD_ITTADDR_ALIGN_SZ (BIT(0) << GITS_CMD_ITTADDR_ALIGN) + +#define GITS_CMD_RDBASE_OFFSET 2 +#define GITS_CMD_RDBASE_SHIFT 16 +#define GITS_CMD_RDBASE_MASK 0xffffffffUL +#define GITS_CMD_RDBASE_ALIGN GITS_CMD_RDBASE_SHIFT + +#define GITS_CMD_VALID_OFFSET 2 +#define GITS_CMD_VALID_SHIFT 63 +#define GITS_CMD_VALID_MASK 0x1UL + +#define MASK(__basename) (__basename##_MASK << __basename##_SHIFT) +#define MASK_SET(__val, __basename) (((__val) & __basename##_MASK) << __basename##_SHIFT) +#define MASK_GET(__reg, __basename) (((__reg) >> __basename##_SHIFT) & __basename##_MASK) #ifdef CONFIG_GIC_V3_ITS void its_rdist_map(void); diff --git a/include/zephyr/drivers/interrupt_controller/gic.h b/include/zephyr/drivers/interrupt_controller/gic.h index ab6aeffe3d2..7d6fffb09e0 100644 --- a/include/zephyr/drivers/interrupt_controller/gic.h +++ b/include/zephyr/drivers/interrupt_controller/gic.h @@ -20,8 +20,8 @@ * GIC Register Interface Base Addresses */ -#define GIC_DIST_BASE DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0) -#define GIC_CPU_BASE DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1) +#define GIC_DIST_BASE DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0) +#define GIC_CPU_BASE DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1) /* * GIC Distributor Interface @@ -32,70 +32,70 @@ * v1 ICDDCR * v2/v3 GICD_CTLR */ -#define GICD_CTLR (GIC_DIST_BASE + 0x0) +#define GICD_CTLR (GIC_DIST_BASE + 0x0) /* * 0x004 Interrupt Controller Type Register * v1 ICDICTR * v2/v3 GICD_TYPER */ -#define GICD_TYPER (GIC_DIST_BASE + 0x4) +#define GICD_TYPER (GIC_DIST_BASE + 0x4) /* * 0x008 Distributor Implementer Identification Register * v1 ICDIIDR * v2/v3 GICD_IIDR */ -#define GICD_IIDR (GIC_DIST_BASE + 0x8) +#define GICD_IIDR (GIC_DIST_BASE + 0x8) /* * 0x080 Interrupt Group Registers * v1 ICDISRn * v2/v3 GICD_IGROUPRn */ -#define GICD_IGROUPRn (GIC_DIST_BASE + 0x80) +#define GICD_IGROUPRn (GIC_DIST_BASE + 0x80) /* * 0x100 Interrupt Set-Enable Registers * v1 ICDISERn * v2/v3 GICD_ISENABLERn */ -#define GICD_ISENABLERn (GIC_DIST_BASE + 0x100) +#define GICD_ISENABLERn (GIC_DIST_BASE + 0x100) /* * 0x180 Interrupt Clear-Enable Registers * v1 ICDICERn * v2/v3 GICD_ICENABLERn */ -#define GICD_ICENABLERn (GIC_DIST_BASE + 0x180) +#define GICD_ICENABLERn (GIC_DIST_BASE + 0x180) /* * 0x200 Interrupt Set-Pending Registers * v1 ICDISPRn * v2/v3 GICD_ISPENDRn */ -#define GICD_ISPENDRn (GIC_DIST_BASE + 0x200) +#define GICD_ISPENDRn (GIC_DIST_BASE + 0x200) /* * 0x280 Interrupt Clear-Pending Registers * v1 ICDICPRn * v2/v3 GICD_ICPENDRn */ -#define GICD_ICPENDRn (GIC_DIST_BASE + 0x280) +#define GICD_ICPENDRn (GIC_DIST_BASE + 0x280) /* * 0x300 Interrupt Set-Active Registers * v1 ICDABRn * v2/v3 GICD_ISACTIVERn */ -#define GICD_ISACTIVERn (GIC_DIST_BASE + 0x300) +#define GICD_ISACTIVERn (GIC_DIST_BASE + 0x300) #if CONFIG_GIC_VER >= 2 /* * 0x380 Interrupt Clear-Active Registers * v2/v3 GICD_ICACTIVERn */ -#define GICD_ICACTIVERn (GIC_DIST_BASE + 0x380) +#define GICD_ICACTIVERn (GIC_DIST_BASE + 0x380) #endif /* @@ -103,28 +103,28 @@ * v1 ICDIPRn * v2/v3 GICD_IPRIORITYRn */ -#define GICD_IPRIORITYRn (GIC_DIST_BASE + 0x400) +#define GICD_IPRIORITYRn (GIC_DIST_BASE + 0x400) /* * 0x800 Interrupt Processor Targets Registers * v1 ICDIPTRn * v2/v3 GICD_ITARGETSRn */ -#define GICD_ITARGETSRn (GIC_DIST_BASE + 0x800) +#define GICD_ITARGETSRn (GIC_DIST_BASE + 0x800) /* * 0xC00 Interrupt Configuration Registers * v1 ICDICRn * v2/v3 GICD_ICFGRn */ -#define GICD_ICFGRn (GIC_DIST_BASE + 0xc00) +#define GICD_ICFGRn (GIC_DIST_BASE + 0xc00) /* * 0xF00 Software Generated Interrupt Register * v1 ICDSGIR * v2/v3 GICD_SGIR */ -#define GICD_SGIR (GIC_DIST_BASE + 0xf00) +#define GICD_SGIR (GIC_DIST_BASE + 0xf00) /* * GIC CPU Interface @@ -137,116 +137,110 @@ * v1 ICCICR * v2/v3 GICC_CTLR */ -#define GICC_CTLR (GIC_CPU_BASE + 0x0) +#define GICC_CTLR (GIC_CPU_BASE + 0x0) /* * 0x0004 Interrupt Priority Mask Register * v1 ICCPMR * v2/v3 GICC_PMR */ -#define GICC_PMR (GIC_CPU_BASE + 0x4) +#define GICC_PMR (GIC_CPU_BASE + 0x4) /* * 0x0008 Binary Point Register * v1 ICCBPR * v2/v3 GICC_BPR */ -#define GICC_BPR (GIC_CPU_BASE + 0x8) +#define GICC_BPR (GIC_CPU_BASE + 0x8) /* * 0x000C Interrupt Acknowledge Register * v1 ICCIAR * v2/v3 GICC_IAR */ -#define GICC_IAR (GIC_CPU_BASE + 0xc) +#define GICC_IAR (GIC_CPU_BASE + 0xc) /* * 0x0010 End of Interrupt Register * v1 ICCEOIR * v2/v3 GICC_EOIR */ -#define GICC_EOIR (GIC_CPU_BASE + 0x10) - +#define GICC_EOIR (GIC_CPU_BASE + 0x10) /* * Helper Constants */ /* GICC_CTLR */ -#define GICC_CTLR_ENABLEGRP0 BIT(0) -#define GICC_CTLR_ENABLEGRP1 BIT(1) +#define GICC_CTLR_ENABLEGRP0 BIT(0) +#define GICC_CTLR_ENABLEGRP1 BIT(1) -#define GICC_CTLR_ENABLE_MASK (GICC_CTLR_ENABLEGRP0 | GICC_CTLR_ENABLEGRP1) +#define GICC_CTLR_ENABLE_MASK (GICC_CTLR_ENABLEGRP0 | GICC_CTLR_ENABLEGRP1) #if defined(CONFIG_GIC_V2) -#define GICC_CTLR_FIQBYPDISGRP0 BIT(5) -#define GICC_CTLR_IRQBYPDISGRP0 BIT(6) -#define GICC_CTLR_FIQBYPDISGRP1 BIT(7) -#define GICC_CTLR_IRQBYPDISGRP1 BIT(8) +#define GICC_CTLR_FIQBYPDISGRP0 BIT(5) +#define GICC_CTLR_IRQBYPDISGRP0 BIT(6) +#define GICC_CTLR_FIQBYPDISGRP1 BIT(7) +#define GICC_CTLR_IRQBYPDISGRP1 BIT(8) -#define GICC_CTLR_BYPASS_MASK (GICC_CTLR_FIQBYPDISGRP0 | \ - GICC_CTLR_IRQBYPDISGRP1 | \ - GICC_CTLR_FIQBYPDISGRP1 | \ - GICC_CTLR_IRQBYPDISGRP1) +#define GICC_CTLR_BYPASS_MASK \ + (GICC_CTLR_FIQBYPDISGRP0 | GICC_CTLR_IRQBYPDISGRP1 | GICC_CTLR_FIQBYPDISGRP1 | \ + GICC_CTLR_IRQBYPDISGRP1) #endif /* CONFIG_GIC_V2 */ /* GICD_SGIR */ -#define GICD_SGIR_TGTFILT(x) ((x) << 24) -#define GICD_SGIR_TGTFILT_CPULIST GICD_SGIR_TGTFILT(0b00) -#define GICD_SGIR_TGTFILT_ALLBUTREQ GICD_SGIR_TGTFILT(0b01) -#define GICD_SGIR_TGTFILT_REQONLY GICD_SGIR_TGTFILT(0b10) +#define GICD_SGIR_TGTFILT(x) ((x) << 24) +#define GICD_SGIR_TGTFILT_CPULIST GICD_SGIR_TGTFILT(0b00) +#define GICD_SGIR_TGTFILT_ALLBUTREQ GICD_SGIR_TGTFILT(0b01) +#define GICD_SGIR_TGTFILT_REQONLY GICD_SGIR_TGTFILT(0b10) -#define GICD_SGIR_CPULIST(x) ((x) << 16) -#define GICD_SGIR_CPULIST_CPU(n) GICD_SGIR_CPULIST(BIT(n)) -#define GICD_SGIR_CPULIST_MASK 0xff +#define GICD_SGIR_CPULIST(x) ((x) << 16) +#define GICD_SGIR_CPULIST_CPU(n) GICD_SGIR_CPULIST(BIT(n)) +#define GICD_SGIR_CPULIST_MASK 0xff -#define GICD_SGIR_NSATT BIT(15) +#define GICD_SGIR_NSATT BIT(15) -#define GICD_SGIR_SGIINTID(x) (x) +#define GICD_SGIR_SGIINTID(x) (x) #endif /* CONFIG_GIC_VER <= 2 */ - /* GICD_ICFGR */ -#define GICD_ICFGR_MASK BIT_MASK(2) -#define GICD_ICFGR_TYPE BIT(1) +#define GICD_ICFGR_MASK BIT_MASK(2) +#define GICD_ICFGR_TYPE BIT(1) /* GICD_TYPER.ITLinesNumber 0:4 */ -#define GICD_TYPER_ITLINESNUM_MASK 0x1f +#define GICD_TYPER_ITLINESNUM_MASK 0x1f /* GICD_TYPER.IDbits */ -#define GICD_TYPER_IDBITS(typer) ((((typer) >> 19) & 0x1f) + 1) +#define GICD_TYPER_IDBITS(typer) ((((typer) >> 19) & 0x1f) + 1) /* * Common Helper Constants */ -#define GIC_SGI_INT_BASE 0 -#define GIC_PPI_INT_BASE 16 - -#define GIC_IS_SGI(intid) (((intid) >= GIC_SGI_INT_BASE) && \ - ((intid) < GIC_PPI_INT_BASE)) +#define GIC_SGI_INT_BASE 0 +#define GIC_PPI_INT_BASE 16 +#define GIC_IS_SGI(intid) (((intid) >= GIC_SGI_INT_BASE) && ((intid) < GIC_PPI_INT_BASE)) -#define GIC_SPI_INT_BASE 32 +#define GIC_SPI_INT_BASE 32 -#define GIC_SPI_MAX_INTID 1019 +#define GIC_SPI_MAX_INTID 1019 -#define GIC_IS_SPI(intid) (((intid) >= GIC_SPI_INT_BASE) && \ - ((intid) <= GIC_SPI_MAX_INTID)) +#define GIC_IS_SPI(intid) (((intid) >= GIC_SPI_INT_BASE) && ((intid) <= GIC_SPI_MAX_INTID)) -#define GIC_NUM_INTR_PER_REG 32 +#define GIC_NUM_INTR_PER_REG 32 -#define GIC_NUM_CFG_PER_REG 16 +#define GIC_NUM_CFG_PER_REG 16 -#define GIC_NUM_PRI_PER_REG 4 +#define GIC_NUM_PRI_PER_REG 4 /* GIC idle priority : value '0xff' will allow all interrupts */ -#define GIC_IDLE_PRIO 0xff +#define GIC_IDLE_PRIO 0xff /* Priority levels 0:255 */ -#define GIC_PRI_MASK 0xff +#define GIC_PRI_MASK 0xff /* * '0xa0'is used to initialize each interrupt default priority. @@ -255,13 +249,13 @@ * The values of individual interrupt and default has to be chosen * carefully if PMR and BPR based nesting and preemption has to be done. */ -#define GIC_INT_DEF_PRI_X4 0xa0a0a0a0 +#define GIC_INT_DEF_PRI_X4 0xa0a0a0a0 /* GIC special interrupt id */ -#define GIC_INTID_SPURIOUS 1023 +#define GIC_INTID_SPURIOUS 1023 /* Fixme: update from platform specific define or dt */ -#define GIC_NUM_CPU_IF CONFIG_MP_MAX_NUM_CPUS +#define GIC_NUM_CPU_IF CONFIG_MP_MAX_NUM_CPUS #ifndef _ASMLANGUAGE @@ -323,8 +317,7 @@ void arm_gic_irq_clear_pending(unsigned int irq); * @param prio interrupt priority * @param flags interrupt flags */ -void arm_gic_irq_set_priority( - unsigned int irq, unsigned int prio, unsigned int flags); +void arm_gic_irq_set_priority(unsigned int irq, unsigned int prio, unsigned int flags); /** * @brief Get active interrupt ID @@ -355,8 +348,7 @@ void arm_gic_secondary_init(void); * Aff level 1 2 3 will be extracted by api. * @param target_list bitmask of target cores */ -void gic_raise_sgi(unsigned int sgi_id, uint64_t target_aff, - uint16_t target_list); +void gic_raise_sgi(unsigned int sgi_id, uint64_t target_aff, uint16_t target_list); #endif /* !_ASMLANGUAGE */