Browse Source
Port M7 core of mimx8mp_evk to HWMv2 Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>collab-hwm
Daniel DeGrasse
1 year ago
committed by
Jamie
16 changed files with 121 additions and 250 deletions
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# MIMX8MP EVK board |
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# Copyright (c) 2021, Laird Connectivity |
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# SPDX-License-Identifier: Apache-2.0 |
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config BOARD_MIMX8MP_EVK |
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bool "NXP i.MX8M Plus EVK" |
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depends on SOC_SERIES_IMX8ML_M7 |
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select SOC_PART_NUMBER_MIMX8ML8DVNLZ |
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# |
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# Copyright (c) 2021, Laird Connectivity |
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# |
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# SPDX-License-Identifier: Apache-2.0 |
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# |
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board_set_debugger_ifnset(jlink) |
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board_set_flasher_ifnset(jlink) |
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board_runner_args(jlink "--device=MIMX8ML8_M7") |
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include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) |
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Before Width: | Height: | Size: 54 KiB |
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.. _mimx8ml_evk: |
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NXP MIMX8MP EVK |
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############### |
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Overview |
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******** |
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i.MX8M Plus EVK board is based on NXP i.MX8M Plus applications |
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processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M7 core. |
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Zephyr OS is ported to run on the Cortex®-M7 core. |
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- Board features: |
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- RAM: 6GB LPDDR4 |
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- Storage: |
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- SanDisk 32GB eMMC5.1 |
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- Micron 32MB QSPI NOR |
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- microSD Socket |
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- Wireless: |
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- WiFi: 2.4/5GHz IEEE 802.11b/g/n/ac |
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- Bluetooth: v4.2 |
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- USB: |
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- USB 3.0 Type C for Power |
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- USB 3.0 Type A |
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- USB 3.0 Type C |
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- 2x 10/100/1000 Ethernet (1x w/ TSN) |
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- PCI-E M.2 |
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- Connectors: |
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- 40-Pin Dual Row Header |
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- LEDs: |
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- 1x Power status LED |
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- 1x UART LED |
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- Debug |
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- JTAG connector |
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- MicroUSB for UART debug, two COM ports for A53 and one for M7 |
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.. image:: img/I.MX8MPLUS-PLUS-EVK-TOP.jpg |
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:align: center |
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:alt: MIMX8MP EVK |
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More information about the board can be found at the |
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`NXP website`_. |
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Supported Features |
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================== |
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The Zephyr mimx8mp_evk board configuration supports the following hardware |
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features: |
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+-----------+------------+-------------------------------------+ |
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| Interface | Controller | Driver/Component | |
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+===========+============+=====================================+ |
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| NVIC | on-chip | nested vector interrupt controller | |
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+-----------+------------+-------------------------------------+ |
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| SYSTICK | on-chip | systick | |
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+-----------+------------+-------------------------------------+ |
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| CLOCK | on-chip | clock_control | |
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+-----------+------------+-------------------------------------+ |
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| PINMUX | on-chip | pinmux | |
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+-----------+------------+-------------------------------------+ |
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| UART | on-chip | serial port-polling; | |
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| | | serial port-interrupt | |
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+-----------+------------+-------------------------------------+ |
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The default configuration can be found in the defconfig file: |
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:zephyr_file:`boards/arm/mimx8mp_evk/mimx8mp_evk_defconfig`. |
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Other hardware features are not currently supported by the port. |
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Connections and IOs |
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=================== |
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MIMX8MP EVK board was tested with the following pinmux controller |
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configuration. |
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+---------------+-----------------+---------------------------+ |
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| Board Name | SoC Name | Usage | |
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+===============+=================+===========================+ |
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| UART4 RXD | UART4_TXD | UART Console | |
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+---------------+-----------------+---------------------------+ |
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| UART4 TXD | UART4_RXD | UART Console | |
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+---------------+-----------------+---------------------------+ |
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System Clock |
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============ |
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The M7 Core is configured to run at a 800 MHz clock speed. |
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Serial Port |
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=========== |
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The i.MX8M Plus SoC has four UARTs. UART_4 is configured for the console and |
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the remaining are not used/tested. |
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Programming and Debugging |
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************************* |
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The MIMX8MP EVK board doesn't have QSPI flash for the M7, and it needs |
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to be started by the A53 core. The A53 core is responsible to load the M7 binary |
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application into the RAM, put the M7 in reset, set the M7 Program Counter and |
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Stack Pointer, and get the M7 out of reset. The A53 can perform these steps at |
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bootloader level or after the Linux system has booted. |
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The M7 can use up to 3 different RAMs (currently, only two configurations are |
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supported: ITCM and DDR). These are the memory mapping for A53 and M7: |
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+------------+-------------------------+------------------------+-----------------------+----------------------+ |
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| Region | Cortex-A53 | Cortex-M7 (System Bus) | Cortex-M7 (Code Bus) | Size | |
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+============+=========================+========================+=======================+======================+ |
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| OCRAM | 0x00900000-0x0098FFFF | 0x20200000-0x2028FFFF | 0x00900000-0x0098FFFF | 576KB | |
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+------------+-------------------------+------------------------+-----------------------+----------------------+ |
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| DTCM | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB | |
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+------------+-------------------------+------------------------+-----------------------+----------------------+ |
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| ITCM | 0x007E0000-0x007FFFFF | | 0x00000000-0x0001FFFF | 128KB | |
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+------------+-------------------------+------------------------+-----------------------+----------------------+ |
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| OCRAM_S | 0x00180000-0x00188FFF | 0x20180000-0x20188FFF | 0x00180000-0x00188FFF | 36KB | |
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+------------+-------------------------+------------------------+-----------------------+----------------------+ |
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| DDR | 0x80000000-0x803FFFFF | 0x80200000-0x803FFFFF | 0x80000000-0x801FFFFF | 2MB | |
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+------------+-------------------------+------------------------+-----------------------+----------------------+ |
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For more information about memory mapping see the |
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`i.MX 8M Plus Applications Processor Reference Manual`_ (section 2.1 to 2.3) |
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At compilation time you have to choose which RAM will be used. This |
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configuration is done based on board name (mimx8mp_evk_itcm for ITCM and |
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mimx8mp_evk_ddr for DDR). |
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Load and run Zephyr on M7 from A53 using u-boot by copying the compiled |
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``zephyr.bin`` to the first FAT partition of the SD card and plug the SD |
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card into the board. Power it up and stop the u-boot execution at prompt. |
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Load the M7 binary onto the desired memory and start its execution using: |
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ITCM |
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=== |
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.. code-block:: console |
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fatload mmc 0:1 0x48000000 zephyr.bin |
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cp.b 0x48000000 0x7e0000 20000 |
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bootaux 0x7e0000 |
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DDR |
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=== |
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.. code-block:: console |
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fatload mmc 0:1 0x80000000 zephyr.bin |
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dcache flush |
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bootaux 0x80000000 |
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Debugging |
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========= |
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MIMX8MP EVK board can be debugged by connecting an external JLink |
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JTAG debugger to the J24 debug connector and to the PC. Then |
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the application can be debugged using the usual way. |
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Here is an example for the :ref:`hello_world` application. |
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.. zephyr-app-commands:: |
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:zephyr-app: samples/hello_world |
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:board: mimx8mp_evk_itcm |
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:goals: debug |
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Open a serial terminal, step through the application in your debugger, and you |
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should see the following message in the terminal: |
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.. code-block:: console |
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*** Booting Zephyr OS build v2.7.99-1310-g2801bf644a91 *** |
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Hello World! mimx8mp_evk |
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References |
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========== |
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.. _NXP website: |
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https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/evaluation-kit-for-the-i-mx-8m-plus-applications-processor:8MPLUSLPD4-EVK |
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.. _i.MX 8M Plus Applications Processor Reference Manual: |
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https://www.nxp.com/webapp/Download?colCode=IMX8MPRM |
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/* |
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* Copyright (c) 2022, NXP |
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* SPDX-License-Identifier: Apache-2.0 |
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* |
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* Note: File generated by gen_board_pinctrl.py |
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* from MIMX8MP-EVK-REV-A.mex |
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*/ |
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#include <nxp/nxp_imx/mimx8ml8dvnlz-pinctrl.dtsi> |
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&pinctrl { |
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uart4_default: uart4_default { |
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group0 { |
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pinmux = <&iomuxc_uart4_rxd_uart_rx_uart4_rx>, |
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<&iomuxc_uart4_txd_uart_tx_uart4_tx>; |
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bias-pull-up; |
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slew-rate = "slow"; |
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drive-strength = "x1"; |
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}; |
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}; |
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}; |
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