diff --git a/boards/boards_legacy/arm/mimx8mp_evk/Kconfig.board b/boards/boards_legacy/arm/mimx8mp_evk/Kconfig.board deleted file mode 100644 index 1595301fa29..00000000000 --- a/boards/boards_legacy/arm/mimx8mp_evk/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# MIMX8MP EVK board - -# Copyright (c) 2021, Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIMX8MP_EVK - bool "NXP i.MX8M Plus EVK" - depends on SOC_SERIES_IMX8ML_M7 - select SOC_PART_NUMBER_MIMX8ML8DVNLZ diff --git a/boards/boards_legacy/arm/mimx8mp_evk/board.cmake b/boards/boards_legacy/arm/mimx8mp_evk/board.cmake deleted file mode 100644 index d773ef92919..00000000000 --- a/boards/boards_legacy/arm/mimx8mp_evk/board.cmake +++ /dev/null @@ -1,11 +0,0 @@ -# -# Copyright (c) 2021, Laird Connectivity -# -# SPDX-License-Identifier: Apache-2.0 -# - -board_set_debugger_ifnset(jlink) -board_set_flasher_ifnset(jlink) - -board_runner_args(jlink "--device=MIMX8ML8_M7") -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) \ No newline at end of file diff --git a/boards/boards_legacy/arm/mimx8mp_evk/doc/img/I.MX8MPLUS-PLUS-EVK-TOP.jpg b/boards/boards_legacy/arm/mimx8mp_evk/doc/img/I.MX8MPLUS-PLUS-EVK-TOP.jpg deleted file mode 100644 index d3cc7cb00dd..00000000000 Binary files a/boards/boards_legacy/arm/mimx8mp_evk/doc/img/I.MX8MPLUS-PLUS-EVK-TOP.jpg and /dev/null differ diff --git a/boards/boards_legacy/arm/mimx8mp_evk/doc/index.rst b/boards/boards_legacy/arm/mimx8mp_evk/doc/index.rst deleted file mode 100644 index 9a9d0ff1599..00000000000 --- a/boards/boards_legacy/arm/mimx8mp_evk/doc/index.rst +++ /dev/null @@ -1,188 +0,0 @@ -.. _mimx8ml_evk: - -NXP MIMX8MP EVK -############### - -Overview -******** - -i.MX8M Plus EVK board is based on NXP i.MX8M Plus applications -processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M7 core. -Zephyr OS is ported to run on the Cortex®-M7 core. - -- Board features: - - - RAM: 6GB LPDDR4 - - Storage: - - - SanDisk 32GB eMMC5.1 - - Micron 32MB QSPI NOR - - microSD Socket - - Wireless: - - - WiFi: 2.4/5GHz IEEE 802.11b/g/n/ac - - Bluetooth: v4.2 - - USB: - - - USB 3.0 Type C for Power - - USB 3.0 Type A - - USB 3.0 Type C - - 2x 10/100/1000 Ethernet (1x w/ TSN) - - PCI-E M.2 - - Connectors: - - - 40-Pin Dual Row Header - - LEDs: - - - 1x Power status LED - - 1x UART LED - - Debug - - - JTAG connector - - MicroUSB for UART debug, two COM ports for A53 and one for M7 - -.. image:: img/I.MX8MPLUS-PLUS-EVK-TOP.jpg - :align: center - :alt: MIMX8MP EVK - -More information about the board can be found at the -`NXP website`_. - -Supported Features -================== - -The Zephyr mimx8mp_evk board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -:zephyr_file:`boards/arm/mimx8mp_evk/mimx8mp_evk_defconfig`. - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -MIMX8MP EVK board was tested with the following pinmux controller -configuration. - -+---------------+-----------------+---------------------------+ -| Board Name | SoC Name | Usage | -+===============+=================+===========================+ -| UART4 RXD | UART4_TXD | UART Console | -+---------------+-----------------+---------------------------+ -| UART4 TXD | UART4_RXD | UART Console | -+---------------+-----------------+---------------------------+ - -System Clock -============ - -The M7 Core is configured to run at a 800 MHz clock speed. - -Serial Port -=========== - -The i.MX8M Plus SoC has four UARTs. UART_4 is configured for the console and -the remaining are not used/tested. - -Programming and Debugging -************************* - -The MIMX8MP EVK board doesn't have QSPI flash for the M7, and it needs -to be started by the A53 core. The A53 core is responsible to load the M7 binary -application into the RAM, put the M7 in reset, set the M7 Program Counter and -Stack Pointer, and get the M7 out of reset. The A53 can perform these steps at -bootloader level or after the Linux system has booted. - -The M7 can use up to 3 different RAMs (currently, only two configurations are -supported: ITCM and DDR). These are the memory mapping for A53 and M7: - -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| Region | Cortex-A53 | Cortex-M7 (System Bus) | Cortex-M7 (Code Bus) | Size | -+============+=========================+========================+=======================+======================+ -| OCRAM | 0x00900000-0x0098FFFF | 0x20200000-0x2028FFFF | 0x00900000-0x0098FFFF | 576KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| DTCM | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| ITCM | 0x007E0000-0x007FFFFF | | 0x00000000-0x0001FFFF | 128KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| OCRAM_S | 0x00180000-0x00188FFF | 0x20180000-0x20188FFF | 0x00180000-0x00188FFF | 36KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| DDR | 0x80000000-0x803FFFFF | 0x80200000-0x803FFFFF | 0x80000000-0x801FFFFF | 2MB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ - -For more information about memory mapping see the -`i.MX 8M Plus Applications Processor Reference Manual`_ (section 2.1 to 2.3) - -At compilation time you have to choose which RAM will be used. This -configuration is done based on board name (mimx8mp_evk_itcm for ITCM and -mimx8mp_evk_ddr for DDR). - -Load and run Zephyr on M7 from A53 using u-boot by copying the compiled -``zephyr.bin`` to the first FAT partition of the SD card and plug the SD -card into the board. Power it up and stop the u-boot execution at prompt. - -Load the M7 binary onto the desired memory and start its execution using: - -ITCM -=== - -.. code-block:: console - - fatload mmc 0:1 0x48000000 zephyr.bin - cp.b 0x48000000 0x7e0000 20000 - bootaux 0x7e0000 - -DDR -=== - -.. code-block:: console - - fatload mmc 0:1 0x80000000 zephyr.bin - dcache flush - bootaux 0x80000000 - -Debugging -========= - -MIMX8MP EVK board can be debugged by connecting an external JLink -JTAG debugger to the J24 debug connector and to the PC. Then -the application can be debugged using the usual way. - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mimx8mp_evk_itcm - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - *** Booting Zephyr OS build v2.7.99-1310-g2801bf644a91 *** - Hello World! mimx8mp_evk - -References -========== - -.. _NXP website: - https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/evaluation-kit-for-the-i-mx-8m-plus-applications-processor:8MPLUSLPD4-EVK - -.. _i.MX 8M Plus Applications Processor Reference Manual: - https://www.nxp.com/webapp/Download?colCode=IMX8MPRM diff --git a/boards/boards_legacy/arm/mimx8mp_evk/mimx8mp_evk-pinctrl.dtsi b/boards/boards_legacy/arm/mimx8mp_evk/mimx8mp_evk-pinctrl.dtsi deleted file mode 100644 index a690f201ba1..00000000000 --- a/boards/boards_legacy/arm/mimx8mp_evk/mimx8mp_evk-pinctrl.dtsi +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (c) 2022, NXP - * SPDX-License-Identifier: Apache-2.0 - * - * Note: File generated by gen_board_pinctrl.py - * from MIMX8MP-EVK-REV-A.mex - */ - -#include - -&pinctrl { - uart4_default: uart4_default { - group0 { - pinmux = <&iomuxc_uart4_rxd_uart_rx_uart4_rx>, - <&iomuxc_uart4_txd_uart_tx_uart4_tx>; - bias-pull-up; - slew-rate = "slow"; - drive-strength = "x1"; - }; - }; - -}; diff --git a/boards/boards_legacy/arm/mimx8mp_evk/Kconfig.defconfig b/boards/nxp/imx8mp_evk/Kconfig.defconfig similarity index 57% rename from boards/boards_legacy/arm/mimx8mp_evk/Kconfig.defconfig rename to boards/nxp/imx8mp_evk/Kconfig.defconfig index 41d7a120fd1..3fdc7b3cd9c 100644 --- a/boards/boards_legacy/arm/mimx8mp_evk/Kconfig.defconfig +++ b/boards/nxp/imx8mp_evk/Kconfig.defconfig @@ -3,10 +3,7 @@ # Copyright (c) 2021, Laird Connectivity # SPDX-License-Identifier: Apache-2.0 -if BOARD_MIMX8MP_EVK - -config BOARD - default "mimx8mp_evk" +if BOARD_IMX8MP_EVK_MIMX8ML8_M7 || BOARD_IMX8MP_EVK_MIMX8ML8_M7_DDR if !XIP config FLASH_SIZE @@ -15,4 +12,4 @@ config FLASH_BASE_ADDRESS default 0 endif -endif # BOARD_MIMX8MP_EVK +endif # BOARD_IMX8MP_EVK_MIMX8ML8_M7 || BOARD_IMX8MP_EVK_MIMX8ML8_M7_DDR diff --git a/boards/nxp/imx8mp_evk/Kconfig.imx8mp_evk b/boards/nxp/imx8mp_evk/Kconfig.imx8mp_evk index 620d59828a3..fbda0ccc10d 100644 --- a/boards/nxp/imx8mp_evk/Kconfig.imx8mp_evk +++ b/boards/nxp/imx8mp_evk/Kconfig.imx8mp_evk @@ -4,4 +4,5 @@ config BOARD_IMX8MP_EVK select SOC_MIMX8ML8_A53 if BOARD_IMX8MP_EVK_MIMX8ML8_A53 || BOARD_IMX8MP_EVK_MIMX8ML8_A53_SMP select SOC_MIMX8MP_ADSP if BOARD_IMX8MP_EVK_MIMX8ML8_ADSP + select SOC_MIMX8MP_M7 if BOARD_IMX8MP_EVK_MIMX8ML8_M7 || BOARD_IMX8MP_EVK_MIMX8ML8_M7_DDR select SOC_PART_NUMBER_MIMX8ML8DVNLZ diff --git a/boards/nxp/imx8mp_evk/board.cmake b/boards/nxp/imx8mp_evk/board.cmake index ca181c922bd..55a52a15b19 100644 --- a/boards/nxp/imx8mp_evk/board.cmake +++ b/boards/nxp/imx8mp_evk/board.cmake @@ -10,3 +10,11 @@ if(CONFIG_SOC_MIMX8MP_ADSP) board_set_rimage_target(imx8m) endif() + +if(CONFIG_SOC_MIMX8MP_M7) + board_set_debugger_ifnset(jlink) + board_set_flasher_ifnset(jlink) + + board_runner_args(jlink "--device=MIMX8ML8_M7") + include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +endif() diff --git a/boards/nxp/imx8mp_evk/board.yml b/boards/nxp/imx8mp_evk/board.yml index 230fda76209..d810c27a596 100644 --- a/boards/nxp/imx8mp_evk/board.yml +++ b/boards/nxp/imx8mp_evk/board.yml @@ -6,3 +6,5 @@ board: variants: - name: smp cpucluster: a53 + - name: ddr + cpucluster: m7 diff --git a/boards/nxp/imx8mp_evk/doc/index.rst b/boards/nxp/imx8mp_evk/doc/index.rst index d8a7753a1eb..9952c7c90b5 100644 --- a/boards/nxp/imx8mp_evk/doc/index.rst +++ b/boards/nxp/imx8mp_evk/doc/index.rst @@ -1,7 +1,7 @@ .. _imx8mp_evk: -NXP i.MX8MP EVK (Cortex-A53) -################################# +NXP i.MX8MP EVK +############### Overview ******** @@ -58,6 +58,24 @@ features: | UART | on-chip | serial port | +-----------+------------+-------------------------------------+ +The Zephyr mimx8mp_evk_m7 board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ + Devices ======== System Clock @@ -65,14 +83,16 @@ System Clock This board configuration uses a system clock frequency of 8 MHz. +The M7 Core is configured to run at a 800 MHz clock speed. + Serial Port ----------- This board configuration uses a single serial communication channel with the CPU's UART4. -Programming and Debugging -************************* +Programming and Debugging (A53) +******************************* Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and plug the SD card into the board. Power it up and stop the u-boot execution at @@ -120,6 +140,85 @@ Use Jailhouse hypervisor, after root cell linux is up: #jailhouse cell load 1 zephyr.bin -a 0xc0000000 #jailhouse cell start 1 +Programming and Debugging (M7) +****************************** + +The MIMX8MP EVK board doesn't have QSPI flash for the M7, and it needs +to be started by the A53 core. The A53 core is responsible to load the M7 binary +application into the RAM, put the M7 in reset, set the M7 Program Counter and +Stack Pointer, and get the M7 out of reset. The A53 can perform these steps at +bootloader level or after the Linux system has booted. + +The M7 can use up to 3 different RAMs (currently, only two configurations are +supported: ITCM and DDR). These are the memory mapping for A53 and M7: + ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| Region | Cortex-A53 | Cortex-M7 (System Bus) | Cortex-M7 (Code Bus) | Size | ++============+=========================+========================+=======================+======================+ +| OCRAM | 0x00900000-0x0098FFFF | 0x20200000-0x2028FFFF | 0x00900000-0x0098FFFF | 576KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| DTCM | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| ITCM | 0x007E0000-0x007FFFFF | | 0x00000000-0x0001FFFF | 128KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| OCRAM_S | 0x00180000-0x00188FFF | 0x20180000-0x20188FFF | 0x00180000-0x00188FFF | 36KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| DDR | 0x80000000-0x803FFFFF | 0x80200000-0x803FFFFF | 0x80000000-0x801FFFFF | 2MB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ + +For more information about memory mapping see the +`i.MX 8M Applications Processor Reference Manual`_ (section 2.1 to 2.3) + +At compilation time you have to choose which RAM will be used. This +configuration is done based on board name (imx8mp_evk/mimx8ml8/m7 for ITCM and +imx8mp_evk/mimx8ml8/m7/ddr for DDR). + +Load and run Zephyr on M7 from A53 using u-boot by copying the compiled +``zephyr.bin`` to the first FAT partition of the SD card and plug the SD +card into the board. Power it up and stop the u-boot execution at prompt. + +Load the M7 binary onto the desired memory and start its execution using: + +ITCM +=== + +.. code-block:: console + + fatload mmc 0:1 0x48000000 zephyr.bin + cp.b 0x48000000 0x7e0000 20000 + bootaux 0x7e0000 + +DDR +=== + +.. code-block:: console + + fatload mmc 0:1 0x80000000 zephyr.bin + dcache flush + bootaux 0x80000000 + +Debugging +========= + +MIMX8MP EVK board can be debugged by connecting an external JLink +JTAG debugger to the J24 debug connector and to the PC. Then +the application can be debugged using the usual way. + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: imx8mp_evk/mimx8ml8/m7 + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v2.7.99-1310-g2801bf644a91 *** + Hello World! imx8mp_evk + References ========== diff --git a/boards/boards_legacy/arm/mimx8mp_evk/mimx8mp_evk_itcm.dts b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7.dts similarity index 93% rename from boards/boards_legacy/arm/mimx8mp_evk/mimx8mp_evk_itcm.dts rename to boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7.dts index 2d3f171339e..2b05cab20ce 100644 --- a/boards/boards_legacy/arm/mimx8mp_evk/mimx8mp_evk_itcm.dts +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7.dts @@ -7,7 +7,7 @@ /dts-v1/; #include -#include "mimx8mp_evk-pinctrl.dtsi" +#include "imx8mp_evk-pinctrl.dtsi" / { model = "NXP i.MX8M Plus EVK board"; diff --git a/boards/boards_legacy/arm/mimx8mp_evk/mimx8mp_evk_itcm.yaml b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7.yaml similarity index 80% rename from boards/boards_legacy/arm/mimx8mp_evk/mimx8mp_evk_itcm.yaml rename to boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7.yaml index 66c3c9b553d..6ab73e3386a 100644 --- a/boards/boards_legacy/arm/mimx8mp_evk/mimx8mp_evk_itcm.yaml +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7.yaml @@ -4,8 +4,8 @@ # SPDX-License-Identifier: Apache-2.0 # -identifier: mimx8mp_evk_itcm -name: NXP i.MX8M Plus EVK (ITCM) +identifier: imx8mp_evk/mimx8ml8/m7 +name: NXP i.MX8M Plus EVK type: mcu arch: arm ram: 128 diff --git a/boards/boards_legacy/arm/mimx8mp_evk/mimx8mp_evk_ddr.dts b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr.dts similarity index 93% rename from boards/boards_legacy/arm/mimx8mp_evk/mimx8mp_evk_ddr.dts rename to boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr.dts index 0179f811eb9..ba805ef7cbf 100644 --- a/boards/boards_legacy/arm/mimx8mp_evk/mimx8mp_evk_ddr.dts +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr.dts @@ -7,7 +7,7 @@ /dts-v1/; #include -#include "mimx8mp_evk-pinctrl.dtsi" +#include "imx8mp_evk-pinctrl.dtsi" / { model = "NXP i.MX8M Plus EVK board"; diff --git a/boards/boards_legacy/arm/mimx8mp_evk/mimx8mp_evk_ddr.yaml b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr.yaml similarity index 88% rename from boards/boards_legacy/arm/mimx8mp_evk/mimx8mp_evk_ddr.yaml rename to boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr.yaml index 7e4b407380b..e5ed32a1d38 100644 --- a/boards/boards_legacy/arm/mimx8mp_evk/mimx8mp_evk_ddr.yaml +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr.yaml @@ -4,7 +4,7 @@ # SPDX-License-Identifier: Apache-2.0 # -identifier: mimx8mp_evk_ddr +identifier: imx8mp_evk/mimx8ml8/m7/ddr name: NXP i.MX8M Plus EVK (DDR) type: mcu arch: arm diff --git a/boards/boards_legacy/arm/mimx8mp_evk/mimx8mp_evk_ddr_defconfig b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr_defconfig similarity index 75% rename from boards/boards_legacy/arm/mimx8mp_evk/mimx8mp_evk_ddr_defconfig rename to boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr_defconfig index 4a77ad558c2..17542cb4eec 100644 --- a/boards/boards_legacy/arm/mimx8mp_evk/mimx8mp_evk_ddr_defconfig +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr_defconfig @@ -4,9 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_SERIES_IMX8ML_M7=y -CONFIG_SOC_MIMX8ML8=y -CONFIG_BOARD_MIMX8MP_EVK=y CONFIG_CLOCK_CONTROL=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/boards_legacy/arm/mimx8mp_evk/mimx8mp_evk_itcm_defconfig b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_defconfig similarity index 75% rename from boards/boards_legacy/arm/mimx8mp_evk/mimx8mp_evk_itcm_defconfig rename to boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_defconfig index 8b2a3b77054..0f7d91f447e 100644 --- a/boards/boards_legacy/arm/mimx8mp_evk/mimx8mp_evk_itcm_defconfig +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_defconfig @@ -4,9 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_SERIES_IMX8ML_M7=y -CONFIG_SOC_MIMX8ML8=y -CONFIG_BOARD_MIMX8MP_EVK=y CONFIG_CLOCK_CONTROL=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y