Browse Source
Port EVK board for NXP imx93 to hwm V2. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>pull/69687/head
Jiafei Pan
1 year ago
committed by
Carles Cufi
14 changed files with 21 additions and 170 deletions
@ -1,7 +0,0 @@
@@ -1,7 +0,0 @@
|
||||
# Copyright 2022 NXP |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
config BOARD_MIMX93_EVK_A55 |
||||
bool "NXP i.MX93 EVK A55" |
||||
depends on SOC_SERIES_MIMX9_A55 |
||||
select SOC_PART_NUMBER_MIMX9352CVUXK |
||||
@ -1,9 +0,0 @@
@@ -1,9 +0,0 @@
|
||||
# Copyright 2022 NXP |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
if BOARD_MIMX93_EVK_A55 |
||||
|
||||
config BOARD |
||||
default "mimx93_evk_a55" |
||||
|
||||
endif # BOARD_MIMX8MP_EVK_A55 |
||||
@ -1,88 +0,0 @@
@@ -1,88 +0,0 @@
|
||||
/* |
||||
* Copyright 2023 NXP |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
|
||||
/dts-v1/; |
||||
|
||||
#include <nxp/nxp_mimx93_a55.dtsi> |
||||
#include "mimx93_evk-pinctrl.dtsi" |
||||
|
||||
/ { |
||||
model = "NXP i.MX93 A55"; |
||||
compatible = "fsl,mimx93"; |
||||
|
||||
chosen { |
||||
zephyr,console = &lpuart2; |
||||
zephyr,shell-uart = &lpuart2; |
||||
zephyr,sram = &sram0; |
||||
}; |
||||
|
||||
cpus { |
||||
cpu@0 { |
||||
status = "disabled"; |
||||
}; |
||||
}; |
||||
|
||||
/* Inmate memory, reserved through "mem=1248MB" boot argument, |
||||
* starts at 0xce000000. |
||||
*/ |
||||
sram0: memory@ce000000 { |
||||
reg = <0xce000000 DT_SIZE_M(1)>; |
||||
}; |
||||
|
||||
/* TODO: all of the nodes below are needed by SOF and should |
||||
* be removed once all drivers used by SOF have been moved |
||||
* to Zephyr. |
||||
* |
||||
* They are added in the DTS for the sake of not using hardcoded |
||||
* values in mmu_regions.c |
||||
*/ |
||||
mu2_a: memory@42430000 { |
||||
reg = <0x42430000 DT_SIZE_K(64)>; |
||||
}; |
||||
|
||||
sai3: memory@42660000 { |
||||
reg = <0x42660000 DT_SIZE_K(64)>; |
||||
}; |
||||
|
||||
edma2_ch0: memory@42010000 { |
||||
reg = <0x42010000 DT_SIZE_K(32)>; |
||||
}; |
||||
|
||||
edma2_ch1: memory@42018000 { |
||||
reg = <0x42018000 DT_SIZE_K(32)>; |
||||
}; |
||||
|
||||
outbox: memory@ce100000 { |
||||
reg = <0xce100000 DT_SIZE_K(4)>; |
||||
}; |
||||
|
||||
inbox: memory@ce101000 { |
||||
reg = <0xce101000 DT_SIZE_K(4)>; |
||||
}; |
||||
|
||||
stream: memory@ce102000 { |
||||
reg = <0xce102000 DT_SIZE_K(4)>; |
||||
}; |
||||
|
||||
/* TODO: this is extremely bad and it's needed here because of |
||||
* the fact that the DMA buffer shared by host and FW is situated |
||||
* in this region. For now, it's easier to create a mapping for the |
||||
* whole region but in the future a mapping should only be created |
||||
* for the physical address of the buffer sent to the FW through an |
||||
* IPC. |
||||
*/ |
||||
host_ram: memory@80000000 { |
||||
reg = <0x80000000 DT_SIZE_M(1024)>; |
||||
}; |
||||
}; |
||||
|
||||
&lpuart2 { |
||||
status = "okay"; |
||||
current-speed = <115200>; |
||||
/* clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>; */ |
||||
pinctrl-0 = <&uart2_default>; |
||||
pinctrl-names = "default"; |
||||
}; |
||||
@ -1,13 +0,0 @@
@@ -1,13 +0,0 @@
|
||||
identifier: mimx93_evk_a55_sof |
||||
name: NXP i.MX93 Plus EVK A55 for SOF module |
||||
type: mcu |
||||
arch: arm64 |
||||
toolchain: |
||||
- zephyr |
||||
- cross-compile |
||||
ram: 1024 |
||||
testing: |
||||
ignore_tags: |
||||
- net |
||||
- bluetooth |
||||
vendor: fsl |
||||
@ -1,44 +0,0 @@
@@ -1,44 +0,0 @@
|
||||
# |
||||
# Copyright 2023 NXP |
||||
# |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
# ARM Options |
||||
CONFIG_AARCH64_IMAGE_HEADER=y |
||||
CONFIG_ARMV8_A_NS=y |
||||
|
||||
# The number of bits used for PAs and VAs |
||||
# from Zephyr needs to match the number of |
||||
# bits used for said address used by Jailhouse. |
||||
CONFIG_ARM64_VA_BITS_40=y |
||||
CONFIG_ARM64_PA_BITS_40=y |
||||
|
||||
# Cache Options |
||||
CONFIG_CACHE_MANAGEMENT=y |
||||
CONFIG_ICACHE_LINE_SIZE_DETECT=y |
||||
# SOF doesn't currently support the usage of |
||||
# run-time data cache line size detection. |
||||
# Because of this, CONFIG_DCACHE_LINE_SIZE_DETECT |
||||
# (which defaults to n) can't be set to 'y'. |
||||
# The size of data cache line will have to be |
||||
# set manually to 64 (value taken from A55 TRM). |
||||
CONFIG_DCACHE_LINE_SIZE=64 |
||||
|
||||
# Platform Configuration |
||||
CONFIG_SOC_SERIES_MIMX9_A55=y |
||||
CONFIG_SOC_MIMX93_A55=y |
||||
CONFIG_BOARD_MIMX93_EVK_A55=y |
||||
|
||||
# Serial Drivers |
||||
CONFIG_SERIAL=y |
||||
CONFIG_UART_INTERRUPT_DRIVEN=y |
||||
|
||||
# Enable Console |
||||
CONFIG_CONSOLE=y |
||||
CONFIG_UART_CONSOLE=y |
||||
|
||||
CONFIG_CLOCK_CONTROL=y |
||||
CONFIG_PINCTRL=y |
||||
|
||||
# Enable dynamic interrupts |
||||
CONFIG_DYNAMIC_INTERRUPTS=y |
||||
@ -0,0 +1,6 @@
@@ -0,0 +1,6 @@
|
||||
# Copyright 2022,2024 NXP |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
config BOARD_IMX93_EVK_MIMX9352_A55 |
||||
select SOC_MIMX9352_A55 |
||||
select SOC_PART_NUMBER_MIMX9352CVUXK |
||||
@ -0,0 +1,5 @@
@@ -0,0 +1,5 @@
|
||||
board: |
||||
name: imx93_evk |
||||
vendor: nxp |
||||
socs: |
||||
- name: mimx9352 |
||||
Loading…
Reference in new issue