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Port EVK board for NXP imx93 to hwm V2. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>pull/69687/head
14 changed files with 21 additions and 170 deletions
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# Copyright 2022 NXP |
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# SPDX-License-Identifier: Apache-2.0 |
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config BOARD_MIMX93_EVK_A55 |
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bool "NXP i.MX93 EVK A55" |
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depends on SOC_SERIES_MIMX9_A55 |
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select SOC_PART_NUMBER_MIMX9352CVUXK |
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# Copyright 2022 NXP |
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# SPDX-License-Identifier: Apache-2.0 |
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if BOARD_MIMX93_EVK_A55 |
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config BOARD |
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default "mimx93_evk_a55" |
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endif # BOARD_MIMX8MP_EVK_A55 |
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/* |
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* Copyright 2023 NXP |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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/dts-v1/; |
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#include <nxp/nxp_mimx93_a55.dtsi> |
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#include "mimx93_evk-pinctrl.dtsi" |
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/ { |
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model = "NXP i.MX93 A55"; |
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compatible = "fsl,mimx93"; |
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chosen { |
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zephyr,console = &lpuart2; |
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zephyr,shell-uart = &lpuart2; |
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zephyr,sram = &sram0; |
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}; |
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cpus { |
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cpu@0 { |
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status = "disabled"; |
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}; |
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}; |
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/* Inmate memory, reserved through "mem=1248MB" boot argument, |
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* starts at 0xce000000. |
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*/ |
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sram0: memory@ce000000 { |
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reg = <0xce000000 DT_SIZE_M(1)>; |
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}; |
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/* TODO: all of the nodes below are needed by SOF and should |
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* be removed once all drivers used by SOF have been moved |
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* to Zephyr. |
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* |
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* They are added in the DTS for the sake of not using hardcoded |
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* values in mmu_regions.c |
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*/ |
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mu2_a: memory@42430000 { |
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reg = <0x42430000 DT_SIZE_K(64)>; |
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}; |
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sai3: memory@42660000 { |
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reg = <0x42660000 DT_SIZE_K(64)>; |
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}; |
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edma2_ch0: memory@42010000 { |
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reg = <0x42010000 DT_SIZE_K(32)>; |
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}; |
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edma2_ch1: memory@42018000 { |
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reg = <0x42018000 DT_SIZE_K(32)>; |
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}; |
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outbox: memory@ce100000 { |
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reg = <0xce100000 DT_SIZE_K(4)>; |
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}; |
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inbox: memory@ce101000 { |
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reg = <0xce101000 DT_SIZE_K(4)>; |
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}; |
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stream: memory@ce102000 { |
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reg = <0xce102000 DT_SIZE_K(4)>; |
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}; |
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/* TODO: this is extremely bad and it's needed here because of |
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* the fact that the DMA buffer shared by host and FW is situated |
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* in this region. For now, it's easier to create a mapping for the |
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* whole region but in the future a mapping should only be created |
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* for the physical address of the buffer sent to the FW through an |
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* IPC. |
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*/ |
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host_ram: memory@80000000 { |
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reg = <0x80000000 DT_SIZE_M(1024)>; |
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}; |
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}; |
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&lpuart2 { |
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status = "okay"; |
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current-speed = <115200>; |
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/* clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>; */ |
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pinctrl-0 = <&uart2_default>; |
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pinctrl-names = "default"; |
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}; |
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identifier: mimx93_evk_a55_sof |
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name: NXP i.MX93 Plus EVK A55 for SOF module |
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type: mcu |
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arch: arm64 |
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toolchain: |
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- zephyr |
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- cross-compile |
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ram: 1024 |
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testing: |
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ignore_tags: |
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- net |
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- bluetooth |
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vendor: fsl |
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# |
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# Copyright 2023 NXP |
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# |
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# SPDX-License-Identifier: Apache-2.0 |
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# ARM Options |
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CONFIG_AARCH64_IMAGE_HEADER=y |
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CONFIG_ARMV8_A_NS=y |
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# The number of bits used for PAs and VAs |
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# from Zephyr needs to match the number of |
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# bits used for said address used by Jailhouse. |
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CONFIG_ARM64_VA_BITS_40=y |
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CONFIG_ARM64_PA_BITS_40=y |
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# Cache Options |
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CONFIG_CACHE_MANAGEMENT=y |
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CONFIG_ICACHE_LINE_SIZE_DETECT=y |
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# SOF doesn't currently support the usage of |
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# run-time data cache line size detection. |
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# Because of this, CONFIG_DCACHE_LINE_SIZE_DETECT |
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# (which defaults to n) can't be set to 'y'. |
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# The size of data cache line will have to be |
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# set manually to 64 (value taken from A55 TRM). |
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CONFIG_DCACHE_LINE_SIZE=64 |
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# Platform Configuration |
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CONFIG_SOC_SERIES_MIMX9_A55=y |
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CONFIG_SOC_MIMX93_A55=y |
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CONFIG_BOARD_MIMX93_EVK_A55=y |
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# Serial Drivers |
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CONFIG_SERIAL=y |
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CONFIG_UART_INTERRUPT_DRIVEN=y |
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# Enable Console |
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CONFIG_CONSOLE=y |
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CONFIG_UART_CONSOLE=y |
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CONFIG_CLOCK_CONTROL=y |
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CONFIG_PINCTRL=y |
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# Enable dynamic interrupts |
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CONFIG_DYNAMIC_INTERRUPTS=y |
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@ -0,0 +1,6 @@ |
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# Copyright 2022,2024 NXP |
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# SPDX-License-Identifier: Apache-2.0 |
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config BOARD_IMX93_EVK_MIMX9352_A55 |
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select SOC_MIMX9352_A55 |
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select SOC_PART_NUMBER_MIMX9352CVUXK |
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board: |
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name: imx93_evk |
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vendor: nxp |
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socs: |
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- name: mimx9352 |
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