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126 lines
3.3 KiB
126 lines
3.3 KiB
/* |
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* Copyright (c) 2025 Aesc Silicon |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#define DT_DRV_COMPAT aesc_uart |
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#include <errno.h> |
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#include <ip_identification.h> |
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#include <soc.h> |
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#include <zephyr/device.h> |
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#include <zephyr/devicetree.h> |
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#include <zephyr/drivers/uart.h> |
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#include <zephyr/init.h> |
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#include <zephyr/kernel.h> |
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#include <zephyr/logging/log.h> |
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LOG_MODULE_REGISTER(aesc_uart, CONFIG_UART_LOG_LEVEL); |
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struct uart_aesc_data { |
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DEVICE_MMIO_NAMED_RAM(regs); |
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}; |
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struct uart_aesc_config { |
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DEVICE_MMIO_NAMED_ROM(regs); |
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uint64_t sys_clk_freq; |
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uint32_t current_speed; |
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}; |
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struct uart_aesc_regs { |
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uint32_t data_width; |
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uint32_t sampling_sizes; |
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uint32_t fifo_depths; |
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uint32_t permissions; |
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uint32_t read_write; |
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uint32_t fifo_status; |
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uint32_t clock_div; |
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uint32_t frame_cfg; |
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uint32_t ip; |
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uint32_t ie; |
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}; |
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#define DEV_CFG(dev) ((struct uart_aesc_config *)(dev)->config) |
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#define DEV_DATA(dev) ((struct uart_aesc_data *)(dev)->data) |
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#define DEV_UART(dev) \ |
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((struct uart_aesc_regs *)DEVICE_MMIO_NAMED_GET(dev, regs)) |
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#define AESC_UART_IRQ_TX_EN BIT(0) |
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#define AESC_UART_IRQ_RX_EN BIT(1) |
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#define AESC_UART_FIFO_TX_COUNT_MASK GENMASK(23, 16) |
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#define AESC_UART_READ_FIFO_VALID_BIT BIT(16) |
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static void uart_aesc_poll_out(const struct device *dev, unsigned char c) |
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{ |
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struct uart_aesc_regs *uart = DEV_UART(dev); |
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while ((uart->fifo_status & AESC_UART_FIFO_TX_COUNT_MASK) == 0) { |
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/* Wait until transmit fifo is empty */ |
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} |
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uart->read_write = c; |
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} |
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static int uart_aesc_poll_in(const struct device *dev, unsigned char *c) |
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{ |
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const struct uart_aesc_regs *uart = DEV_UART(dev); |
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int val; |
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val = uart->read_write; |
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if (val & AESC_UART_READ_FIFO_VALID_BIT) { |
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*c = val & 0xFF; |
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return 0; |
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} |
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return -1; |
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} |
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static int uart_aesc_init(const struct device *dev) |
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{ |
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const struct uart_aesc_config *cfg = DEV_CFG(dev); |
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volatile uintptr_t *base_addr = (volatile uintptr_t *)DEV_UART(dev); |
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volatile struct uart_aesc_regs *uart; |
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DEVICE_MMIO_NAMED_MAP(dev, regs, K_MEM_CACHE_NONE); |
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LOG_DBG("IP core version: %i.%i.%i.", |
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ip_id_get_major_version(base_addr), |
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ip_id_get_minor_version(base_addr), |
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ip_id_get_patchlevel(base_addr) |
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); |
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DEVICE_MMIO_NAMED_GET(dev, regs) = ip_id_relocate_driver(base_addr); |
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LOG_DBG("Relocate driver to address 0x%lx.", DEVICE_MMIO_NAMED_GET(dev, regs)); |
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uart = DEV_UART(dev); |
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uart->clock_div = cfg->sys_clk_freq / cfg->current_speed / 8; |
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uart->frame_cfg = 7; |
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return 0; |
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} |
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static DEVICE_API(uart, uart_aesc_driver_api) = { |
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.poll_in = uart_aesc_poll_in, |
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.poll_out = uart_aesc_poll_out, |
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.err_check = NULL, |
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}; |
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#define AESC_UART_INIT(no) \ |
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static struct uart_aesc_data uart_aesc_dev_data_##no; \ |
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static struct uart_aesc_config uart_aesc_dev_cfg_##no = { \ |
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DEVICE_MMIO_NAMED_ROM_INIT(regs, \ |
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DT_INST(no, aesc_uart)), \ |
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.sys_clk_freq = \ |
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DT_PROP(DT_INST(no, aesc_uart), clock_frequency), \ |
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.current_speed = \ |
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DT_PROP(DT_INST(no, aesc_uart), current_speed), \ |
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}; \ |
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DEVICE_DT_INST_DEFINE(no, \ |
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uart_aesc_init, \ |
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NULL, \ |
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&uart_aesc_dev_data_##no, \ |
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&uart_aesc_dev_cfg_##no, \ |
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PRE_KERNEL_1, \ |
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \ |
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(void *)&uart_aesc_driver_api); |
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DT_INST_FOREACH_STATUS_OKAY(AESC_UART_INIT)
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