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138 lines
3.0 KiB
138 lines
3.0 KiB
/* |
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* Copyright (c) 2018 - 2021 Antmicro <www.antmicro.com> |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#define DT_DRV_COMPAT litex_eth0 |
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#include <kernel.h> |
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#include <arch/cpu.h> |
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#include <init.h> |
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#include <irq.h> |
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#include <device.h> |
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#include <zephyr.h> |
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#include <zephyr/types.h> |
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#define IRQ_MASK DT_REG_ADDR_BY_NAME(DT_INST(0, vexriscv_intc0), irq_mask) |
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#define IRQ_PENDING DT_REG_ADDR_BY_NAME(DT_INST(0, vexriscv_intc0), irq_pending) |
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#define TIMER0_IRQ DT_IRQN(DT_INST(0, litex_timer0)) |
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#define UART0_IRQ DT_IRQN(DT_INST(0, litex_uart0)) |
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#define ETH0_IRQ DT_IRQN(DT_INST(0, litex_eth0)) |
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#define I2S_RX_IRQ DT_IRQN(DT_NODELABEL(i2s_rx)) |
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#define I2S_TX_IRQ DT_IRQN(DT_NODELABEL(i2s_tx)) |
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#define GPIO_IRQ DT_IRQN(DT_NODELABEL(gpio_in)) |
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static inline void vexriscv_litex_irq_setmask(uint32_t mask) |
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{ |
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__asm__ volatile ("csrw %0, %1" :: "i"(IRQ_MASK), "r"(mask)); |
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} |
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static inline uint32_t vexriscv_litex_irq_getmask(void) |
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{ |
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uint32_t mask; |
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__asm__ volatile ("csrr %0, %1" : "=r"(mask) : "i"(IRQ_MASK)); |
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return mask; |
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} |
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static inline uint32_t vexriscv_litex_irq_pending(void) |
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{ |
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uint32_t pending; |
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__asm__ volatile ("csrr %0, %1" : "=r"(pending) : "i"(IRQ_PENDING)); |
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return pending; |
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} |
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static inline void vexriscv_litex_irq_setie(uint32_t ie) |
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{ |
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if (ie) { |
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__asm__ volatile ("csrrs x0, mstatus, %0" |
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:: "r"(MSTATUS_IEN)); |
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} else { |
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__asm__ volatile ("csrrc x0, mstatus, %0" |
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:: "r"(MSTATUS_IEN)); |
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} |
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} |
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static void vexriscv_litex_irq_handler(const void *device) |
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{ |
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struct _isr_table_entry *ite; |
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uint32_t pending, mask, irqs; |
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pending = vexriscv_litex_irq_pending(); |
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mask = vexriscv_litex_irq_getmask(); |
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irqs = pending & mask; |
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#ifdef CONFIG_LITEX_TIMER |
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if (irqs & (1 << TIMER0_IRQ)) { |
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ite = &_sw_isr_table[TIMER0_IRQ]; |
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ite->isr(ite->arg); |
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} |
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#endif |
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN |
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if (irqs & (1 << UART0_IRQ)) { |
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ite = &_sw_isr_table[UART0_IRQ]; |
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ite->isr(ite->arg); |
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} |
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#endif |
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#ifdef CONFIG_ETH_LITEETH |
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if (irqs & (1 << ETH0_IRQ)) { |
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ite = &_sw_isr_table[ETH0_IRQ]; |
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ite->isr(ite->arg); |
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} |
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#endif |
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#ifdef CONFIG_I2S |
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if (irqs & (1 << I2S_RX_IRQ)) { |
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ite = &_sw_isr_table[I2S_RX_IRQ]; |
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ite->isr(ite->arg); |
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} |
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if (irqs & (1 << I2S_TX_IRQ)) { |
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ite = &_sw_isr_table[I2S_TX_IRQ]; |
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ite->isr(ite->arg); |
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} |
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#endif |
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if (irqs & (1 << GPIO_IRQ)) { |
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ite = &_sw_isr_table[GPIO_IRQ]; |
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ite->isr(ite->arg); |
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} |
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} |
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void arch_irq_enable(unsigned int irq) |
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{ |
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vexriscv_litex_irq_setmask(vexriscv_litex_irq_getmask() | (1 << irq)); |
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} |
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void arch_irq_disable(unsigned int irq) |
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{ |
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vexriscv_litex_irq_setmask(vexriscv_litex_irq_getmask() & ~(1 << irq)); |
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} |
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int arch_irq_is_enabled(unsigned int irq) |
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{ |
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return vexriscv_litex_irq_getmask() & (1 << irq); |
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} |
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static int vexriscv_litex_irq_init(const struct device *dev) |
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{ |
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ARG_UNUSED(dev); |
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__asm__ volatile ("csrrs x0, mie, %0" |
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:: "r"((1 << RISCV_MACHINE_TIMER_IRQ) |
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| (1 << RISCV_MACHINE_EXT_IRQ))); |
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vexriscv_litex_irq_setie(1); |
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IRQ_CONNECT(RISCV_MACHINE_EXT_IRQ, 0, vexriscv_litex_irq_handler, |
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NULL, 0); |
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return 0; |
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} |
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SYS_INIT(vexriscv_litex_irq_init, PRE_KERNEL_2, |
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CONFIG_INTC_INIT_PRIORITY);
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