Currently, the Zephyr dt requires address to the direction register
instead of the base GPIO address. usually means base address + 0x10 when
compared with Linux.
To make things more consistent between linux and zephyr, handle the
direction offset in the driver itself. This also lays the foundation for
supporting more than 32 GPIOs per port in the future by introducing
offsets for all the banks.
Signed-off-by: Ayush Singh <ayush@beagleboard.org>
Currently to set/clear the pins, we do a logical OR of the value with the
existing values in set/clear registers. However, reading these registers
always returns the value in out_data register. This is undesirable as it
can cause unnecessary complications. Consider the following scenario:
We need to set PIN 0:
set_data |= BIT(0)
We need to clear PIN 1:
clr_data |= BIT(1)
The latter would also clear the 0th bit due to the aforementioned
behaviour.
This patch fixes this by writing the mask directly without ORing.
Signed-off-by: Amneesh Singh <a-singh7@ti.com>
Ignore error if default pinctrl missing. Some devices allow specifying
pinctrl in them, which is better to do , specially for static (on-board)
devices to keep overlays simpler.
Signed-off-by: Ayush Singh <ayush@beagleboard.org>
Move the direction reset to config init function. This ensures that regs
is read after the DEVICE_MMIO_NAMED_MAP is called, which is where the
init for RAM MMIO takes place
Tested on PocketBeagle 2 A53s.
Signed-off-by: Ayush Singh <ayush@beagleboard.org>
This commit adds a padding of 0x10 bytes at the beginning of the
`gpio_davinci_regs` structure to correctly align the register
definitions with the actual register layout.
Previously, the DTS had to manually offset the base address by
0x10, introducing a special case in Zephyr's Davinci GPIO driver.
This change eliminates the need for that workaround
Adding the paddingi also help to maintain a similarly with also
to the linux counterpart.
Signed-off-by: Dhruv Menon <dhruvmenon1104@gmail.com>
Zephyr GPIO drivers require the pin mask `struct gpio_driver_data` to be
the first element of the driver config. Reordering fixes failures in ASSERT
statements of the GPIO driver due to the base address being interpreted as
supported pin mask.
Signed-off-by: Mika Braunschweig <mika.braunschweig@siemens.com>
Remove address-of operator ('&') when assigning `gpio_xxx_init`
function pointer in `DEVICE_DT_INST_DEFINE` macro.
This change aims to maintain consistency among the drivers in
`drivers/gpio`, ensuring that all function pointer assignments
follow the same pattern.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Add pinctrl to the Davinci GPIO driver to allow muxing pins dirctly
in this driver.
Also aligned the macro backslashes as line continuation character at
the end of each line with each at the same position and removed the
GPIO_DAVINCI_DEVICE_INIT macro which seems to be not used.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Davinci gpio controller support to add various soc gpio
support (J721E, AM654).
TRM for J721e https://www.ti.com/lit/zip/spruil1
File: spruil1c.pdf
GPIO: section 12.1.2
BeagleBone AI_64 https://beagleboard.org/ai-64
Signed-off-by: Prashanth S <slpp95prashanth@yahoo.com>
Ayush Singh
Amneesh Singh
Dhruv Menon
Mika Braunschweig
Pieter De Gendt
Pisit Sawangvonganan
Daniel Schultz
Prashanth S