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collab-hwm
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${ noResults }
9 Commits (1ff7d1c6388a6390f0288628f951cefa6e5d9ff1)
Author | SHA1 | Message | Date |
---|---|---|---|
|
12b2ee54e3 |
drivers: timer: s/device.h/init.h
Timer "drivers" do not use the device model infrastructure, they are singletons with a SYS_INIT call. This means they do not have to include device.h but init.h. Things worked because device.h includes init.h. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com> |
2 years ago |
|
a5fd0d184a |
init: remove the need for a dummy device pointer in SYS_INIT functions
The init infrastructure, found in `init.h`, is currently used by: - `SYS_INIT`: to call functions before `main` - `DEVICE_*`: to initialize devices They are all sorted according to an initialization level + a priority. `SYS_INIT` calls are really orthogonal to devices, however, the required function signature requires a `const struct device *dev` as a first argument. The only reason for that is because the same init machinery is used by devices, so we have something like: ```c struct init_entry { int (*init)(const struct device *dev); /* only set by DEVICE_*, otherwise NULL */ const struct device *dev; } ``` As a result, we end up with such weird/ugly pattern: ```c static int my_init(const struct device *dev) { /* always NULL! add ARG_UNUSED to avoid compiler warning */ ARG_UNUSED(dev); ... } ``` This is really a result of poor internals isolation. This patch proposes a to make init entries more flexible so that they can accept sytem initialization calls like this: ```c static int my_init(void) { ... } ``` This is achieved using a union: ```c union init_function { /* for SYS_INIT, used when init_entry.dev == NULL */ int (*sys)(void); /* for DEVICE*, used when init_entry.dev != NULL */ int (*dev)(const struct device *dev); }; struct init_entry { /* stores init function (either for SYS_INIT or DEVICE*) union init_function init_fn; /* stores device pointer for DEVICE*, NULL for SYS_INIT. Allows * to know which union entry to call. */ const struct device *dev; } ``` This solution **does not increase ROM usage**, and allows to offer clean public APIs for both SYS_INIT and DEVICE*. Note that however, init machinery keeps a coupling with devices. **NOTE**: This is a breaking change! All `SYS_INIT` functions will need to be converted to the new signature. See the script offered in the following commit. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no> init: convert SYS_INIT functions to the new signature Conversion scripted using scripts/utils/migrate_sys_init.py. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no> manifest: update projects for SYS_INIT changes Update modules with updated SYS_INIT calls: - hal_ti - lvgl - sof - TraceRecorderSource Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no> tests: devicetree: devices: adjust test Adjust test according to the recently introduced SYS_INIT infrastructure. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no> tests: kernel: threads: adjust SYS_INIT call Adjust to the new signature: int (*init_fn)(void); Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no> |
2 years ago |
|
f3a35c58d8 |
drivers: timer: mcux_gpt_timer: rewrite timer to use free run mode
GPT timer driver previously used "restart mode", where the timer would count to a given value, then rollover. In this mode, "Any write access to the Compare register of Channel 1 will reset the GPT counter". Since a write to the compare register takes affect after 1 cycle of the module's bus clock, and the bus clock is not synchonized with the GPT module's low frequency counter clock, writing to the compare register will induce a counter reset, and can cause the GPT to lose time synchronization. This can induce time drift over time. To fix this, rework the GPT driver to use "free run" mode. Note that free run mode is not used directly, rather the GPT is configured to reset on a tick boundary at boot, and then the second compare register is used to set capture points. This way, the GPT interrupt will always fire at a tick boundary, and no calculations are needed to handle the counter rollover. Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com> |
2 years ago |
|
acc8cb4bc8 |
include: add missing irq.h include
Some modules use the IRQ API without including the necessary headers. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no> |
3 years ago |
|
fb60aab245 |
drivers: migrate includes to <zephyr/...>
In order to bring consistency in-tree, migrate all drivers to the new prefix <zephyr/...>. Note that the conversion has been scripted, refer to #45388 for more details. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no> |
3 years ago |
|
694e6493af |
timers: mcux_gpt_timer: Change MCUX GPT timer to use indirect ISR
Indirect ISR automatically calls power management functions, which GPT timer direct ISR was not calling. Calling these functions means that the kernel will recognize that it is exiting low power mode when the GPT timer interrupt fires that wakes the SOC up, and will call pm_power_state_exit_post_ops, which can in turn raise the clock frequencies and voltage of the SOC as early as possible. Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com> |
3 years ago |
|
0694e47f97 |
drivers: mcux_gpt_timer: Fix rounding error on tick boundary
GPT timer driver was announcing progress to the kernel too soon when an announcement was requested via sys_clock_set_timeout() on a tick boundary. Fix rounding to add a tick worth of cycles. Fixes #42665 Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com> |
3 years ago |
|
59f9dfae58 |
drivers: timer: mcux_gpt: Enable GPT timer to run in doze mode
GPT timer must continue running in low power modes, as it is the system wakeup source. Set configuration to ensure peripheral will not stop running in low power modes. Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com> |
4 years ago |
|
fa56e9ee2b |
drivers: mcux_gpt_timer: Added GPT timer for HW clock
Added a driver to enable the GPT timer on RT1xxx parts to be used instead of systick as a clock source. The timer is set to run in reset mode, and uses the low frequency 32kHz oscillator for power savings Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com> |
4 years ago |