Utilize a code spell-checking tool to scan for and correct spelling errors
in `Kconfig` files within the `drivers` directory.
Additionally, incorporates a fix recommended by the reviewer.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
1. The edma version 5 share one driver with edma 4.
2. Edma5 tcd structure some difference, Use tcd type to distinguish,
and Edma5 uses 64 bytes for alignment instead of 32.
3. Some platforms have some address offsets for certain memory
when processing from a DMA perspective, such as imx95 cm7 TCM,
so add offset processing.
Signed-off-by: Yongxu Wang <yongxu.wang@nxp.com>
XCACHE has been designed for RT700, tcd pool need to be put in
noncache region, update driver to support
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
we iterate over all the channels, and if more than one channel is
active at a time. interrupt on any one of active channel was
triggering callback for other active channel, because flags value
is 1 (enabled). this is commit handle this behaviour and only
trigger callback if bits other than status is set
Signed-off-by: Anuj Pathak <anuj@croxel.com>
The SDK FSL DMA driver converts descriptor addresses to DMA's address
space when linking descriptors. The Zephyr dma_mcux_lpc driver is
missing the inverse conversion when dereferencing the linked next
descriptor pointer.
This isn't a problem when this driver is used on the M33 core
of the MIMXRT595S because the M33 can access the address space
of the DMA (0x20000000+). But when the Fusion F1 DSP core uses
this driver, the DSP cannot access the DMA's address space
so the inverse conversion is needed.
Signed-off-by: Yicheng Li <yichengli@google.com>
The driver treats the `source_data_size` and `dest_data_size` as a
width in bits and converts 8 bits to 1, 16 bits to 2, and 32 bits to 3.
This should be a width in bytes with 1 byte mapping to 0, 2 bytes to
1, and 4 bytes to 3.
Note that this preserves the current behaviour of silently accepting
invalid transfer bit widths.
Signed-off-by: Michael Hope <michaelh@juju.nz>
For MAX32657, 'MXC_DMA_EnableInt' function requires DMA instance
and this causes build error. To fix this, created wrapper version
of this function and update driver with it.
Signed-off-by: Furkan Akkiz <hasanfurkan.akkiz@analog.com>
The typical way of calling INPUTMUX_AttachSignal() is to
bracket it around INPUTMUX_Init() and INPUTMUX_Deinit()
calls because we can reduce power consumption by not
keeping the interface powered when not changing INPUTMUX.
This driver was violating that convention, which caused
it to not coexist well with other code that followed the
usage convention because the INPUTMUX might be initialized
or not depending on execution order with the other modules.
Signed-off-by: Mike J. Chen <mjchen@google.com>
DMA channel stats like pending_length or free is not protected
and can be modified in parallel by a consumer and a producer.
This can result in non-atomic updates which in turn will result
in using stale data.
Fix this by making regions of code accessing dma stats atomic.
Fixes: e94c86f395 ("drivers: dma: Add initial support for NXP SDMA")
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Each time we configure an SDMA channel we also compute the total
allocated DMA buffer length but we assume is initialized with zero.
This is true each time a channel is requested. But if there are
multiple calls to configure without releasing the channel the buffer
length is not correctly computed.
So, we need to initialize it with zero each time we reconfigure the dma
channel.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Add the PM handler. Reinitialize the DMA block in the
TURN_ON action, this is needed for some SoC's after the system
exits certain power modes.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Add missing curly braces in if/while/for statements.
This is a style guideline we have that was not enforced in CI. All
issues fixed here were detected by sonarqube SCA.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Commit fa4a9db7a3 ("dma: intel_adsp_hda: Fix invalid init sequence and
register use") moved intel_adsp_hda_channels_init() out from resume
path. This causes a regression to CONFIG_DMA_INTEL_ADSP_HDA_TIMING_L1_EXIT
as without irq_config() call the interrupt configuration may be partial.
Address this by calling irq_config() unconditionally on resume path.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Current DMA driver reload function only works for 8-bit
data. This is due to incorrect interpretation of size
argument. Added changes to support other xfer sizes.
Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
Remove address-of operator ('&') when assigning `dma_xxx_init`
function pointer in `DEVICE_DT_INST_DEFINE` macro.
This change aims to maintain consistency among the drivers in
`drivers/dma`, ensuring that all function pointer assignments
follow the same pattern.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
printf is failing in hello_world sample due to current
uart driver init level. This reverts back to PRE_KERNEL_1.
As uart depends on GDMA, set it also to same level.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Addressed an issue where alignment of dma desc varaible
of dma0 is corrected to 1024 instead of 512.
Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
Addressed an issue where regular/non-scatter-gather DMA
transfers were not explicitly using the primary DMA descriptor
structure. This ensures a smooth regular DMA transfer after
any scatter gather transfer.
Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
Introduced a new variable in the `dma_siwx91x_channel_info`
structure to provide a clean way to differentiate transfer
directions. This enhancement is utilized to trigger software
requests specifically for memory-to-memory transfers
Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
Some instances of DMA (dma0) can use the normal sram to store their
descriptors. In this case, it makes sense to allow the linker to
allocate the memory rather than tweaking the memory layout.
So, if the attribute silabs,sram-region is not defined, use a statically
allocated buffer.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
DMA can be initialized with the other devices. The user only need to the
ensure CONFIG_DMA_INIT_PRIORITY is less than the DMA consumers.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Silabs siwx91x hardware use specific memory areas to store descriptors
for DMA requests. These areas are tightly coupled between the CPU and
the hardware. This helps in reducing the wait cycles.
Until now these addresses was also hard coded in the DT and in the
linker script. This patch leverage the zephyr,memory-region driver to
centralize the information in the DT.
Then, with this new implementation, the memory mapping is easier to
understand for the reader.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
New HAL update changed the prototype of the check DMA flag functions.
C0 use a const parameter for these functions.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
This removes big structures allocated on stack.
It also moves linked list node to dedicated buffer.
Signed-off-by: Adam Berlinger <adam.berlinger@st.com>
Remove InitStructs of LL driver, since they take a lot of space on stack.
This can cause stack overflow in some scenarios.
Signed-off-by: Adam Berlinger <adam.berlinger@st.com>
DMA channel capacity wasn't properly initialized and the computation
relies on it being zeroed.
This only works fine only when requesting channel the first time
causing problems when we have multiple cycles of channel
request/release.
Fix this by properly initializing the capacity when requesting the
channel.
Fixes 43a48d4630 ("drivers: dma: sdma: Update buffer descriptor")
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
This reverts commit c2f02533a6.
DMA_INTEL_ADSP_HDA_TIMING_L1_EXIT should be enabled for all ACE platforms.
Any new platform in the ACE series will likely need it as well.
Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Replace occurrences of "RaspberryPi" with "Raspberry Pi" in
documentation, comment blocks etc. Correct the name of "PicoW" to
"Pico W", matching Raspberry Pi's documentation at
https://www.raspberrypi.com/documentation/microcontrollers/pico-series.html .
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
Implement support for scatter-gather DMA transfers in the siwx917 driver.
This enhancement allows the driver to handle multiple non-contiguous memory
buffers in a single DMA transaction
Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
Updated the driver to ensure that each DMA channel can properly
assign and handle individual callbacks.
Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
This new API allows the assignment of desired DMA channels for
peripheral transfers, enhancing flexibility and control over DMA
operations.
Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
Refactored the driver code to ensure compatibility with the
dma_context API, improving maintainability and consistency
with other DMA drivers in the Zephyr project.
Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
1. Corrected the burst length processing to be handled in bytes
for the siwx917 DMA drivers.
2. Removed overlay and configuration files associated with the
chan_blen_transfer test application. The chan_blen_transfer
test application attempted to use 8 and 16 byte bursts, which
are not supported by the siwx91x UDMA.
Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
#84065 replaced diagnostic pragmas with TOOLCHAIN_* macros, but we don't
need to use that here since __used is a cleaner way to indicate that the
function is used and will also prevent it from being optimized away at
link time if LTO is enabled.
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Drivers update to use shared interrupt allocator for Xtensa
and RISCV devices.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add support for 8-channel configurable DMA controller. The driver
supports the following features:
- memory to peripheral (ch0 to ch5)
- peripheral to memory (ch0 to ch5)
- memory to memory (ch6 and ch7)
Each DMA channel is multiplexed between two or more trigger sources:
- ch0 -> SPI0_TX or UART0_RX
- ch1 -> SPI0_RX or UART0_TX
- ch2 -> LRFD or UART0_TX
- ch3 -> ADC0 or UART0_RX
- ch4 -> AES_A or LRFD
- ch5 -> AES_B or ADC0
- ch6 -> Software Event Channel 0
- ch7 -> Software Event Channel 1
Signed-off-by: Julien Panis <jpanis@baylibre.com>
The TOOLCHAIN_DISABLE_WARNING/TOOLCHAIN_ENABLE_WARNING macros are easier
to read and compiler agnostic.
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Some SDMA scripts (e.g multi-fifo) updates the buffer descriptor
count field after a transfer is complete.
Re-initialize the buffer descriptor to point to the correct
transfer size for the next transfer.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Pisit Sawangvonganan
Yongxu Wang
Lucien Zhao
Benjamin Cabé
Anuj Pathak
Yicheng Li
Michael Hope
Tahsin Mutlugun
Furkan Akkiz
jacob kung
Mike J. Chen
Manuel Argüelles
Daniel Baluta
Mahesh Mahadevan
Anas Nashif
Hake Huang
Kai Vehmanen
Sai Santhosh Malae
Vit Stanicek
Sylvio Alves
Pieter De Gendt
Jérôme Pouiller
Fabrice DJIATSA
Adam Berlinger
Serhiy Katsyuba
Andrew Featherstone
Tom Hughes
Raffael Rostagno
Julien Panis
Zhaoxiang Jin