Current interrupt allocator is not taking into account
reserved areas. In case of esp32c6, Wi-Fi isn't properly
configured, causing instability or even non-functional feature.
This adds the reserved area ranges for all risc-v based SoC and
unify the slot finding based on interrupt source.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Fixes a multitude of Kconfigs that wrongly appear on devices
where support is literally impossible
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
For GIC multiple views feature support, all GIC Re-distributor's
GICR_TYPER.last will be set. Because configuration view-0 can
assign non-contiguous CPUs to views other than 0, in this case
the GIC Redistributors' registers won't seem contiguous.
So the GIC driver should cope with multiple sets of redistributors
like multi-chip scenarios. In this patch we add multiple GIC
redistributor regions support in GIC redistributor iteration.
For more information, refer to the Multi view subsection
in the GIC Technical Reference Manual.
For example:
https://developer.arm.com/documentation/101516/0400/Operation-of-GIC-700/Multi-view
Signed-off-by: Ziad Elhanafy <ziad.elhanafy@arm.com>
IRQ 1 is reserved for WiFi in ESP-IDF, which is used as the basis
for the Espressif HAL in Zephyr.
If IRQ 1 is used by Zephyr and too many other peripherals (e.g.
multiple UARTs) are enabled, WiFi stops working.
Marking IRQ 1 as "not available" seems to fix the issue.
Fixes#82874
Signed-off-by: Martin Jäger <martin@libre.solar>
Commit e63c6cd534 introduced device API
macros to be used by driver implementations. The DEVICE_API macro
ensures the passed API instance is placed in the corresponding iterable
section to allow for runtime checks.
Add wrapper DEVICE_API macro to all its_driver_api instances.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
This commit adds the pfic interrupt controller driver for WCH CH32V003.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>
Instead of doing an `irq_lock()`, use per-instance spinlock instead.
Refactored out an unlocked version of `local_irq_is_enabled`
from `riscv_plic_irq_is_enabled()` to achieve that.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
The `arch_proc_id()` returns the hartid of a CPU, which may not start
from zero. The way that it's used as an index to access `save_irq[]`
array is wrong, use `arch_curr_cpu()->id` instead.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
In case of multiple OSes running on different CPU Cores which share the
same GIC controller, need to avoid the distributor re-configured to avoid
crash the OS has already been started.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Initialize the 'enabled' variable before using it.
This fixes the following compilation warning:
"warning: 'enabled' may be used uninitialized [-Wmaybe-uninitialized]"
issued when compiling with `CONFIG_DEBUG` enabled.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Tested-by: Daniel Baluta <daniel.baluta@nxp.com>
The Drivers using Pinctrl should be turning Pinctrl on
this should not be the responsibility of the board. This
commit removes CONFIG_PINCTRL from the boards side for nxp boards.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Add support for PM. The strategy is as follows:
1) For level 1 interrupts: don't care, these don't
require the PM domain of irqsteer to be turned on
since they are, well, direct.
2) For level 2 interrupts: use the reference count
of the dispatchers.
Upon doing a get() on a dispatcher with its reference count
set to 0, before enabling the IRQ (meaning accessing the
reg. space) increment the reference count of the irqstr device
(which will result in the PM domain being enabled if 0).
Upon doin a put() on a dispatcher with its reference count
set to 1, after disabling the IRQ (meaning accessing the
reg. space) decrement the reference count of the irqstr device
(which will result in the PM domain being disabled if 0).
In summary, the PM domain of the device will be enabled if
at least one dispatcher is in use. On the other hand, the
PM domain of the device will be disabled if there's no
dispatchers in use (assuming there's no other dependencies).
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Currently, all dispatcher interrupts are enabled during
the driver init() function, which will cause a bus fault
unless the PM domain associated with irqsteer is powered on.
Since PM will be done during irq_enable()/irq_disable(),
add support for dynamically enabling/disabling dispatchers.
This way, the reg. space of the dispatchers will be accessed
when the PM domain is powered on.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Currently, shared interrupts pose a big problem because
irq_disable() doesn't keep track of the number of clients
using that interrupt line. As such, add a reference count
mechanism which will stop the interrupt from being disabled
if there's still clients using it.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Convert the compilation of the trigger type feature to depend
on Kconfig, following the same pattern of software-triggered
interrupt.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Implement `riscv_plic_irq_set_pending()` to trigger a
software-generated interrupt.
The "4. Interrupt Pending Bits" of the riscv-plic specs
described the reading of the pending bits, but not the writing
Since not all PLIC implementations support software-generated
interrupt, the function is compiled only when
`CONFIG_PLIC_SUPPORTS_SOFT_INTERRUPT` is enabled on PLIC that
supports it, such as the Andes' NCEPLIC100.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Correct several inconsistent parameter names in the following functions:
- stm32_gpio_intc_select_line_trigger: rename `trigger` to `trg`
to match the header file.
- stm32_gpio_intc_set_irq_callback: rename the callback argument to `user`
to match the `stm32_gpio_irq_cb_t` type.
- stm32_exti_get_line_src_port: rename `pin` to `line` to align with
the Doxygen comment and implementation.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
The functions to obtain the address are hardcoded to return
the address of the first core when `CONFIG_SMP != y`, this
causes an issue with enabling an IRQ when there are more than
one core in the system (`CONFIG_MP_MAX_NUM_CPUS > 1`), as the
driver would first enable the IRQ on the first core, and when
it tries to obtain the address for the following cores and
disable the IRQ on them, the functions continue to return the
address of the first core, causing the IRQ to be disabled
on the first core.
Fix this by determine if `CONFIG_MP_MAX_NUM_CPUS > 1` instead
of `CONFIG_SMP=y` when returning the address.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
- Implement irq-set-affinity in RISCV PLIC.
- Added new affinity shell command to get/set the irq(s)
affinity in runtime, when `0` is sent as the `local_irq`, it
means set/get all IRQs affinity.
- Some minor optimizations
Updated the build_all test to build this new configuration.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Allow IRQs to work on every hart regardless of the mapping
of the contexts.
Add a test to validate the hart-context mapping.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Move the lock out from the `plic_irq_enable_set_state()` function
to cover the entire configuration process, so the whole of
enable/disable is atomic.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Adds a driver for the STM32WB0 series GPIO interrupt controller.
This driver implements the STM32 GPIO INTC API, along with an extension
function used to check if a specific line is available on current board.
This also extends the GPIO INTC API to support level-sensitive interrupts,
as this feature is available on STM32WB0.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
In corner case, the pending ISR will be triggered immediately
after enable the IRQ, this PR will setting CPU affinity first
to avoid routing the unexpected IRQ to other CPUs.
Signed-off-by: chao an <anchao@lixiang.com>
This commit rebrands the STM32 EXTI API to a more hardware-agnostic
"GPIO interrupt controller" API, in anticipation of the introduction of
new series lacking the EXTI peripheral. The GPIO and EXTI drivers are
updated to match the rebranded API.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
This commit makes the contents of the stm32_exti_line_t data type opaque to
the EXTI GPIO interrupt controller API users. The GPIO driver is updated
to comply with this API change.
N.B.: while some assertions are removed as part of this commit, they were
broken since forever anyways, so nothing of value is lost.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Move the functions that interact with EXTI configuration registers to
select or get the GPIO port that triggers events on a given EXTI line
to the EXTI driver.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
This commit reorders the functions in the EXTI driver.
Internal functions and exported functions are now grouped with each other.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
This commit changes the EXTI driver API to use unsigned types
for all parameters previously typed as `int`, as the signedness
is unneeded and unwanted.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
All assertions performed in the EXTI drivers were wrong, as they passed
values to __ASSERT_NO_MSG instead of predicates. Update all assertions
to be actually useful.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
When CONFIG_RISCV_VECTORED_MODE is disabled, CLIC claims interrupts using
CSR 'mnxti' and handles all pending interrupts before exiting the ISR.
When CONFIG_RISCV_VECTORED_MODE is enabled, all interrupts use vector mode
and are claimed automatically. The RISC-V common ISR is used for interrupts
hooked into SW ISR table, but it only handle one pending interrupt per ISR.
This commit enhances CLIC to set vector mode for direct ISRs only and use
the CLIC common entry for regular ISRs to handles multiple pending
interrupts in an ISR.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Introduce riscv_clic_irq_vector_set() to implement z_riscv_irq_vector_set()
for CLIC. This commit also introduces CONFIG_CLIC_SMCLICSHV_EXT to indicate
support for the smclicshv extenion and riscv_clic_irq_vector_set().
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Fixes repeated allocation of interrupt sources by successive calls
to esp_intr_alloc or esp_intr_enable for the same source.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Print the ISR & its ARG along with the IRQ and Hits in
`plic stats get <intc>` command, i.e.
```CONFIG_SYMTAB=n
uart:~$ plic stats get interrupt-controller@c000000
IRQ Hits ISR(ARG)
10 541 0x800054ee(0x80008170)
```
```CONFIG_SYMTAB=y
uart:~$ plic stats get interrupt-controller@c000000
IRQ Hits ISR(ARG)
10 114 uart_ns16550_isr(0x80008230)
```
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
After flashed EC image, we needed to manually press the reset button
on it8xxx2_evb. Now, without pressing the button, we can disable
debug mode and trigger a watchdog hard reset for running tests.
After flash EC, running below tests can pass (without pressing the button):
west build -p always -b it8xxx2_evb tests/drivers/watchdog/wdt_basic_api
west build -p always -b it8xxx2_evb tests/kernel/timer/timer_api
west build -p always -b it8xxx2_evb tests/kernel/fatal/exception
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
In the it8xxx2 chip, the interrupt for INT0 is reserved. However,in some
stress tests, the unhandled IRQ0 issue occurs. To prevent the system from
going directly into kernel panic, we implemented a workaround by
registering interrupt number 0 and doing nothing in the IRQ0 handler.
The side effect of this solution is that when IRQ0 is triggered, it will
take some time to execute the routine. There is no need to worry about
missing interrupts because each IRQ's ISR is write-clear, and if the
status is not cleared, it will continue to trigger.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
add helper for interrupts, so multiple
instances of peripherals work.
this way out-off-tree peripherals are supported.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Sylvio Alves
Hoang Nguyen
Jamie McCrae
Ziad Elhanafy
Martin Jäger
Pieter De Gendt
Michael Hope
Yong Cong Sin
Yong Cong Sin
Nils Bosbach
Jiafei Pan
Laurentiu Mihalcea
Emilio Benavente
Pisit Sawangvonganan
Mathieu Choplain
chao an
Tim Lin
Jimmy Zheng
Raffael Rostagno
Manuel Argüelles
Dino Li
Fin Maaß