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soc: rw: Enable flexcomm wakeup/sleep clocking 

Following the new feature in the flexcomm driver to be able to wake up
from low power mode, the clock control drivers have to handle the
platform specific details, so this commit adds to the already ugly mess
that is the LPC syscon driver which is used by RW currently and makes
the required devicetree changes.

Make the console/shell uart on the FRDM_RW612 take advantage of this by
default.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
pull/90887/head
Declan Snyder 2 months ago committed by Benjamin Cabé
parent
e5a35e6435
commit
f1df21278c
4 changed files with 62 additions and 5 deletions
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  1. 1
      boards/nxp/frdm_rw612/frdm_rw612_common.dtsi
  2. 50
      drivers/clock_control/clock_control_mcux_syscon.c
  3. 12
      dts/arm/nxp/nxp_rw6xx_common.dtsi
  4. 4
      include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h

1
boards/nxp/frdm_rw612/frdm_rw612_common.dtsi
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@ -63,6 +63,7 @@ @@ -63,6 +63,7 @@
current-speed = <115200>;
pinctrl-0 = <&pinmux_flexcomm3_usart>;
pinctrl-names = "default";
wakeup-source;
};
&flexcomm0 {

50
drivers/clock_control/clock_control_mcux_syscon.c
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@ -1,5 +1,5 @@ @@ -1,5 +1,5 @@
/*
* Copyright 2020-2024 NXP
* Copyright 2020-2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -621,11 +621,59 @@ static int SYSCON_SET_FUNC_ATTR mcux_lpc_syscon_clock_control_set_subsys_rate( @@ -621,11 +621,59 @@ static int SYSCON_SET_FUNC_ATTR mcux_lpc_syscon_clock_control_set_subsys_rate(
}
}
static int mcux_lpc_syscon_clock_control_configure(const struct device *dev,
clock_control_subsys_t sub_system, void *data)
{
#ifdef CONFIG_SOC_SERIES_RW6XX
#define FLEXCOMM_LP_CLK_DECODE(n) (n & 0x80)
uint32_t clock_name = (uint32_t)sub_system;
int flexcomm_num = -1;
switch (clock_name) {
case MCUX_FLEXCOMM0_CLK:
case MCUX_FLEXCOMM0_LP_CLK:
flexcomm_num = 0;
break;
case MCUX_FLEXCOMM1_CLK:
case MCUX_FLEXCOMM1_LP_CLK:
flexcomm_num = 1;
break;
case MCUX_FLEXCOMM2_CLK:
case MCUX_FLEXCOMM2_LP_CLK:
flexcomm_num = 2;
break;
case MCUX_FLEXCOMM3_CLK:
case MCUX_FLEXCOMM3_LP_CLK:
flexcomm_num = 3;
break;
default:
return -ENOTSUP;
}
if (flexcomm_num >= 0) {
static uint32_t frgclksels[4];
static uint32_t frgctls[4];
if (FLEXCOMM_LP_CLK_DECODE(clock_name)) {
frgclksels[flexcomm_num] = CLKCTL1->FLEXCOMM[flexcomm_num].FRGCLKSEL;
frgctls[flexcomm_num] = CLKCTL1->FLEXCOMM[flexcomm_num].FRGCTL;
CLKCTL1->FLEXCOMM[flexcomm_num].FRGCLKSEL = 0;
CLKCTL1->FLEXCOMM[flexcomm_num].FRGCTL = 0;
} else {
CLKCTL1->FLEXCOMM[flexcomm_num].FRGCLKSEL = frgclksels[flexcomm_num];
CLKCTL1->FLEXCOMM[flexcomm_num].FRGCTL = frgctls[flexcomm_num];
}
}
#endif
return 0;
}
static DEVICE_API(clock_control, mcux_lpc_syscon_api) = {
.on = mcux_lpc_syscon_clock_control_on,
.off = mcux_lpc_syscon_clock_control_off,
.get_rate = mcux_lpc_syscon_clock_control_get_subsys_rate,
.set_rate = mcux_lpc_syscon_clock_control_set_subsys_rate,
.configure = mcux_lpc_syscon_clock_control_configure,
};
#define LPC_CLOCK_INIT(n) \

12
dts/arm/nxp/nxp_rw6xx_common.dtsi
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@ -245,7 +245,8 @@ @@ -245,7 +245,8 @@
compatible = "nxp,lpc-flexcomm";
reg = <0x106000 0x1000>;
interrupts = <14 0>;
clocks = <&clkctl1 MCUX_FLEXCOMM0_CLK>;
clocks = <&clkctl1 MCUX_FLEXCOMM0_CLK &clkctl1 MCUX_FLEXCOMM0_LP_CLK>;
clock-names = "default", "sleep";
resets = <&rstctl1 NXP_SYSCON_RESET(0, 8)>;
dmas = <&dma0 0>, <&dma0 1>;
dma-names = "rx", "tx";
@ -258,7 +259,8 @@ @@ -258,7 +259,8 @@
compatible = "nxp,lpc-flexcomm";
reg = <0x107000 0x1000>;
interrupts = <15 0>;
clocks = <&clkctl1 MCUX_FLEXCOMM1_CLK>;
clocks = <&clkctl1 MCUX_FLEXCOMM1_CLK &clkctl1 MCUX_FLEXCOMM1_LP_CLK>;
clock-names = "default", "sleep";
resets = <&rstctl1 NXP_SYSCON_RESET(0, 9)>;
dmas = <&dma0 2>, <&dma0 3>;
dma-names = "rx", "tx";
@ -271,7 +273,8 @@ @@ -271,7 +273,8 @@
compatible = "nxp,lpc-flexcomm";
reg = <0x108000 0x1000>;
interrupts = <16 0>;
clocks = <&clkctl1 MCUX_FLEXCOMM2_CLK>;
clocks = <&clkctl1 MCUX_FLEXCOMM2_CLK &clkctl1 MCUX_FLEXCOMM2_LP_CLK>;
clock-names = "default", "sleep";
resets = <&rstctl1 NXP_SYSCON_RESET(0, 10)>;
dmas = <&dma0 4>, <&dma0 5>;
dma-names = "rx", "tx";
@ -284,7 +287,8 @@ @@ -284,7 +287,8 @@
compatible = "nxp,lpc-flexcomm";
reg = <0x109000 0x1000>;
interrupts = <17 0>;
clocks = <&clkctl1 MCUX_FLEXCOMM3_CLK>;
clocks = <&clkctl1 MCUX_FLEXCOMM3_CLK &clkctl1 MCUX_FLEXCOMM3_LP_CLK>;
clock-names = "default", "sleep";
resets = <&rstctl1 NXP_SYSCON_RESET(0, 11)>;
dmas = <&dma0 6>, <&dma0 7>;
dma-names = "rx", "tx";

4
include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h
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@ -30,6 +30,10 @@ @@ -30,6 +30,10 @@
#define MCUX_FLEXCOMM2_CLK MCUX_LPC_CLK_ID(0x01, 0x02)
#define MCUX_FLEXCOMM3_CLK MCUX_LPC_CLK_ID(0x01, 0x03)
#define MCUX_FLEXCOMM4_CLK MCUX_LPC_CLK_ID(0x01, 0x04)
#define MCUX_FLEXCOMM0_LP_CLK MCUX_LPC_CLK_ID(0x01, 0x80)
#define MCUX_FLEXCOMM1_LP_CLK MCUX_LPC_CLK_ID(0x01, 0x81)
#define MCUX_FLEXCOMM2_LP_CLK MCUX_LPC_CLK_ID(0x01, 0x82)
#define MCUX_FLEXCOMM3_LP_CLK MCUX_LPC_CLK_ID(0x01, 0x83)
#define MCUX_FLEXCOMM5_CLK MCUX_LPC_CLK_ID(0x01, 0x05)
#define MCUX_FLEXCOMM6_CLK MCUX_LPC_CLK_ID(0x01, 0x06)
#define MCUX_FLEXCOMM7_CLK MCUX_LPC_CLK_ID(0x01, 0x07)

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