diff --git a/boards/nxp/frdm_rw612/frdm_rw612_common.dtsi b/boards/nxp/frdm_rw612/frdm_rw612_common.dtsi
index bfefa0e5b50..31ef74793d3 100644
--- a/boards/nxp/frdm_rw612/frdm_rw612_common.dtsi
+++ b/boards/nxp/frdm_rw612/frdm_rw612_common.dtsi
@@ -63,6 +63,7 @@
 	current-speed = <115200>;
 	pinctrl-0 = <&pinmux_flexcomm3_usart>;
 	pinctrl-names = "default";
+	wakeup-source;
 };
 
 &flexcomm0 {
diff --git a/drivers/clock_control/clock_control_mcux_syscon.c b/drivers/clock_control/clock_control_mcux_syscon.c
index ede157ba123..7faee128cdb 100644
--- a/drivers/clock_control/clock_control_mcux_syscon.c
+++ b/drivers/clock_control/clock_control_mcux_syscon.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2020-2024 NXP
+ * Copyright 2020-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -621,11 +621,59 @@ static int SYSCON_SET_FUNC_ATTR mcux_lpc_syscon_clock_control_set_subsys_rate(
 	}
 }
 
+static int mcux_lpc_syscon_clock_control_configure(const struct device *dev,
+						   clock_control_subsys_t sub_system, void *data)
+{
+#ifdef CONFIG_SOC_SERIES_RW6XX
+#define FLEXCOMM_LP_CLK_DECODE(n) (n & 0x80)
+	uint32_t clock_name = (uint32_t)sub_system;
+	int flexcomm_num = -1;
+
+	switch (clock_name) {
+	case MCUX_FLEXCOMM0_CLK:
+	case MCUX_FLEXCOMM0_LP_CLK:
+		flexcomm_num = 0;
+		break;
+	case MCUX_FLEXCOMM1_CLK:
+	case MCUX_FLEXCOMM1_LP_CLK:
+		flexcomm_num = 1;
+		break;
+	case MCUX_FLEXCOMM2_CLK:
+	case MCUX_FLEXCOMM2_LP_CLK:
+		flexcomm_num = 2;
+		break;
+	case MCUX_FLEXCOMM3_CLK:
+	case MCUX_FLEXCOMM3_LP_CLK:
+		flexcomm_num = 3;
+		break;
+	default:
+		return -ENOTSUP;
+	}
+
+	if (flexcomm_num >= 0) {
+		static uint32_t frgclksels[4];
+		static uint32_t frgctls[4];
+
+		if (FLEXCOMM_LP_CLK_DECODE(clock_name)) {
+			frgclksels[flexcomm_num] = CLKCTL1->FLEXCOMM[flexcomm_num].FRGCLKSEL;
+			frgctls[flexcomm_num] = CLKCTL1->FLEXCOMM[flexcomm_num].FRGCTL;
+			CLKCTL1->FLEXCOMM[flexcomm_num].FRGCLKSEL = 0;
+			CLKCTL1->FLEXCOMM[flexcomm_num].FRGCTL = 0;
+		} else {
+			CLKCTL1->FLEXCOMM[flexcomm_num].FRGCLKSEL = frgclksels[flexcomm_num];
+			CLKCTL1->FLEXCOMM[flexcomm_num].FRGCTL = frgctls[flexcomm_num];
+		}
+	}
+#endif
+	return 0;
+}
+
 static DEVICE_API(clock_control, mcux_lpc_syscon_api) = {
 	.on = mcux_lpc_syscon_clock_control_on,
 	.off = mcux_lpc_syscon_clock_control_off,
 	.get_rate = mcux_lpc_syscon_clock_control_get_subsys_rate,
 	.set_rate = mcux_lpc_syscon_clock_control_set_subsys_rate,
+	.configure = mcux_lpc_syscon_clock_control_configure,
 };
 
 #define LPC_CLOCK_INIT(n)                                                                          \
diff --git a/dts/arm/nxp/nxp_rw6xx_common.dtsi b/dts/arm/nxp/nxp_rw6xx_common.dtsi
index d4849c40e8a..b56c72d70ee 100644
--- a/dts/arm/nxp/nxp_rw6xx_common.dtsi
+++ b/dts/arm/nxp/nxp_rw6xx_common.dtsi
@@ -245,7 +245,8 @@
 		compatible = "nxp,lpc-flexcomm";
 		reg = <0x106000 0x1000>;
 		interrupts = <14 0>;
-		clocks = <&clkctl1 MCUX_FLEXCOMM0_CLK>;
+		clocks = <&clkctl1 MCUX_FLEXCOMM0_CLK &clkctl1 MCUX_FLEXCOMM0_LP_CLK>;
+		clock-names = "default", "sleep";
 		resets = <&rstctl1 NXP_SYSCON_RESET(0, 8)>;
 		dmas = <&dma0 0>, <&dma0 1>;
 		dma-names = "rx", "tx";
@@ -258,7 +259,8 @@
 		compatible = "nxp,lpc-flexcomm";
 		reg = <0x107000 0x1000>;
 		interrupts = <15 0>;
-		clocks = <&clkctl1 MCUX_FLEXCOMM1_CLK>;
+		clocks = <&clkctl1 MCUX_FLEXCOMM1_CLK &clkctl1 MCUX_FLEXCOMM1_LP_CLK>;
+		clock-names = "default", "sleep";
 		resets = <&rstctl1 NXP_SYSCON_RESET(0, 9)>;
 		dmas = <&dma0 2>, <&dma0 3>;
 		dma-names = "rx", "tx";
@@ -271,7 +273,8 @@
 		compatible = "nxp,lpc-flexcomm";
 		reg = <0x108000 0x1000>;
 		interrupts = <16 0>;
-		clocks = <&clkctl1 MCUX_FLEXCOMM2_CLK>;
+		clocks = <&clkctl1 MCUX_FLEXCOMM2_CLK &clkctl1 MCUX_FLEXCOMM2_LP_CLK>;
+		clock-names = "default", "sleep";
 		resets = <&rstctl1 NXP_SYSCON_RESET(0, 10)>;
 		dmas = <&dma0 4>, <&dma0 5>;
 		dma-names = "rx", "tx";
@@ -284,7 +287,8 @@
 		compatible = "nxp,lpc-flexcomm";
 		reg = <0x109000 0x1000>;
 		interrupts = <17 0>;
-		clocks = <&clkctl1 MCUX_FLEXCOMM3_CLK>;
+		clocks = <&clkctl1 MCUX_FLEXCOMM3_CLK &clkctl1 MCUX_FLEXCOMM3_LP_CLK>;
+		clock-names = "default", "sleep";
 		resets = <&rstctl1 NXP_SYSCON_RESET(0, 11)>;
 		dmas = <&dma0 6>, <&dma0 7>;
 		dma-names = "rx", "tx";
diff --git a/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h b/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h
index b98f2a1079e..b6f3c4a83a6 100644
--- a/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h
+++ b/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h
@@ -30,6 +30,10 @@
 #define MCUX_FLEXCOMM2_CLK  MCUX_LPC_CLK_ID(0x01, 0x02)
 #define MCUX_FLEXCOMM3_CLK  MCUX_LPC_CLK_ID(0x01, 0x03)
 #define MCUX_FLEXCOMM4_CLK  MCUX_LPC_CLK_ID(0x01, 0x04)
+#define MCUX_FLEXCOMM0_LP_CLK  MCUX_LPC_CLK_ID(0x01, 0x80)
+#define MCUX_FLEXCOMM1_LP_CLK  MCUX_LPC_CLK_ID(0x01, 0x81)
+#define MCUX_FLEXCOMM2_LP_CLK  MCUX_LPC_CLK_ID(0x01, 0x82)
+#define MCUX_FLEXCOMM3_LP_CLK  MCUX_LPC_CLK_ID(0x01, 0x83)
 #define MCUX_FLEXCOMM5_CLK  MCUX_LPC_CLK_ID(0x01, 0x05)
 #define MCUX_FLEXCOMM6_CLK  MCUX_LPC_CLK_ID(0x01, 0x06)
 #define MCUX_FLEXCOMM7_CLK  MCUX_LPC_CLK_ID(0x01, 0x07)