Browse Source
Initial version Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>pull/76425/head
Sreeram Tatapudi
1 year ago
committed by
Carles Cufí
14 changed files with 460 additions and 19 deletions
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/*
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* Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or |
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* an affiliate of Cypress Semiconductor Corporation |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#define DT_DRV_COMPAT infineon_cat1_qspi_flash |
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#define SOC_NV_FLASH_NODE DT_PARENT(DT_INST(0, fixed_partitions)) |
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#define PAGE_LEN DT_PROP(SOC_NV_FLASH_NODE, erase_block_size) |
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#include <zephyr/kernel.h> |
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#include <zephyr/devicetree.h> |
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#include <zephyr/drivers/flash.h> |
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#include <zephyr/logging/log.h> |
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#include "cy_serial_flash_qspi.h" |
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#include "cy_smif_memslot.h" |
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LOG_MODULE_REGISTER(flash_infineon_cat1, CONFIG_FLASH_LOG_LEVEL); |
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/* Device config structure */ |
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struct ifx_cat1_flash_config { |
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uint32_t base_addr; |
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uint32_t max_addr; |
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}; |
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/* Data structure */ |
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struct ifx_cat1_flash_data { |
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cyhal_flash_t flash_obj; |
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struct k_sem sem; |
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}; |
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static struct flash_parameters ifx_cat1_flash_parameters = { |
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.write_block_size = DT_PROP(SOC_NV_FLASH_NODE, write_block_size), |
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.erase_value = 0xFF, |
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}; |
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cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_read_cmd = {0}; |
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cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_write_en_cmd = {0}; |
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cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_write_dis_cmd = {0}; |
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cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_erase_cmd = {0}; |
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cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_chip_erase_cmd = {0}; |
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cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_program_cmd = {0}; |
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cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_read_sts_reg_qe_cmd = {0}; |
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cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_read_sts_reg_wip_cmd = {0}; |
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cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_write_sts_reg_qe_cmd = {0}; |
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cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_read_sts_reg_oe_cmd = {0}; |
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cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_write_sts_reg_oe_cmd = {0}; |
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cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_read_latency_cmd = {0}; |
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cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_write_latency_cmd = {0}; |
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cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_read_sfdp_cmd = { |
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/* The 8-bit command. 1 x I/O read command. */ |
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.command = 0x5AU, |
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/* The width of the command transfer. */ |
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.cmdWidth = CY_SMIF_WIDTH_SINGLE, |
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/* The width of the address transfer. */ |
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.addrWidth = CY_SMIF_WIDTH_SINGLE, |
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/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ |
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.mode = 0xFFFFFFFFU, |
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/* The width of the mode command transfer. */ |
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.modeWidth = CY_SMIF_WIDTH_SINGLE, |
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/* The number of dummy cycles. A zero value suggests no dummy cycles. */ |
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.dummyCycles = 8U, |
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/* The width of the data transfer. */ |
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.dataWidth = CY_SMIF_WIDTH_SINGLE, |
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}; |
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cy_stc_smif_octal_ddr_en_seq_t oe_sequence_SFDP_SlaveSlot_0 = { |
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.cmdSeq1Len = CY_SMIF_SFDP_ODDR_CMD_SEQ_MAX_LEN, |
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.cmdSeq2Len = CY_SMIF_SFDP_ODDR_CMD_SEQ_MAX_LEN, |
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.cmdSeq1 = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, |
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.cmdSeq2 = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, |
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}; |
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/* Support for memories with hybrid regions is added in the version 1.50
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* Please refer to the changelog in |
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* https://iot-webserver.aus.cypress.com/projects/iot_release/
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* ASSETS/repo/mtb-pdl-cat1/develop/Latest/deploy/docs/ |
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* pdl_api_reference_manual/html/group__group__smif.html |
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* for more details |
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*/ |
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#if (CY_SMIF_DRV_VERSION_MAJOR > 1) && (CY_SMIF_DRV_VERSION_MINOR >= 50) |
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static cy_stc_smif_hybrid_region_info_t sfdp_slave_slot_0_region_info_storage[16]; |
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#define GENERATE_REGION_INFO_PTR(index, _) &sfdp_slave_slot_0_region_info_storage[index], |
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static cy_stc_smif_hybrid_region_info_t *sfdp_slave_slot_0_region_info[16] = { |
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LISTIFY(16, GENERATE_REGION_INFO_PTR, ())}; |
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#endif |
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cy_stc_smif_mem_device_cfg_t deviceCfg_SFDP_SlaveSlot_0 = { |
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/* Specifies the number of address bytes used by the memory slave device. */ |
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.numOfAddrBytes = 0x03U, |
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/* The size of the memory. */ |
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.memSize = 0x0000100U, |
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/* Specifies the Read command. */ |
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.readCmd = &sfdp_slave_slot_0_read_cmd, |
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/* Specifies the Write Enable command. */ |
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.writeEnCmd = &sfdp_slave_slot_0_write_en_cmd, |
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/* Specifies the Write Disable command. */ |
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.writeDisCmd = &sfdp_slave_slot_0_write_dis_cmd, |
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/* Specifies the Erase command. */ |
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.eraseCmd = &sfdp_slave_slot_0_erase_cmd, |
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/* Specifies the sector size of each erase. */ |
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.eraseSize = 0x0001000U, |
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/* Specifies the Chip Erase command. */ |
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.chipEraseCmd = &sfdp_slave_slot_0_chip_erase_cmd, |
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/* Specifies the Program command. */ |
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.programCmd = &sfdp_slave_slot_0_program_cmd, |
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/* Specifies the page size for programming. */ |
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.programSize = 0x0000100U, |
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/* Specifies the command to read the QE-containing status register. */ |
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.readStsRegQeCmd = &sfdp_slave_slot_0_read_sts_reg_qe_cmd, |
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/* Specifies the command to read the WIP-containing status register. */ |
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.readStsRegWipCmd = &sfdp_slave_slot_0_read_sts_reg_wip_cmd, |
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/* Specifies the read SFDP command */ |
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.readSfdpCmd = &sfdp_slave_slot_0_read_sfdp_cmd, |
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/* Specifies the command to write into the QE-containing status register. */ |
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.writeStsRegQeCmd = &sfdp_slave_slot_0_write_sts_reg_qe_cmd, |
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/* The mask for the status register. */ |
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.stsRegBusyMask = 0x00U, |
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/* The mask for the status register. */ |
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.stsRegQuadEnableMask = 0x00U, |
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/* The max time for the erase type-1 cycle-time in ms. */ |
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.eraseTime = 1U, |
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/* The max time for the chip-erase cycle-time in ms. */ |
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.chipEraseTime = 16U, |
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/* The max time for the page-program cycle-time in us. */ |
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.programTime = 8U, |
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#if (CY_SMIF_DRV_VERSION_MAJOR > 1) && (CY_SMIF_DRV_VERSION_MINOR >= 50) |
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/* Points to NULL or to structure with info about sectors for hybrid memory. */ |
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.hybridRegionCount = 0U, |
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.hybridRegionInfo = sfdp_slave_slot_0_region_info, |
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#endif |
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/* Specifies the command to read variable latency cycles configuration register */ |
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.readLatencyCmd = &sfdp_slave_slot_0_read_latency_cmd, |
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/* Specifies the command to write variable latency cycles configuration register */ |
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.writeLatencyCmd = &sfdp_slave_slot_0_write_latency_cmd, |
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/* Specifies the address for variable latency cycle address */ |
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.latencyCyclesRegAddr = 0x00U, |
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/* Specifies variable latency cycles Mask */ |
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.latencyCyclesMask = 0x00U, |
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/* Specifies data for memory with hybrid sectors */ |
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.octalDDREnableSeq = &oe_sequence_SFDP_SlaveSlot_0, |
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/* Specifies the command to read the OE-containing status register. */ |
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.readStsRegOeCmd = &sfdp_slave_slot_0_read_sts_reg_oe_cmd, |
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/* Specifies the command to write the OE-containing status register. */ |
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.writeStsRegOeCmd = &sfdp_slave_slot_0_write_sts_reg_oe_cmd, |
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/* QE mask for the status registers */ |
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.stsRegOctalEnableMask = 0x00U, |
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/* Octal enable register address */ |
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.octalEnableRegAddr = 0x00U, |
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/* Frequency of operation used in Octal mode */ |
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.freq_of_operation = CY_SMIF_100MHZ_OPERATION, |
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}; |
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cy_stc_smif_mem_config_t sfdp_slave_slot_0 = { |
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/* Determines the slot number where the memory device is placed. */ |
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.slaveSelect = CY_SMIF_SLAVE_SELECT_0, |
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/* Flags. */ |
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.flags = CY_SMIF_FLAG_SMIF_REV_3 | CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN | |
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CY_SMIF_FLAG_DETECT_SFDP | CY_SMIF_FLAG_MERGE_ENABLE, |
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/* The data-line selection options for a slave device. */ |
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.dataSelect = CY_SMIF_DATA_SEL0, |
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/* The base address the memory slave
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* Valid when the memory-mapped mode is enabled. |
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*/ |
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.baseAddress = 0x60000000U, |
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/* The size allocated in the memory map, for the memory slave device.
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* The size is allocated from the base address. Valid when the memory mapped mode is |
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* enabled. |
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*/ |
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.memMappedSize = 0x100000U, |
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/* If this memory device is one of the devices in the dual quad SPI configuration.
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* Valid when the memory mapped mode is enabled. |
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*/ |
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.dualQuadSlots = 0, |
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/* The configuration of the device. */ |
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.deviceCfg = &deviceCfg_SFDP_SlaveSlot_0, |
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/** Continuous transfer merge timeout.
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* After this period the memory device is deselected. A later transfer, even from a |
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* continuous address, starts with the overhead phases (command, address, mode, dummy |
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* cycles). This configuration parameter is available for CAT1B devices. |
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*/ |
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.mergeTimeout = CY_SMIF_MERGE_TIMEOUT_1_CYCLE, |
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}; |
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static inline void flash_ifx_sem_take(const struct device *dev) |
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{ |
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struct ifx_cat1_flash_data *data = dev->data; |
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k_sem_take(&data->sem, K_FOREVER); |
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} |
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static inline void flash_ifx_sem_give(const struct device *dev) |
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{ |
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struct ifx_cat1_flash_data *data = dev->data; |
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k_sem_give(&data->sem); |
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} |
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static int ifx_cat1_flash_read(const struct device *dev, off_t offset, void *data, size_t data_len) |
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{ |
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cy_rslt_t rslt = CY_RSLT_SUCCESS; |
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int ret = 0; |
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if (!data_len) { |
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return 0; |
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} |
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flash_ifx_sem_take(dev); |
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rslt = cy_serial_flash_qspi_read(offset, data_len, data); |
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if (rslt != CY_RSLT_SUCCESS) { |
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LOG_ERR("Error reading @ %lu (Err:0x%x)", offset, rslt); |
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ret = -EIO; |
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} |
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flash_ifx_sem_give(dev); |
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return ret; |
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} |
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static int ifx_cat1_flash_write(const struct device *dev, off_t offset, const void *data, |
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size_t data_len) |
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{ |
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cy_rslt_t rslt = CY_RSLT_SUCCESS; |
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int ret = 0; |
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if (data_len == 0) { |
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return 0; |
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} |
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if (offset < 0) { |
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return -EINVAL; |
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} |
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flash_ifx_sem_take(dev); |
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rslt = cy_serial_flash_qspi_write(offset, data_len, data); |
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if (rslt != CY_RSLT_SUCCESS) { |
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LOG_ERR("Error in writing @ %lu (Err:0x%x)", offset, rslt); |
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ret = -EIO; |
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} |
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flash_ifx_sem_give(dev); |
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return ret; |
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} |
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static int ifx_cat1_flash_erase(const struct device *dev, off_t offset, size_t size) |
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{ |
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cy_rslt_t rslt; |
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int ret = 0; |
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if (offset < 0) { |
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return -EINVAL; |
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} |
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flash_ifx_sem_take(dev); |
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rslt = cy_serial_flash_qspi_erase(offset, size); |
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if (rslt != CY_RSLT_SUCCESS) { |
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LOG_ERR("Error in erasing : 0x%x", rslt); |
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ret = -EIO; |
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} |
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flash_ifx_sem_give(dev); |
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return ret; |
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} |
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#if CONFIG_FLASH_PAGE_LAYOUT |
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static const struct flash_pages_layout ifx_cat1_flash_pages_layout = { |
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.pages_count = DT_REG_SIZE(SOC_NV_FLASH_NODE) / PAGE_LEN, |
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.pages_size = PAGE_LEN, |
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}; |
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static void ifx_cat1_flash_page_layout(const struct device *dev, |
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const struct flash_pages_layout **layout, |
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size_t *layout_size) |
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{ |
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*layout = &ifx_cat1_flash_pages_layout; |
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/*
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* For flash memories which have uniform page sizes, this routine |
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* returns an array of length 1, which specifies the page size and |
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* number of pages in the memory. |
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*/ |
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*layout_size = 1; |
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} |
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#endif /* CONFIG_FLASH_PAGE_LAYOUT */ |
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static const struct flash_parameters *ifx_cat1_flash_get_parameters(const struct device *dev) |
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{ |
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ARG_UNUSED(dev); |
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return &ifx_cat1_flash_parameters; |
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} |
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static int ifx_cat1_flash_init(const struct device *dev) |
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{ |
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struct ifx_cat1_flash_data *data = dev->data; |
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cy_rslt_t rslt = CY_RSLT_SUCCESS; |
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rslt = cy_serial_flash_qspi_init(&sfdp_slave_slot_0, NC, NC, NC, NC, NC, NC, NC, NC, NC, NC, |
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50000000lu); |
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if (rslt != CY_RSLT_SUCCESS) { |
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LOG_ERR("Serial Flash initialization failed [rslt: 0x%x]", rslt); |
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} |
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k_sem_init(&data->sem, 1, 1); |
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return 0; |
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} |
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static const struct flash_driver_api ifx_cat1_flash_driver_api = { |
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.read = ifx_cat1_flash_read, |
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.write = ifx_cat1_flash_write, |
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.erase = ifx_cat1_flash_erase, |
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.get_parameters = ifx_cat1_flash_get_parameters, |
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#ifdef CONFIG_FLASH_PAGE_LAYOUT |
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.page_layout = ifx_cat1_flash_page_layout, |
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#endif |
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}; |
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static struct ifx_cat1_flash_data flash_data; |
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static const struct ifx_cat1_flash_config flash_config = { |
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.base_addr = DT_REG_ADDR(SOC_NV_FLASH_NODE), |
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.max_addr = DT_REG_ADDR(SOC_NV_FLASH_NODE) + DT_REG_SIZE(SOC_NV_FLASH_NODE)}; |
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DEVICE_DT_INST_DEFINE(0, ifx_cat1_flash_init, NULL, &flash_data, &flash_config, POST_KERNEL, |
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CONFIG_FLASH_INIT_PRIORITY, &ifx_cat1_flash_driver_api); |
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@ -0,0 +1,5 @@ |
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description: Infineon CAT1 QSPI flash controller |
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compatible: "infineon,cat1-qspi-flash" |
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include: flash-controller.yaml |
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@ -0,0 +1,10 @@ |
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# Copyright (c) 2024 Cypress Semiconductor Corporation (an Infineon company) or |
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# an affiliate of Cypress Semiconductor Corporation |
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# |
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# SPDX-License-Identifier: Apache-2.0 |
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set(serial_flash_dir ${ZEPHYR_HAL_INFINEON_MODULE_DIR}/serial-flash) |
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zephyr_include_directories(${serial_flash_dir}) |
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|
zephyr_library_sources(${serial_flash_dir}/cy_serial_flash_qspi.c) |
||||||
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Reference in new issue