From eebc998a5aab67c56419219faf3f1c053e266f52 Mon Sep 17 00:00:00 2001 From: Sreeram Tatapudi Date: Mon, 3 Jun 2024 17:05:27 -0700 Subject: [PATCH] drivers: flash: Support for IFX QSPI Flash driver Initial version Signed-off-by: Sreeram Tatapudi --- .../cyw920829m2evk_02/cyw920829m2evk_02.dts | 38 +- .../cyw920829m2evk_02_defconfig | 3 + drivers/flash/CMakeLists.txt | 1 + drivers/flash/Kconfig | 1 + drivers/flash/Kconfig.ifx_cat1 | 12 + drivers/flash/flash_ifx_cat1_qspi.c | 346 ++++++++++++++++++ .../infineon,cat1-qspi-flash.yaml | 5 + modules/hal_infineon/CMakeLists.txt | 3 + modules/hal_infineon/Kconfig | 7 +- .../hal_infineon/mtb-hal-cat1/CMakeLists.txt | 4 +- .../hal_infineon/mtb-pdl-cat1/CMakeLists.txt | 12 +- .../hal_infineon/serial-flash/CMakeLists.txt | 10 + soc/infineon/cat1b/cyw20829/soc.c | 35 ++ west.yml | 2 +- 14 files changed, 460 insertions(+), 19 deletions(-) create mode 100644 drivers/flash/flash_ifx_cat1_qspi.c create mode 100644 dts/bindings/flash_controller/infineon,cat1-qspi-flash.yaml create mode 100644 modules/hal_infineon/serial-flash/CMakeLists.txt diff --git a/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.dts b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.dts index 27a1214a4ab..9cdd5e0c133 100644 --- a/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.dts +++ b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.dts @@ -86,34 +86,44 @@ uart2: &scb2 { }; / { - flash0: flash@60000000 { - compatible = "soc-nv-flash"; - reg = <0x60000000 DT_SIZE_K(512)>; - write-block-size = <16>; - erase-block-size = <256>; - - partitions { - compatible = "fixed-partitions"; + qspi_flash: qspi_flash@40890000 { + compatible = "infineon,cat1-qspi-flash"; + reg = <0x40890000 0x30000>; + #address-cells = <1>; + #size-cells = <1>; + + flash0: flash@60000000 { + compatible = "soc-nv-flash"; + reg = <0x60000000 DT_SIZE_K(512)>; + write-block-size = <1>; + erase-block-size = ; #address-cells = <1>; #size-cells = <1>; - toc2_region: flash@60000000 { + toc2_region: toc2_region@60000000 { compatible = "zephyr,memory-region", "soc-nv-flash"; zephyr,memory-region = "APP_HEADER_FLASH"; reg = <0x60000000 0x50>; }; - bootstrap_region: flash@60000050 { + bootstrap_region: bootstrap_region@60000050 { compatible = "zephyr,memory-region", "soc-nv-flash"; zephyr,memory-region = "BOOTSTRAP_FLASH"; reg = <0x60000050 DT_SIZE_K(12)>; }; - app_region: flash@60003050 { + app_region: app_region@60003050 { compatible = "soc-nv-flash"; reg = <0x60003050 0x6CFB0>; /* 435kb */ }; - storage_partition: flash@60070000 { - compatible = "soc-nv-flash"; - reg = <0x60070000 DT_SIZE_K(64)>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + storage_partition: storage_partition@70000 { + compatible = "soc-nv-flash"; + reg = <0x60000 DT_SIZE_K(64)>; + }; }; }; }; diff --git a/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02_defconfig b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02_defconfig index a59cfbf692a..fea80ce0119 100644 --- a/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02_defconfig +++ b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02_defconfig @@ -29,3 +29,6 @@ CONFIG_CLOCK_CONTROL=y # Main Stack Size CONFIG_MAIN_STACK_SIZE=2048 + +# Enable code/data relocation to move SMIF driver into RAM +CONFIG_CODE_DATA_RELOCATION=y diff --git a/drivers/flash/CMakeLists.txt b/drivers/flash/CMakeLists.txt index ca149a14a85..189b505d645 100644 --- a/drivers/flash/CMakeLists.txt +++ b/drivers/flash/CMakeLists.txt @@ -134,6 +134,7 @@ zephyr_library_include_directories_ifdef( zephyr_library_sources_ifdef(CONFIG_FLASH_SHELL flash_shell.c) zephyr_library_sources_ifdef(CONFIG_FLASH_JESD216 jesd216.c) zephyr_library_sources_ifdef(CONFIG_FLASH_INFINEON_CAT1 flash_ifx_cat1.c) +zephyr_library_sources_ifdef(CONFIG_INFINEON_CAT1_QSPI_FLASH flash_ifx_cat1_qspi.c) zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_NUMAKER soc_flash_numaker.c) zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_NRF_RRAM soc_flash_nrf_rram.c) zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_NRF_MRAM soc_flash_nrf_mram.c) diff --git a/drivers/flash/Kconfig b/drivers/flash/Kconfig index d0bb8e24c55..aae29acca26 100644 --- a/drivers/flash/Kconfig +++ b/drivers/flash/Kconfig @@ -222,6 +222,7 @@ source "drivers/flash/Kconfig.gd32" source "drivers/flash/Kconfig.xmc4xxx" source "drivers/flash/Kconfig.ifx_cat1" + source "drivers/flash/Kconfig.cadence_nand" source "drivers/flash/Kconfig.numaker" diff --git a/drivers/flash/Kconfig.ifx_cat1 b/drivers/flash/Kconfig.ifx_cat1 index 4964258c4ec..e55b2768ede 100644 --- a/drivers/flash/Kconfig.ifx_cat1 +++ b/drivers/flash/Kconfig.ifx_cat1 @@ -16,6 +16,18 @@ config FLASH_INFINEON_CAT1 help Enable the Flash driver for Infineon CAT1 family. +config INFINEON_CAT1_QSPI_FLASH + bool "Infineon CAT1 QSPI FLASH driver" + default y + depends on DT_HAS_INFINEON_CAT1_QSPI_FLASH_ENABLED && DT_HAS_FIXED_PARTITIONS_ENABLED + select FLASH_HAS_PAGE_LAYOUT + select FLASH_HAS_DRIVER_ENABLED + select USE_INFINEON_FLASH + select USE_INFINEON_SMIF + select FLASH_HAS_EXPLICIT_ERASE + help + Enable the QSPI Flash driver for Infineon CAT1 family. + config MPU_ALLOW_FLASH_WRITE bool "Add MPU access to write to flash" diff --git a/drivers/flash/flash_ifx_cat1_qspi.c b/drivers/flash/flash_ifx_cat1_qspi.c new file mode 100644 index 00000000000..44e8686a742 --- /dev/null +++ b/drivers/flash/flash_ifx_cat1_qspi.c @@ -0,0 +1,346 @@ +/* + * Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT infineon_cat1_qspi_flash +#define SOC_NV_FLASH_NODE DT_PARENT(DT_INST(0, fixed_partitions)) + +#define PAGE_LEN DT_PROP(SOC_NV_FLASH_NODE, erase_block_size) + +#include +#include +#include +#include + +#include "cy_serial_flash_qspi.h" +#include "cy_smif_memslot.h" + +LOG_MODULE_REGISTER(flash_infineon_cat1, CONFIG_FLASH_LOG_LEVEL); + +/* Device config structure */ +struct ifx_cat1_flash_config { + uint32_t base_addr; + uint32_t max_addr; +}; + +/* Data structure */ +struct ifx_cat1_flash_data { + cyhal_flash_t flash_obj; + struct k_sem sem; +}; + +static struct flash_parameters ifx_cat1_flash_parameters = { + .write_block_size = DT_PROP(SOC_NV_FLASH_NODE, write_block_size), + .erase_value = 0xFF, +}; + +cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_read_cmd = {0}; + +cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_write_en_cmd = {0}; + +cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_write_dis_cmd = {0}; + +cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_erase_cmd = {0}; + +cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_chip_erase_cmd = {0}; + +cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_program_cmd = {0}; + +cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_read_sts_reg_qe_cmd = {0}; + +cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_read_sts_reg_wip_cmd = {0}; + +cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_write_sts_reg_qe_cmd = {0}; + +cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_read_sts_reg_oe_cmd = {0}; + +cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_write_sts_reg_oe_cmd = {0}; + +cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_read_latency_cmd = {0}; + +cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_write_latency_cmd = {0}; + +cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_read_sfdp_cmd = { + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x5AU, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 8U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE, +}; + +cy_stc_smif_octal_ddr_en_seq_t oe_sequence_SFDP_SlaveSlot_0 = { + .cmdSeq1Len = CY_SMIF_SFDP_ODDR_CMD_SEQ_MAX_LEN, + .cmdSeq2Len = CY_SMIF_SFDP_ODDR_CMD_SEQ_MAX_LEN, + .cmdSeq1 = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .cmdSeq2 = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, +}; + +/* Support for memories with hybrid regions is added in the version 1.50 + * Please refer to the changelog in + * https://iot-webserver.aus.cypress.com/projects/iot_release/ + * ASSETS/repo/mtb-pdl-cat1/develop/Latest/deploy/docs/ + * pdl_api_reference_manual/html/group__group__smif.html + * for more details + */ +#if (CY_SMIF_DRV_VERSION_MAJOR > 1) && (CY_SMIF_DRV_VERSION_MINOR >= 50) +static cy_stc_smif_hybrid_region_info_t sfdp_slave_slot_0_region_info_storage[16]; + +#define GENERATE_REGION_INFO_PTR(index, _) &sfdp_slave_slot_0_region_info_storage[index], + +static cy_stc_smif_hybrid_region_info_t *sfdp_slave_slot_0_region_info[16] = { + LISTIFY(16, GENERATE_REGION_INFO_PTR, ())}; +#endif + +cy_stc_smif_mem_device_cfg_t deviceCfg_SFDP_SlaveSlot_0 = { + /* Specifies the number of address bytes used by the memory slave device. */ + .numOfAddrBytes = 0x03U, + /* The size of the memory. */ + .memSize = 0x0000100U, + /* Specifies the Read command. */ + .readCmd = &sfdp_slave_slot_0_read_cmd, + /* Specifies the Write Enable command. */ + .writeEnCmd = &sfdp_slave_slot_0_write_en_cmd, + /* Specifies the Write Disable command. */ + .writeDisCmd = &sfdp_slave_slot_0_write_dis_cmd, + /* Specifies the Erase command. */ + .eraseCmd = &sfdp_slave_slot_0_erase_cmd, + /* Specifies the sector size of each erase. */ + .eraseSize = 0x0001000U, + /* Specifies the Chip Erase command. */ + .chipEraseCmd = &sfdp_slave_slot_0_chip_erase_cmd, + /* Specifies the Program command. */ + .programCmd = &sfdp_slave_slot_0_program_cmd, + /* Specifies the page size for programming. */ + .programSize = 0x0000100U, + /* Specifies the command to read the QE-containing status register. */ + .readStsRegQeCmd = &sfdp_slave_slot_0_read_sts_reg_qe_cmd, + /* Specifies the command to read the WIP-containing status register. */ + .readStsRegWipCmd = &sfdp_slave_slot_0_read_sts_reg_wip_cmd, + /* Specifies the read SFDP command */ + .readSfdpCmd = &sfdp_slave_slot_0_read_sfdp_cmd, + /* Specifies the command to write into the QE-containing status register. */ + .writeStsRegQeCmd = &sfdp_slave_slot_0_write_sts_reg_qe_cmd, + /* The mask for the status register. */ + .stsRegBusyMask = 0x00U, + /* The mask for the status register. */ + .stsRegQuadEnableMask = 0x00U, + /* The max time for the erase type-1 cycle-time in ms. */ + .eraseTime = 1U, + /* The max time for the chip-erase cycle-time in ms. */ + .chipEraseTime = 16U, + /* The max time for the page-program cycle-time in us. */ + .programTime = 8U, +#if (CY_SMIF_DRV_VERSION_MAJOR > 1) && (CY_SMIF_DRV_VERSION_MINOR >= 50) + /* Points to NULL or to structure with info about sectors for hybrid memory. */ + .hybridRegionCount = 0U, + .hybridRegionInfo = sfdp_slave_slot_0_region_info, +#endif + /* Specifies the command to read variable latency cycles configuration register */ + .readLatencyCmd = &sfdp_slave_slot_0_read_latency_cmd, + /* Specifies the command to write variable latency cycles configuration register */ + .writeLatencyCmd = &sfdp_slave_slot_0_write_latency_cmd, + /* Specifies the address for variable latency cycle address */ + .latencyCyclesRegAddr = 0x00U, + /* Specifies variable latency cycles Mask */ + .latencyCyclesMask = 0x00U, + /* Specifies data for memory with hybrid sectors */ + .octalDDREnableSeq = &oe_sequence_SFDP_SlaveSlot_0, + /* Specifies the command to read the OE-containing status register. */ + .readStsRegOeCmd = &sfdp_slave_slot_0_read_sts_reg_oe_cmd, + /* Specifies the command to write the OE-containing status register. */ + .writeStsRegOeCmd = &sfdp_slave_slot_0_write_sts_reg_oe_cmd, + /* QE mask for the status registers */ + .stsRegOctalEnableMask = 0x00U, + /* Octal enable register address */ + .octalEnableRegAddr = 0x00U, + /* Frequency of operation used in Octal mode */ + .freq_of_operation = CY_SMIF_100MHZ_OPERATION, +}; + +cy_stc_smif_mem_config_t sfdp_slave_slot_0 = { + /* Determines the slot number where the memory device is placed. */ + .slaveSelect = CY_SMIF_SLAVE_SELECT_0, + /* Flags. */ + .flags = CY_SMIF_FLAG_SMIF_REV_3 | CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN | + CY_SMIF_FLAG_DETECT_SFDP | CY_SMIF_FLAG_MERGE_ENABLE, + /* The data-line selection options for a slave device. */ + .dataSelect = CY_SMIF_DATA_SEL0, + /* The base address the memory slave + * Valid when the memory-mapped mode is enabled. + */ + .baseAddress = 0x60000000U, + /* The size allocated in the memory map, for the memory slave device. + * The size is allocated from the base address. Valid when the memory mapped mode is + * enabled. + */ + .memMappedSize = 0x100000U, + /* If this memory device is one of the devices in the dual quad SPI configuration. + * Valid when the memory mapped mode is enabled. + */ + .dualQuadSlots = 0, + /* The configuration of the device. */ + .deviceCfg = &deviceCfg_SFDP_SlaveSlot_0, + /** Continuous transfer merge timeout. + * After this period the memory device is deselected. A later transfer, even from a + * continuous address, starts with the overhead phases (command, address, mode, dummy + * cycles). This configuration parameter is available for CAT1B devices. + */ + .mergeTimeout = CY_SMIF_MERGE_TIMEOUT_1_CYCLE, +}; + +static inline void flash_ifx_sem_take(const struct device *dev) +{ + struct ifx_cat1_flash_data *data = dev->data; + + k_sem_take(&data->sem, K_FOREVER); +} + +static inline void flash_ifx_sem_give(const struct device *dev) +{ + struct ifx_cat1_flash_data *data = dev->data; + + k_sem_give(&data->sem); +} + +static int ifx_cat1_flash_read(const struct device *dev, off_t offset, void *data, size_t data_len) +{ + cy_rslt_t rslt = CY_RSLT_SUCCESS; + int ret = 0; + + if (!data_len) { + return 0; + } + + flash_ifx_sem_take(dev); + + rslt = cy_serial_flash_qspi_read(offset, data_len, data); + if (rslt != CY_RSLT_SUCCESS) { + LOG_ERR("Error reading @ %lu (Err:0x%x)", offset, rslt); + ret = -EIO; + } + + flash_ifx_sem_give(dev); + return ret; +} + +static int ifx_cat1_flash_write(const struct device *dev, off_t offset, const void *data, + size_t data_len) +{ + cy_rslt_t rslt = CY_RSLT_SUCCESS; + int ret = 0; + + if (data_len == 0) { + return 0; + } + + if (offset < 0) { + return -EINVAL; + } + + flash_ifx_sem_take(dev); + + rslt = cy_serial_flash_qspi_write(offset, data_len, data); + if (rslt != CY_RSLT_SUCCESS) { + LOG_ERR("Error in writing @ %lu (Err:0x%x)", offset, rslt); + ret = -EIO; + } + + flash_ifx_sem_give(dev); + return ret; +} + +static int ifx_cat1_flash_erase(const struct device *dev, off_t offset, size_t size) +{ + cy_rslt_t rslt; + int ret = 0; + + if (offset < 0) { + return -EINVAL; + } + + flash_ifx_sem_take(dev); + + rslt = cy_serial_flash_qspi_erase(offset, size); + if (rslt != CY_RSLT_SUCCESS) { + LOG_ERR("Error in erasing : 0x%x", rslt); + ret = -EIO; + } + + flash_ifx_sem_give(dev); + return ret; +} + +#if CONFIG_FLASH_PAGE_LAYOUT +static const struct flash_pages_layout ifx_cat1_flash_pages_layout = { + .pages_count = DT_REG_SIZE(SOC_NV_FLASH_NODE) / PAGE_LEN, + .pages_size = PAGE_LEN, +}; + +static void ifx_cat1_flash_page_layout(const struct device *dev, + const struct flash_pages_layout **layout, + size_t *layout_size) +{ + *layout = &ifx_cat1_flash_pages_layout; + + /* + * For flash memories which have uniform page sizes, this routine + * returns an array of length 1, which specifies the page size and + * number of pages in the memory. + */ + *layout_size = 1; +} +#endif /* CONFIG_FLASH_PAGE_LAYOUT */ + +static const struct flash_parameters *ifx_cat1_flash_get_parameters(const struct device *dev) +{ + ARG_UNUSED(dev); + + return &ifx_cat1_flash_parameters; +} + +static int ifx_cat1_flash_init(const struct device *dev) +{ + struct ifx_cat1_flash_data *data = dev->data; + cy_rslt_t rslt = CY_RSLT_SUCCESS; + + rslt = cy_serial_flash_qspi_init(&sfdp_slave_slot_0, NC, NC, NC, NC, NC, NC, NC, NC, NC, NC, + 50000000lu); + if (rslt != CY_RSLT_SUCCESS) { + LOG_ERR("Serial Flash initialization failed [rslt: 0x%x]", rslt); + } + + k_sem_init(&data->sem, 1, 1); + + return 0; +} + +static const struct flash_driver_api ifx_cat1_flash_driver_api = { + .read = ifx_cat1_flash_read, + .write = ifx_cat1_flash_write, + .erase = ifx_cat1_flash_erase, + .get_parameters = ifx_cat1_flash_get_parameters, +#ifdef CONFIG_FLASH_PAGE_LAYOUT + .page_layout = ifx_cat1_flash_page_layout, +#endif +}; + +static struct ifx_cat1_flash_data flash_data; + +static const struct ifx_cat1_flash_config flash_config = { + .base_addr = DT_REG_ADDR(SOC_NV_FLASH_NODE), + .max_addr = DT_REG_ADDR(SOC_NV_FLASH_NODE) + DT_REG_SIZE(SOC_NV_FLASH_NODE)}; + +DEVICE_DT_INST_DEFINE(0, ifx_cat1_flash_init, NULL, &flash_data, &flash_config, POST_KERNEL, + CONFIG_FLASH_INIT_PRIORITY, &ifx_cat1_flash_driver_api); diff --git a/dts/bindings/flash_controller/infineon,cat1-qspi-flash.yaml b/dts/bindings/flash_controller/infineon,cat1-qspi-flash.yaml new file mode 100644 index 00000000000..dd79972b8ba --- /dev/null +++ b/dts/bindings/flash_controller/infineon,cat1-qspi-flash.yaml @@ -0,0 +1,5 @@ +description: Infineon CAT1 QSPI flash controller + +compatible: "infineon,cat1-qspi-flash" + +include: flash-controller.yaml diff --git a/modules/hal_infineon/CMakeLists.txt b/modules/hal_infineon/CMakeLists.txt index c6d9d95aa24..0715737250f 100644 --- a/modules/hal_infineon/CMakeLists.txt +++ b/modules/hal_infineon/CMakeLists.txt @@ -34,6 +34,9 @@ if (CONFIG_SOC_FAMILY_INFINEON_CAT1 AND NOT CONFIG_SOC_FAMILY_PSOC6_LEGACY) ## Add abstraction-rtos sources add_subdirectory(abstraction-rtos) + + add_subdirectory(serial-flash) + endif() ## Add Wi-Fi assets for AIROC devices diff --git a/modules/hal_infineon/Kconfig b/modules/hal_infineon/Kconfig index fb1431faed2..1b1737d45fd 100644 --- a/modules/hal_infineon/Kconfig +++ b/modules/hal_infineon/Kconfig @@ -77,8 +77,13 @@ config USE_INFINEON_FLASH help Enable Flash HAL module driver for Infineon devices -endif # SOC_FAMILY_INFINEON_CAT1 || SOC_FAMILY_PSOC6_LEGACY config USE_INFINEON_ABSTRACTION_RTOS bool "Abstraction RTOS component (Zephyr support)" help Enable Abstraction RTOS component with Zephyr support +config USE_INFINEON_SMIF + bool + help + Enable SMIF HAL driver for Infineon devices + +endif # SOC_FAMILY_INFINEON_CAT1 || SOC_FAMILY_PSOC6_LEGACY diff --git a/modules/hal_infineon/mtb-hal-cat1/CMakeLists.txt b/modules/hal_infineon/mtb-hal-cat1/CMakeLists.txt index 2d7641f59b6..e759a471f79 100644 --- a/modules/hal_infineon/mtb-hal-cat1/CMakeLists.txt +++ b/modules/hal_infineon/mtb-hal-cat1/CMakeLists.txt @@ -74,6 +74,7 @@ zephyr_library_sources_ifdef(CONFIG_SOC_DIE_PSOC6_04 # High level interface for interacting with CAT1 hardware zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_ADC ${hal_dir}/source/cyhal_adc_sar.c) +zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_ADC ${hal_dir}/source/cyhal_analog_common.c) zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_FLASH ${hal_dir}/source/cyhal_nvm.c) zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_I2C ${hal_dir}/source/cyhal_i2c.c) zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_LPTIMER ${hal_dir}/source/cyhal_lptimer.c) @@ -86,8 +87,7 @@ zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_TRNG ${hal_dir}/source/cyhal zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_UART ${hal_dir}/source/cyhal_uart.c) zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_WDT ${hal_dir}/source/cyhal_wdt.c) -if(CONFIG_USE_INFINEON_ADC) - zephyr_library_sources(${hal_dir}/source/cyhal_analog_common.c) +if(CONFIG_USE_INFINEON_ADC OR CONFIG_USE_INFINEON_SMIF) zephyr_library_sources(${hal_dir}/source/cyhal_dma.c) zephyr_library_sources(${hal_dir}/source/cyhal_dma_dmac.c) zephyr_library_sources(${hal_dir}/source/cyhal_dma_dw.c) diff --git a/modules/hal_infineon/mtb-pdl-cat1/CMakeLists.txt b/modules/hal_infineon/mtb-pdl-cat1/CMakeLists.txt index fd14d6da280..ed33a73bfcd 100644 --- a/modules/hal_infineon/mtb-pdl-cat1/CMakeLists.txt +++ b/modules/hal_infineon/mtb-pdl-cat1/CMakeLists.txt @@ -55,9 +55,19 @@ if(CONFIG_USE_INFINEON_UART OR CONFIG_USE_INFINEON_I2C OR CONFIG_USE_INFINEON_SP zephyr_library_sources(${pdl_drv_dir}/source/cy_scb_common.c) endif() -if(CONFIG_USE_INFINEON_ADC) +if(CONFIG_USE_INFINEON_ADC OR CONFIG_USE_INFINEON_SMIF) zephyr_library_sources(${pdl_drv_dir}/source/cy_dma.c) zephyr_library_sources(${pdl_drv_dir}/source/cy_dmac.c) +endif() + +zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_SMIF ${pdl_drv_dir}/source/cy_smif.c) +zephyr_code_relocate(FILES ${pdl_drv_dir}/source/cy_smif.c LOCATION RAM) +zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_SMIF ${pdl_drv_dir}/source/cy_smif_sfdp.c) +zephyr_code_relocate(FILES ${pdl_drv_dir}/source/cy_smif_sfdp.c LOCATION RAM) +zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_SMIF ${pdl_drv_dir}/source/cy_smif_memslot.c) +zephyr_code_relocate(FILES ${pdl_drv_dir}/source/cy_smif_memslot.c LOCATION RAM) + +if(CONFIG_USE_INFINEON_ADC) zephyr_library_sources(${pdl_drv_dir}/source/cy_sysanalog.c) endif() diff --git a/modules/hal_infineon/serial-flash/CMakeLists.txt b/modules/hal_infineon/serial-flash/CMakeLists.txt new file mode 100644 index 00000000000..49ef6358f2d --- /dev/null +++ b/modules/hal_infineon/serial-flash/CMakeLists.txt @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Cypress Semiconductor Corporation (an Infineon company) or +# an affiliate of Cypress Semiconductor Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +set(serial_flash_dir ${ZEPHYR_HAL_INFINEON_MODULE_DIR}/serial-flash) + +zephyr_include_directories(${serial_flash_dir}) + +zephyr_library_sources(${serial_flash_dir}/cy_serial_flash_qspi.c) diff --git a/soc/infineon/cat1b/cyw20829/soc.c b/soc/infineon/cat1b/cyw20829/soc.c index 3199a1ac894..5e87a400841 100644 --- a/soc/infineon/cat1b/cyw20829/soc.c +++ b/soc/infineon/cat1b/cyw20829/soc.c @@ -51,8 +51,43 @@ cy_en_sysint_status_t Cy_SysInt_Init(const cy_stc_sysint_t *config, cy_israddres return(status); } +/* + * This function will allow execute from sram region. This is needed only for + * this sample because by default all soc will disable the execute from SRAM. + * An application that requires that the code be executed from SRAM will have + * to configure the region appropriately in arm_mpu_regions.c. + */ +#ifdef CONFIG_ARM_MPU +#include +void disable_mpu_rasr_xn(void) +{ + uint32_t index; + + /* + * Kept the max index as 8(irrespective of soc) because the sram would + * most likely be set at index 2. + */ + for (index = 0U; index < 8; index++) { + MPU->RNR = index; +#if defined(CONFIG_ARMV8_M_BASELINE) || defined(CONFIG_ARMV8_M_MAINLINE) + if (MPU->RBAR & MPU_RBAR_XN_Msk) { + MPU->RBAR ^= MPU_RBAR_XN_Msk; + } +#else + if (MPU->RASR & MPU_RASR_XN_Msk) { + MPU->RASR ^= MPU_RASR_XN_Msk; + } +#endif /* CONFIG_ARMV8_M_BASELINE || CONFIG_ARMV8_M_MAINLINE */ + } +} +#endif /* CONFIG_ARM_MPU */ + static int init_cycfg_platform_wrapper(void) { +#ifdef CONFIG_ARM_MPU + disable_mpu_rasr_xn(); +#endif /* CONFIG_ARM_MPU */ + /* Initializes the system */ SystemInit(); return 0; diff --git a/west.yml b/west.yml index 9454f2e57ad..8866aa164a9 100644 --- a/west.yml +++ b/west.yml @@ -173,7 +173,7 @@ manifest: groups: - hal - name: hal_infineon - revision: f25734a72c585f6675e8254a382e80e78a3cd03a + revision: d48d38ce6c75b749df3c8210af9b39aab2ab6053 path: modules/hal/infineon groups: - hal