boards: nxp: add mcx_n9xx_evk

Another board for the MCXN947 SOC, very similar to FRDM-MCXN947

Signed-off-by: Derek Snell <derek.snell@nxp.com>

boards/nxp/mcx_n9xx_evk/CMakeLists.txt

@@ -0,0 +1,8 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+zephyr_library()
+zephyr_library_sources(board.c)

boards/nxp/mcx_n9xx_evk/Kconfig

@@ -0,0 +1,5 @@
+# Copyright 2024-2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_MCX_N9XX_EVK
+	select BOARD_EARLY_INIT_HOOK

boards/nxp/mcx_n9xx_evk/Kconfig.defconfig

@@ -0,0 +1,24 @@
+# Copyright 2024-2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_MCX_N9XX_EVK
+
+config NET_L2_ETHERNET
+	default y if NETWORKING
+
+if SD_STACK
+
+# SD stack requires larger main stack size
+config MAIN_STACK_SIZE
+	default 1536
+
+endif
+
+if BOOTLOADER_MCUBOOT
+choice MCUBOOT_BOOTLOADER_MODE
+	# Board only supports MCUBoot via "upgrade only" method:
+	default MCUBOOT_BOOTLOADER_MODE_OVERWRITE_ONLY
+endchoice
+endif #BOOTLOADER_MCUBOOT
+
+endif

boards/nxp/mcx_n9xx_evk/Kconfig.mcx_n9xx_evk

@@ -0,0 +1,7 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_MCX_N9XX_EVK
+	select SOC_MCXN947_CPU0 if BOARD_MCX_N9XX_EVK_MCXN947_CPU0 || BOARD_MCX_N9XX_EVK_MCXN947_CPU0_QSPI
+	select SOC_MCXN947_CPU1 if BOARD_MCX_N9XX_EVK_MCXN947_CPU1
+	select SOC_PART_NUMBER_MCXN947VDF

boards/nxp/mcx_n9xx_evk/Kconfig.sysbuild

@@ -0,0 +1,6 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+choice MCUBOOT_MODE
+	default MCUBOOT_MODE_OVERWRITE_ONLY
+endchoice

boards/nxp/mcx_n9xx_evk/board.c

@@ -0,0 +1,445 @@
+/*
+ * Copyright 2024-2025 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr/init.h>
+#include <zephyr/device.h>
+#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
+#include <fsl_clock.h>
+#include <fsl_spc.h>
+#include <soc.h>
+#if CONFIG_USB_DC_NXP_EHCI
+#include "usb_phy.h"
+#include "usb.h"
+
+/* USB PHY configuration */
+#define BOARD_USB_PHY_D_CAL     (0x04U)
+#define BOARD_USB_PHY_TXCAL45DP (0x07U)
+#define BOARD_USB_PHY_TXCAL45DM (0x07U)
+
+usb_phy_config_struct_t usbPhyConfig = {
+	BOARD_USB_PHY_D_CAL, BOARD_USB_PHY_TXCAL45DP, BOARD_USB_PHY_TXCAL45DM,
+};
+#endif
+
+/* Board xtal frequency in Hz */
+#define BOARD_XTAL0_CLK_HZ                        24000000U
+/* Core clock frequency: 150MHz */
+#define CLOCK_INIT_CORE_CLOCK                     150000000U
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+
+/* Update Active mode voltage for OverDrive mode. */
+void power_mode_od(void)
+{
+	/* Set the DCDC VDD regulator to 1.2 V voltage level */
+	spc_active_mode_dcdc_option_t opt = {
+		.DCDCVoltage       = kSPC_DCDC_OverdriveVoltage,
+		.DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength,
+	};
+	SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &opt);
+
+	/* Set the LDO_CORE VDD regulator to 1.2 V voltage level */
+	spc_active_mode_core_ldo_option_t ldo_opt = {
+		.CoreLDOVoltage       = kSPC_CoreLDO_OverDriveVoltage,
+		.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength,
+	};
+	SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldo_opt);
+
+	/* Specifies the 1.2V operating voltage for the SRAM's read/write timing margin */
+	spc_sram_voltage_config_t cfg = {
+		.operateVoltage       = kSPC_sramOperateAt1P2V,
+		.requestVoltageUpdate = true,
+	};
+	SPC_SetSRAMOperateVoltage(SPC0, &cfg);
+}
+
+#if CONFIG_FLASH_MCUX_FLEXSPI_NOR || CONFIG_FLASH_MCUX_FLEXSPI_XIP
+__ramfunc static void enable_cache64(void)
+{
+	/* Make sure the FlexSPI clock is enabled before configuring the FlexSPI cache. */
+	SYSCON->AHBCLKCTRLSET[0] |= SYSCON_AHBCLKCTRL0_FLEXSPI_MASK;
+
+	/* Set command to invalidate all ways and write GO bit to initiate command */
+	CACHE64_CTRL0->CCR = CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_INVW0_MASK;
+	CACHE64_CTRL0->CCR |= CACHE64_CTRL_CCR_GO_MASK;
+	/* Wait until the command completes */
+	while ((CACHE64_CTRL0->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0U) {
+	}
+	/* Enable cache, enable write buffer */
+	CACHE64_CTRL0->CCR = (CACHE64_CTRL_CCR_ENWRBUF_MASK | CACHE64_CTRL_CCR_ENCACHE_MASK);
+
+	/* configure reg0, reg1 to cover the whole FlexSPI
+	 * reg 0 covers the space where Zephyr resides in case of XIP from FlexSPI
+	 * reg 1 covers the storage space in case of XIP from FlexSPI
+	 */
+	CACHE64_POLSEL0->REG0_TOP = 0x7FFC00;
+	CACHE64_POLSEL0->REG1_TOP = 0x0;
+	CACHE64_POLSEL0->POLSEL =
+		(CACHE64_POLSEL_POLSEL_REG0_POLICY(1) | CACHE64_POLSEL_POLSEL_REG1_POLICY(0) |
+		 CACHE64_POLSEL_POLSEL_REG2_POLICY(0));
+
+	__ISB();
+	__DSB();
+}
+#endif
+
+void board_early_init_hook(void)
+{
+	power_mode_od();
+
+	/* Enable SCG clock */
+	CLOCK_EnableClock(kCLOCK_Scg);
+
+	/* FRO OSC setup - begin, enable the FRO for safety switching */
+
+	/* Switch to FRO 12M first to ensure we can change the clock setting */
+	CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);
+
+	/* Configure Flash wait-states to support 1.2V voltage level and 150000000Hz frequency */
+	FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x3U));
+
+	/* Enable FRO HF(48MHz) output */
+	CLOCK_SetupFROHFClocking(48000000U);
+
+#ifdef CONFIG_FLASH_MCUX_FLEXSPI_XIP
+	/* Call function flexspi_clock_safe_config() to move FleXSPI clock to a stable
+	 * clock source when updating the PLL if in XIP (execute code from FlexSPI memory
+	 */
+	flexspi_clock_safe_config();
+#endif
+
+	/* Set up PLL0 */
+	const pll_setup_t pll0Setup = {
+		.pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) |
+			   SCG_APLLCTRL_SELP(13U),
+		.pllndiv = SCG_APLLNDIV_NDIV(8U),
+		.pllpdiv = SCG_APLLPDIV_PDIV(1U),
+		.pllmdiv = SCG_APLLMDIV_MDIV(50U),
+		.pllRate = 150000000U
+	};
+	/* Configure PLL0 to the desired values */
+	CLOCK_SetPLL0Freq(&pll0Setup);
+	/* PLL0 Monitor is disabled */
+	CLOCK_SetPll0MonitorMode(kSCG_Pll0MonitorDisable);
+
+	/* Switch MAIN_CLK to PLL0 */
+	CLOCK_AttachClk(kPLL0_to_MAIN_CLK);
+
+	/* Set AHBCLKDIV divider to value 1 */
+	CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);
+
+	CLOCK_SetupExtClocking(BOARD_XTAL0_CLK_HZ);
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai0)) || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai1))
+	/* < Set up PLL1 */
+	const pll_setup_t pll1_Setup = {
+		.pllctrl = SCG_SPLLCTRL_SOURCE(1U) | SCG_SPLLCTRL_SELI(3U) |
+				 SCG_SPLLCTRL_SELP(1U),
+		.pllndiv = SCG_SPLLNDIV_NDIV(25U),
+		.pllpdiv = SCG_SPLLPDIV_PDIV(10U),
+		.pllmdiv = SCG_SPLLMDIV_MDIV(256U),
+		.pllRate = 24576000U};
+
+	/* Configure PLL1 to the desired values */
+	CLOCK_SetPLL1Freq(&pll1_Setup);
+	/* Set PLL1 CLK0 divider to value 1 */
+	CLOCK_SetClkDiv(kCLOCK_DivPLL1Clk0, 1U);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm0))
+	CLOCK_SetClkDiv(kCLOCK_DivFlexcom0Clk, 1u);
+	CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM0);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm1))
+	/* Configure input clock to be able to reach the datasheet specified SPI band rate. */
+	CLOCK_SetClkDiv(kCLOCK_DivFlexcom1Clk, 1u);
+	CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM1);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm2))
+	/* Configure input clock to be able to reach the datasheet specified SPI band rate. */
+	CLOCK_SetClkDiv(kCLOCK_DivFlexcom2Clk, 1u);
+	CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM2);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm3))
+	/* Configure input clock to be able to reach the datasheet specified SPI band rate. */
+	CLOCK_SetClkDiv(kCLOCK_DivFlexcom3Clk, 1u);
+	CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM3);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm4))
+	/* Configure input clock to be able to reach the datasheet specified SPI band rate. */
+	CLOCK_SetClkDiv(kCLOCK_DivFlexcom4Clk, 1u);
+	CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM4);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm5))
+	CLOCK_SetClkDiv(kCLOCK_DivFlexcom5Clk, 1u);
+	CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM5);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm6))
+	CLOCK_SetClkDiv(kCLOCK_DivFlexcom6Clk, 1u);
+	CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM6);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm7))
+	/* Configure input clock to be able to reach the datasheet specified SPI band rate. */
+	CLOCK_SetClkDiv(kCLOCK_DivFlexcom7Clk, 1u);
+	CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM7);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm8))
+	CLOCK_SetClkDiv(kCLOCK_DivFlexcom8Clk, 1u);
+	CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM8);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm9))
+	CLOCK_SetClkDiv(kCLOCK_DivFlexcom9Clk, 1u);
+	CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM9);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(os_timer))
+	CLOCK_AttachClk(kCLK_1M_to_OSTIMER);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio0))
+	CLOCK_EnableClock(kCLOCK_Gpio0);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio1))
+	CLOCK_EnableClock(kCLOCK_Gpio1);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio2))
+	CLOCK_EnableClock(kCLOCK_Gpio2);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio3))
+	CLOCK_EnableClock(kCLOCK_Gpio3);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio4))
+	CLOCK_EnableClock(kCLOCK_Gpio4);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(dac0))
+	SPC_EnableActiveModeAnalogModules(SPC0, kSPC_controlDac0);
+	CLOCK_SetClkDiv(kCLOCK_DivDac0Clk, 1u);
+	CLOCK_AttachClk(kFRO_HF_to_DAC0);
+
+	CLOCK_EnableClock(kCLOCK_Dac0);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(dac1))
+	SPC_EnableActiveModeAnalogModules(SPC0, kSPC_controlDac1);
+	CLOCK_SetClkDiv(kCLOCK_DivDac1Clk, 1u);
+	CLOCK_AttachClk(kFRO_HF_to_DAC1);
+
+	CLOCK_EnableClock(kCLOCK_Dac1);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(enet))
+	CLOCK_AttachClk(kNONE_to_ENETRMII);
+	CLOCK_EnableClock(kCLOCK_Enet);
+	SYSCON0->PRESETCTRL2 = SYSCON_PRESETCTRL2_ENET_RST_MASK;
+	SYSCON0->PRESETCTRL2 &= ~SYSCON_PRESETCTRL2_ENET_RST_MASK;
+	/* rmii selection for this board */
+	SYSCON->ENET_PHY_INTF_SEL = SYSCON_ENET_PHY_INTF_SEL_PHY_SEL(1);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(wwdt0))
+	CLOCK_SetClkDiv(kCLOCK_DivWdt0Clk, 1u);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ctimer0))
+	CLOCK_SetClkDiv(kCLOCK_DivCtimer0Clk, 1U);
+	CLOCK_AttachClk(kPLL0_to_CTIMER0);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ctimer1))
+	CLOCK_SetClkDiv(kCLOCK_DivCtimer1Clk, 1U);
+	CLOCK_AttachClk(kPLL0_to_CTIMER1);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ctimer2))
+	CLOCK_SetClkDiv(kCLOCK_DivCtimer2Clk, 1U);
+	CLOCK_AttachClk(kPLL0_to_CTIMER2);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ctimer3))
+	CLOCK_SetClkDiv(kCLOCK_DivCtimer3Clk, 1U);
+	CLOCK_AttachClk(kPLL0_to_CTIMER3);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ctimer4))
+	CLOCK_SetClkDiv(kCLOCK_DivCtimer4Clk, 1U);
+	CLOCK_AttachClk(kPLL0_to_CTIMER4);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcan0))
+	CLOCK_SetClkDiv(kCLOCK_DivFlexcan0Clk, 1U);
+	CLOCK_AttachClk(kFRO_HF_to_FLEXCAN0);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usdhc0))
+	CLOCK_SetClkDiv(kCLOCK_DivUSdhcClk, 1u);
+	CLOCK_AttachClk(kFRO_HF_to_USDHC);
+#endif
+
+#if CONFIG_FLASH_MCUX_FLEXSPI_NOR || CONFIG_FLASH_MCUX_FLEXSPI_XIP
+	/* Setup the FlexSPI clock */
+	flexspi_clock_set_freq(MCUX_FLEXSPI_CLK,
+			       DT_PROP(DT_NODELABEL(w25q64jwtbjq), spi_max_frequency));
+	enable_cache64();
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(smartdma))
+	CLOCK_EnableClock(kCLOCK_Smartdma);
+	RESET_PeripheralReset(kSMART_DMA_RST_SHIFT_RSTn);
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(video_sdma))
+	/* Drive CLKOUT from main clock, divided by 25 to yield 6MHz clock
+	 * The camera will use this clock signal to generate
+	 * PCLK, HSYNC, and VSYNC
+	 */
+	CLOCK_AttachClk(kMAIN_CLK_to_CLKOUT);
+	CLOCK_SetClkDiv(kCLOCK_DivClkOut, 25U);
+#endif
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(vref))
+	CLOCK_EnableClock(kCLOCK_Vref);
+	SPC_EnableActiveModeAnalogModules(SPC0, kSPC_controlVref);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpadc0))
+	CLOCK_SetClkDiv(kCLOCK_DivAdc0Clk, 1U);
+	CLOCK_AttachClk(kFRO_HF_to_ADC0);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb0)) && (CONFIG_USB_KINETIS || CONFIG_UDC_KINETIS)
+	CLOCK_AttachClk(kCLK_48M_to_USB0);
+	CLOCK_EnableClock(kCLOCK_Usb0Ram);
+	CLOCK_EnableClock(kCLOCK_Usb0Fs);
+	CLOCK_EnableUsbfsClock();
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb1)) && (CONFIG_USB_DC_NXP_EHCI || CONFIG_UDC_NXP_EHCI)
+	SPC0->ACTIVE_VDELAY = 0x0500;
+	/* Change the power DCDC to 1.8v (By default, DCDC is 1.8V), CORELDO to 1.1v (By default,
+	 * CORELDO is 1.0V)
+	 */
+	SPC0->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK;
+	SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_DCDC_VDD_LVL(0x3) | SPC_ACTIVE_CFG_CORELDO_VDD_LVL(0x3) |
+			    SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK | SPC_ACTIVE_CFG_DCDC_VDD_DS(0x2u);
+	/* Wait until it is done */
+	while (SPC0->SC & SPC_SC_BUSY_MASK) {
+	};
+	if (0u == (SCG0->LDOCSR & SCG_LDOCSR_LDOEN_MASK)) {
+		SCG0->TRIM_LOCK = 0x5a5a0001U;
+		SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK;
+		/* wait LDO ready */
+		while (0U == (SCG0->LDOCSR & SCG_LDOCSR_VOUT_OK_MASK)) {
+		};
+	}
+	SYSCON->AHBCLKCTRLSET[2] |= SYSCON_AHBCLKCTRL2_USB_HS_MASK |
+				    SYSCON_AHBCLKCTRL2_USB_HS_PHY_MASK;
+	SCG0->SOSCCFG &= ~(SCG_SOSCCFG_RANGE_MASK | SCG_SOSCCFG_EREFS_MASK);
+	/* xtal = 20 ~ 30MHz */
+	SCG0->SOSCCFG = (1U << SCG_SOSCCFG_RANGE_SHIFT) | (1U << SCG_SOSCCFG_EREFS_SHIFT);
+	SCG0->SOSCCSR |= SCG_SOSCCSR_SOSCEN_MASK;
+	while (1) {
+		if (SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) {
+			break;
+		}
+	}
+	SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK |
+			      SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_MASK;
+	CLOCK_EnableClock(kCLOCK_UsbHs);
+	CLOCK_EnableClock(kCLOCK_UsbHsPhy);
+	CLOCK_EnableUsbhsPhyPllClock(kCLOCK_Usbphy480M, BOARD_XTAL0_CLK_HZ);
+	CLOCK_EnableUsbhsClock();
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb1)) && CONFIG_USB_DC_NXP_EHCI
+	USB_EhciPhyInit(kUSB_ControllerEhci0, BOARD_XTAL0_CLK_HZ, &usbPhyConfig);
+#endif
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpcmp0))
+	CLOCK_SetClkDiv(kCLOCK_DivCmp0FClk, 1U);
+	CLOCK_AttachClk(kFRO12M_to_CMP0F);
+	SPC_EnableActiveModeAnalogModules(SPC0, (kSPC_controlCmp0 | kSPC_controlCmp0Dac));
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpcmp2))
+	CLOCK_SetClkDiv(kCLOCK_DivCmp2FClk, 1U);
+	CLOCK_AttachClk(kFRO12M_to_CMP2F);
+	SPC_EnableActiveModeAnalogModules(SPC0, (kSPC_controlCmp2 | kSPC_controlCmp2Dac));
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lptmr0))
+
+/*
+ * Clock Select Decides what input source the lptmr will clock from
+ *
+ * 0 <- 12MHz FRO
+ * 1 <- 16K FRO
+ * 2 <- 32K OSC
+ * 3 <- Output from the OSC_SYS
+ */
+#if DT_PROP(DT_NODELABEL(lptmr0), clk_source) == 0x0
+	CLOCK_SetupClockCtrl(kCLOCK_FRO12MHZ_ENA);
+#elif DT_PROP(DT_NODELABEL(lptmr0), clk_source) == 0x1
+	CLOCK_SetupClk16KClocking(kCLOCK_Clk16KToVsys);
+#elif DT_PROP(DT_NODELABEL(lptmr0), clk_source) == 0x2
+	CLOCK_SetupOsc32KClocking(kCLOCK_Osc32kToVsys);
+#elif DT_PROP(DT_NODELABEL(lptmr0), clk_source) == 0x3
+	/* Value here should not exceed 25MHZ when using lptmr */
+	CLOCK_SetupExtClocking(MHZ(24));
+	CLOCK_SetupClockCtrl(kCLOCK_CLKIN_ENA_FM_USBH_LPT);
+#endif /* DT_PROP(DT_NODELABEL(lptmr0), clk_source) */
+
+#endif /* DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lptmr0)) */
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexio0))
+	CLOCK_SetClkDiv(kCLOCK_DivFlexioClk, 1u);
+	CLOCK_AttachClk(kPLL0_to_FLEXIO);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(i3c1), okay)
+	/* Enable 1MHz clock. */
+	SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK;
+
+	CLOCK_SetClkDiv(kCLOCK_DivI3c1FClk, DT_PROP(DT_NODELABEL(i3c1), clk_divider));
+	CLOCK_SetClkDiv(kCLOCK_DivI3c1FClkS, DT_PROP(DT_NODELABEL(i3c1), clk_divider_slow));
+	CLOCK_SetClkDiv(kCLOCK_DivI3c1FClkStc, DT_PROP(DT_NODELABEL(i3c1), clk_divider_tc));
+
+	/* Attach PLL0 clock to I3C, 150MHz / 6 = 25MHz. */
+	CLOCK_AttachClk(kPLL0_to_I3C1FCLK);
+	CLOCK_AttachClk(kCLK_1M_to_I3C1FCLKS);
+	CLOCK_AttachClk(kI3C1FCLK_to_I3C1FCLKSTC);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(sc_timer), okay)
+	/* attach FRO HF to SCT */
+	CLOCK_SetClkDiv(kCLOCK_DivSctClk, 1u);
+	CLOCK_AttachClk(kFRO_HF_to_SCT);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai0))
+	CLOCK_SetClkDiv(kCLOCK_DivSai0Clk, 1u);
+	CLOCK_AttachClk(kPLL1_CLK0_to_SAI0);
+	CLOCK_EnableClock(kCLOCK_Sai0);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai1))
+	CLOCK_SetClkDiv(kCLOCK_DivSai1Clk, 1u);
+	CLOCK_AttachClk(kPLL1_CLK0_to_SAI1);
+	CLOCK_EnableClock(kCLOCK_Sai1);
+#endif
+
+	/* Set SystemCoreClock variable. */
+	SystemCoreClock = CLOCK_INIT_CORE_CLOCK;
+}

boards/nxp/mcx_n9xx_evk/board.cmake

@@ -0,0 +1,37 @@
+#
+# Copyright 2024-2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if(CONFIG_SOC_MCXN947_CPU0 OR CONFIG_SECOND_CORE_MCUX)
+  board_runner_args(jlink "--device=MCXN947_M33_0" "--reset-after-load")
+  board_runner_args(linkserver  "--device=MCXN947:MCX-N9XX-EVK")
+  if(CONFIG_SECOND_CORE_MCUX)
+    board_runner_args(linkserver  "--core=all")
+  else()
+    board_runner_args(linkserver  "--core=cm33_core0")
+  endif()
+  board_runner_args(linkserver  "--override=/device/memory/1/flash-driver=MCXN9xx_S.cfx")
+  board_runner_args(linkserver  "--override=/device/memory/1/location=0x10000000")
+  # Linkserver v1.4.85 and earlier do not include the secure regions in the
+  # MCXN947 memory map, so we add them here
+  board_runner_args(linkserver "--override=/device/memory/-=\{\"location\":\"0x30000000\",\
+                               \"size\":\"0x00060000\",\"type\":\"RAM\"\}")
+  board_runner_args(linkserver "--override=/device/memory/-=\{\"location\":\"0x30060000\",\
+                               \"size\":\"0x00008000\",\"type\":\"RAM\"\}")
+  # Define region for peripherals
+  board_runner_args(linkserver "--override=/device/memory/-=\{\"location\":\"0x50000000\",\
+                               \"size\":\"0x00140000\",\"type\":\"RAM\"\}")
+elseif(CONFIG_SOC_MCXN947_CPU1)
+  board_runner_args(jlink "--device=MCXN947_M33_1" "--reset-after-load")
+  board_runner_args(linkserver  "--device=MCXN947:MCX-N9XX-EVK")
+  board_runner_args(linkserver  "--core=cm33_core1")
+endif()
+
+# Pyocd support added with the NXP.MCXN947_DFP.17.0.0.pack CMSIS Pack
+board_runner_args(pyocd "--target=mcxn947")
+
+include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)

boards/nxp/mcx_n9xx_evk/board.yml

@@ -0,0 +1,9 @@
+board:
+  name: mcx_n9xx_evk
+  full_name: MCX-N9XX-EVK
+  vendor: nxp
+  socs:
+  - name: mcxn947
+    variants:
+    - name: qspi
+      cpucluster: 'cpu0'

boards/nxp/mcx_n9xx_evk/doc/index.rst

@@ -0,0 +1,294 @@
+.. zephyr:board:: mcx_n9xx_evk
+
+Overview
+********
+
+MCX-N9XX-EVK is a full featured evaluation kit for prototyping of MCX N94 / N54
+MCUs. They offer industry standard headers for access to the MCU’s I/Os,
+integrated open-standard serial interfaces and an on-board MCU-Link debugger
+with power measurement capability.  MCX N Series are high-performance, low-power
+microcontrollers with intelligent peripherals and accelerators providing
+multi-tasking capabilities and performance efficiency.
+
+Hardware
+********
+
+- MCX-N947 Dual Arm Cortex-M33 microcontroller running at 150 MHz
+- 2MB dual-bank on chip Flash
+- 512 KB RAM
+- External Quad SPI flash over FlexSPI
+- USB high-speed (Host/Device) with on-chip HS PHY.
+- USB full-speed (Host/Device) with on-chip FS PHY.
+- 10x LP Flexcomms each supporting SPI, I2C, UART
+- FlexCAN with FD, I3Cs, SAI
+- 1x Ethernet with QoS
+- On-board MCU-Link debugger with CMSIS-DAP
+- Arduino Header, FlexIO/LCD Header, mikroBUS, M.2
+
+For more information about the MCX-N947 SoC and MCX-N9XX-EVK board, see:
+
+- `MCX-N947 SoC Website`_
+- `MCX-N947 Datasheet`_
+- `MCX-N947 Reference Manual`_
+- `MCX-N9XX-EVK Website`_
+- `MCX-N9XX-EVK Board User Manual`_
+- `MCX-N9XX-EVK Schematics`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Shields for Supported Features
+==============================
+Some features in the table above are tested with Zephyr shields.  These shields
+are tested on this board:
+- :ref:`lcd_par_s035` - supports the Display interface.  This board uses the
+MIPI_DBI interface of the shield, connected to the FlexIO on-chip peripheral.
+
+Dual Core samples
+*****************
+
++-----------+-------------------+----------------------+
+| Core      | Boot Address      | Comment              |
++===========+===================+======================+
+| CPU0      | 0x10000000[1856K] | primary core flash   |
++-----------+-------------------+----------------------+
+| CPU1      | 0x101d0000[192K]  | secondary core flash |
++-----------+-------------------+----------------------+
+
++----------+------------------+-----------------------+
+| Memory   | Address[Size]    | Comment               |
++==========+==================+=======================+
+| srama    | 0x20000000[320k] | CPU0 ram              |
++----------+------------------+-----------------------+
+| sramg    | 0x20050000[64k]  | CPU1 ram              |
++----------+------------------+-----------------------+
+| sramh    | 0x20060000[32k]  | Shared memory         |
++----------+------------------+-----------------------+
+
+Targets available
+==================
+
+The default configuration file
+:zephyr_file:`boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0_defconfig`
+only enables the first core. CPU0 is the only target that can run standalone.
+
+CPU1 does not work without CPU0 enabling it.
+
+To enable CPU1, create System Build application project and enable the
+second core with config :kconfig:option:`CONFIG_SECOND_CORE_MCUX`.
+
+Please have a look at some already enabled samples:
+
+- :zephyr:code-sample:`ipc-static-vrings`
+- :zephyr:code-sample:`openamp`
+- :zephyr:code-sample:`mbox`
+- :zephyr:code-sample:`mbox_data`
+
+Connections and IOs
+===================
+
+The MCX-N947 SoC has 6 gpio controllers and has pinmux registers which
+can be used to configure the functionality of a pin.
+
++------------+-----------------+----------------------------+
+| Name       | Function        | Usage                      |
++============+=================+============================+
+| P0_PIO1_8  | UART            | UART RX cpu0               |
++------------+-----------------+----------------------------+
+| P1_PIO1_9  | UART            | UART TX cpu0               |
++------------+-----------------+----------------------------+
+| P4_PIO4_3  | UART            | UART RX cpu1               |
++------------+-----------------+----------------------------+
+| P4_PIO4_2  | UART            | UART TX cpu1               |
++------------+-----------------+----------------------------+
+
+System Clock
+============
+
+The MCX-N947 SoC is configured to use PLL0 running at 150MHz as a source for
+the system clock.
+
+Serial Port
+===========
+
+The MCX-N9XX-EVK SoC has 10 FLEXCOMM interfaces for serial communication.
+Flexcomm 4 is configured as UART for the console.
+
+Ethernet
+========
+To use networking samples with the Ethernet jack, change jumper JP13 to pins 2-3.
+
+Programming and Debugging
+*************************
+
+Build and flash applications as usual (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+Configuring a Debug Probe
+=========================
+
+A debug probe is used for both flashing and debugging the board. This board is
+configured by default to use the MCU-Link CMSIS-DAP Onboard Debug Probe.
+
+Using LinkServer
+----------------
+
+LinkServer is the default runner for this board, and supports the factory
+default MCU-Link firmware. Follow the instructions in
+:ref:`mcu-link-cmsis-onboard-debug-probe` to reprogram the default MCU-Link
+firmware. This only needs to be done if the default onboard debug circuit
+firmware was changed. To put the board in ``ISP mode`` to program the firmware,
+short jumper JP24.
+
+Using J-Link
+------------
+
+There are two options. The onboard debug circuit can be updated with Segger
+J-Link firmware by following the instructions in
+:ref:`mcu-link-jlink-onboard-debug-probe`.
+To be able to program the firmware, you need to put the board in ``ISP mode``
+by shortening the jumper JP24.
+The second option is to attach a :ref:`jlink-external-debug-probe` to the
+20-pin SWD connector (J11) of the board. Additionally, the jumper JP6 must
+be shorted.
+For both options use the ``-r jlink`` option with west to use the jlink runner.
+
+.. code-block:: console
+
+   west flash -r jlink
+
+Configuring a Console
+=====================
+
+Connect a USB cable from your PC to J5, and use the serial terminal of your choice
+(minicom, putty, etc.) with the following settings:
+
+- Speed: 115200
+- Data: 8 bits
+- Parity: None
+- Stop bits: 1
+
+Flashing
+========
+
+Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: mcx_n9xx_evk/mcxn947/cpu0
+   :goals: flash
+
+Open a serial terminal, reset the board (press the RESET button), and you should
+see the following message in the terminal:
+
+.. code-block:: console
+
+   *** Booting Zephyr OS build vX.X.X ***
+   Hello World! mcx_n9xx_evk/mcxn947/cpu0
+
+Building a dual-core image
+==========================
+
+The dual-core samples are run using ``mcx_n9xx_evk/mcxn947/cpu0`` target.
+
+Images built for ``mcx_n9xx_evk/mcxn947/cpu1`` will be loaded from flash
+and executed on the second core when :kconfig:option:`CONFIG_SECOND_CORE_MCUX` is selected.
+
+For an example of building for both cores with System Build, see
+:zephyr:code-sample:`ipc-static-vrings`
+
+Here is an example for the :zephyr:code-sample:`mbox_data` application.
+
+.. zephyr-app-commands::
+   :app: zephyr/samples/drivers/mbox_data
+   :board: mcx_n9xx_evk/mcxn947/cpu0
+   :goals: flash
+   :west-args: --sysbuild
+
+Flashing to QSPI
+================
+
+In order to load Zephyr application from QSPI, program a bootloader like
+MCUboot bootloader to internal flash. Here are the steps for the
+:zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :app: zephyr/samples/hello_world
+   :board: mcx_n9xx_evk/mcxn947/cpu0/qspi
+   :gen-args: --sysbuild -- -DSB_CONFIG_BOOTLOADER_MCUBOOT=y
+   :goals: flash
+
+Open a serial terminal, reset the board (press the RESET button), and you should
+see the following message in the terminal:
+
+.. code-block:: console
+
+  *** Booting MCUboot vX.X.X ***
+  *** Using Zephyr OS build vX.X.X ***
+  I: Starting bootloader
+  I: Primary image: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3
+  I: Secondary image: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3
+  I: Boot source: none
+  I: Image index: 0, Swap type: none
+  I: Bootloader chainload address offset: 0x0
+  I: Jumping to the first image slot
+  *** Booting Zephyr OS build vX.X.X ***
+  Hello World! mcx_n9xx_evk/mcxn947/cpu0/qspi
+
+Debugging
+=========
+
+Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: mcx_n9xx_evk/mcxn947/cpu0
+   :goals: debug
+
+Open a serial terminal, step through the application in your debugger, and you
+should see the following message in the terminal:
+
+.. code-block:: console
+
+   *** Booting Zephyr OS build vX.X.X ***
+   Hello World! mcx_n9xx_evk/mcxn947/cpu0
+
+Debugging a dual-core image
+---------------------------
+
+For dual core builds, the secondary core should be placed into a loop,
+then a debugger can be attached.
+As a reference please see (`AN13264`_, section 4.2.3 for more information).
+The reference is for the RT1170 but similar technique can be also used here.
+
+Troubleshooting
+===============
+
+.. include:: ../../common/segger-ecc-systemview.rst
+   :start-after: segger-ecc-systemview
+
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
+.. _MCX-N947 SoC Website:
+   https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-n-series-microcontrollers/mcx-n94x-54x-highly-integrated-multicore-mcus-with-on-chip-accelerators-intelligent-peripherals-and-advanced-security:MCX-N94X-N54X
+
+.. _MCX-N947 Datasheet:
+   https://www.nxp.com/docs/en/data-sheet/MCXNx4xDS.pdf
+
+.. _MCX-N947 Reference Manual:
+   https://www.nxp.com/webapp/Download?colCode=MCXNX4XRM
+
+.. _MCX-N9XX-EVK Website:
+   https://www.nxp.com/design/design-center/development-boards-and-designs/MCX-N9XX-EVK
+
+.. _MCX-N9XX-EVK Board User Manual:
+   https://www.nxp.com/webapp/Download?colCode=UM12036
+
+.. _MCX-N9XX-EVK Schematics:
+   https://www.nxp.com/webapp/Download?colCode=SPF-55276
+
+.. _AN13264:
+   https://www.nxp.com/docs/en/application-note/AN13264.pdf

boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk-pinctrl.dtsi

@@ -0,0 +1,273 @@
+/*
+ * Copyright 2024-2025 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+#include <nxp/mcx/MCXN947VDF-pinctrl.h>
+
+&pinctrl {
+	pinmux_flexcomm1_lpspi: pinmux_flexcomm1_lpspi {
+		group0 {
+			pinmux = <FC1_P0_PIO0_24>,
+				<FC1_P1_PIO0_25>,
+				<FC1_P2_PIO0_26>,
+				<FC1_P3_PIO0_27>;
+			slew-rate = "fast";
+			drive-strength = "low";
+			input-enable;
+		};
+	};
+
+	pinmux_flexcomm2_lpi2c: pinmux_flexcomm2_lpi2c {
+		group0 {
+			pinmux = <FC2_P0_PIO4_0>,
+				<FC2_P1_PIO4_1>;
+			slew-rate = "fast";
+			drive-strength = "low";
+			input-enable;
+			bias-pull-up;
+			drive-open-drain;
+		};
+	};
+
+	pinmux_flexcomm3_lpi2c: pimux_flexcomm3_lpi2c {
+		group0 {
+			pinmux = <FC3_P0_PIO1_0>,
+				<FC3_P1_PIO1_1>;
+			slew-rate = "fast";
+			drive-strength = "low";
+			input-enable;
+			bias-pull-up;
+			drive-open-drain;
+		};
+	};
+
+	pinmux_flexcomm2_lpuart: pinmux_flexcomm2_lpuart {
+		group0 {
+			pinmux = <FC2_P2_PIO4_2>,
+				<FC2_P3_PIO4_3>;
+			slew-rate = "fast";
+			drive-strength = "low";
+			input-enable;
+		};
+	};
+
+	pinmux_flexcomm4_lpuart: pinmux_flexcomm4_lpuart {
+		group0 {
+			pinmux = <FC4_P0_PIO1_8>,
+				<FC4_P1_PIO1_9>;
+			slew-rate = "fast";
+			drive-strength = "low";
+			input-enable;
+		};
+	};
+
+	pinmux_flexspi: pinmux_flexspi {
+		group0 {
+			pinmux = <FLEXSPI0_A_SS0_b_PIO3_0>,
+					<FLEXSPI0_A_SCLK_PIO3_7>,
+					<FLEXSPI0_A_DQS_PIO3_6>,
+					<FLEXSPI0_A_DATA0_PIO3_8>,
+					<FLEXSPI0_A_DATA1_PIO3_9>;
+			input-enable;
+			slew-rate = "fast";
+			drive-strength = "low";
+		};
+		group1 {
+			pinmux = <FLEXSPI0_A_DATA2_PIO3_10>,
+					<FLEXSPI0_A_DATA3_PIO3_11>;
+			input-enable;
+			slew-rate = "fast";
+			drive-strength = "low";
+			bias-pull-up;
+		};
+	};
+
+	pinmux_dac0: pinmux_dac0 {
+		group0 {
+			pinmux = <DAC0_OUT_PIO4_2>;
+			drive-strength = "low";
+			slew-rate = "fast";
+		};
+	};
+
+	pinmux_sai1: pinmux_sai1 {
+		group0 {
+			pinmux = <SAI1_TX_BCLK_PIO3_16>,
+				<SAI1_TX_FS_PIO3_17>,
+				<SAI1_TXD0_PIO3_20>,
+				<SAI1_RX_FS_PIO3_19>,
+				<SAI1_RX_BCLK_PIO3_18>,
+				<SAI1_RXD0_PIO3_21>;
+			drive-strength = "high";
+			slew-rate = "fast";
+			input-enable;
+		};
+	};
+
+	pinmux_enet_qos: pinmux_enet_qos {
+		mdio_group {
+			pinmux = <ENET0_MDC_PIO1_20>,
+				<ENET0_MDIO_PIO1_21>;
+			slew-rate = "fast";
+			drive-strength = "low";
+			input-enable;
+		};
+		mac_group {
+			pinmux = <ENET0_RXDV_PIO1_13>,
+				<ENET0_RXD0_PIO1_14>,
+				<ENET0_RXD1_PIO1_15>,
+				<ENET0_TX_CLK_PIO1_4>,
+				<ENET0_TXEN_PIO1_5>,
+				<ENET0_TXD0_PIO1_6>,
+				<ENET0_TXD1_PIO1_7>;
+			slew-rate = "fast";
+			drive-strength = "low";
+			input-enable;
+		};
+	};
+
+	pinmux_flexpwm1_pwm0: pinmux_flexpwm1_pwm0 {
+		group0 {
+			pinmux = <PWM1_A0_PIO2_6>,
+				<PWM1_B0_PIO2_7>;
+			slew-rate = "fast";
+			drive-strength = "low";
+		};
+	};
+
+	pinmux_flexpwm1_pwm1: pinmux_flexpwm1_pwm1 {
+		group0 {
+			pinmux = <PWM1_A1_PIO2_4>,
+				<PWM1_B1_PIO2_5>;
+			slew-rate = "fast";
+			drive-strength = "low";
+		};
+	};
+
+	pinmux_flexpwm1_pwm2: pinmux_flexpwm1_pwm2 {
+		group0 {
+			pinmux = <PWM1_A2_PIO2_2>,
+				<PWM1_B2_PIO2_3>;
+			slew-rate = "fast";
+			drive-strength = "low";
+		};
+	};
+
+	pinmux_usdhc0: pinmux_usdhc0 {
+		group0 {
+			pinmux = <SDHC0_CMD_PIO2_5>,
+			       <SDHC0_D0_PIO2_3>,
+			       <SDHC0_D1_PIO2_2>,
+			       <SDHC0_D2_PIO2_7>,
+			       <SDHC0_D3_PIO2_6>;
+			slew-rate = "fast";
+			drive-strength = "low";
+			bias-pull-up;
+			input-enable;
+		};
+		group1 {
+			pinmux = <SDHC0_CLK_PIO2_4>;
+			slew-rate = "fast";
+			drive-strength = "low";
+			input-enable;
+		};
+	};
+
+	pinmux_lpadc0: pinmux_lpadc0 {
+		group0 {
+			pinmux = <ADC0_A2_PIO4_23>,
+				<ADC0_A1_PIO4_15>,
+				<ADC0_B1_PIO4_19>;
+			slew-rate = "fast";
+			drive-strength = "low";
+		};
+	};
+
+	pinmux_lpcmp2: pinmux_lpcmp2 {
+		group0 {
+			pinmux = <CMP2_IN0_PIO1_2>;
+			drive-strength = "low";
+			slew-rate = "fast";
+			bias-pull-up;
+		};
+	};
+
+	pinmux_flexcan0: pinmux_flexcan0 {
+		group0 {
+			pinmux = <CAN0_TXD_PIO1_18>,
+				<CAN0_RXD_PIO1_19>;
+			slew-rate = "fast";
+			drive-strength = "low";
+			input-enable;
+		};
+	};
+
+	pinmux_i3c1: pinmux_i3c1 {
+		group0 {
+			pinmux = <I3C1_SDA_PIO1_16>,
+				<I3C1_SCL_PIO1_17>;
+			slew-rate = "fast";
+			drive-strength = "low";
+			input-enable;
+			bias-pull-up;
+		};
+		group1 {
+			pinmux = <I3C1_PUR_PIO1_11>;
+			slew-rate = "fast";
+			drive-strength = "low";
+			input-enable;
+		};
+	};
+
+	pinmux_sctimer: pinmux_sctimer {
+		group0 {
+			pinmux = <SCT0_OUT0_PIO2_2>;
+			slew-rate = "fast";
+			drive-strength = "low";
+			input-enable;
+		};
+	};
+
+	pinmux_flexio_lcd: pinmux_flexio_lcd {
+		group0 {
+			pinmux = <FLEXIO0_D16_PIO2_8>,
+				<FLEXIO0_D17_PIO2_9>,
+				<FLEXIO0_D18_PIO2_10>,
+				<FLEXIO0_D19_PIO2_11>,
+				<FLEXIO0_D20_PIO4_12>,
+				<FLEXIO0_D21_PIO4_13>,
+				<FLEXIO0_D22_PIO4_14>,
+				<FLEXIO0_D23_PIO4_15>,
+				<FLEXIO0_D24_PIO4_16>,
+				<FLEXIO0_D25_PIO4_17>,
+				<FLEXIO0_D26_PIO4_18>,
+				<FLEXIO0_D27_PIO4_19>,
+				<FLEXIO0_D28_PIO4_20>,
+				<FLEXIO0_D29_PIO4_21>,
+				<FLEXIO0_D30_PIO4_22>,
+				<FLEXIO0_D31_PIO4_23>,
+				<PIO0_7>,
+				<PIO0_12>,
+				<PIO4_7>;
+			slew-rate = "fast";
+			drive-strength = "low";
+			input-enable;
+		};
+		group1 {
+			pinmux = <FLEXIO0_D0_PIO0_8>;
+			slew-rate = "fast";
+			drive-strength = "low";
+			input-enable;
+			bias-pull-up;
+		};
+		group2 {
+			pinmux = <FLEXIO0_D1_PIO0_9>;
+			slew-rate = "slow";
+			drive-strength = "low";
+			input-enable;
+			bias-pull-up;
+		};
+	};
+};

boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk.dtsi

@@ -0,0 +1,265 @@
+/*
+ * Copyright 2024-2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "mcx_n9xx_evk-pinctrl.dtsi"
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	aliases{
+		led0 = &red_led;
+		led1 = &green_led;
+		led2 = &blue_led;
+		sw0 = &user_button_2;
+		sw1 = &user_button_3;
+		sdhc0 = &usdhc0;
+		mcuboot-button0 = &user_button_2;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		green_led: led_1 {
+			gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>;
+			label = "Green LED";
+			status = "disabled";
+		};
+		blue_led: led_2 {
+			gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
+			label = "Blue LED";
+			status = "disabled";
+		};
+		red_led: led_3 {
+			gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
+			label = "Red LED";
+			status = "disabled";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		user_button_2: button_0 {
+			label = "User SW2";
+			gpios = <&gpio1 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			zephyr,code = <INPUT_KEY_0>;
+			status = "disabled";
+		};
+		user_button_3: button_1 {
+			label = "User SW3";
+			gpios = <&gpio0 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			zephyr,code = <INPUT_KEY_1>;
+			status = "disabled";
+		};
+	};
+
+	/*
+	 * This node describes the GPIO pins of the LCD-PAR-S035 panel 8080 interface.
+	 */
+	nxp_lcd_8080_connector: lcd-8080-connector {
+		compatible = "nxp,lcd-8080";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map =	<9  0 &gpio4 6 0>,	/* Pin 9, LCD touch INT */
+				<10  0 &gpio1 11 0>,	/* Pin 10, LCD backlight control */
+				<11  0 &gpio4 7 0>;	/* Pin 11, LCD and touch reset */
+	};
+};
+
+&flexcomm1_lpspi1 {
+	pinctrl-0 = <&pinmux_flexcomm1_lpspi>;
+	pinctrl-names = "default";
+};
+
+nxp_8080_touch_panel_i2c: &flexcomm2_lpi2c2 {
+	pinctrl-0 = <&pinmux_flexcomm2_lpi2c>;
+	pinctrl-names = "default";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+};
+
+&flexcomm2_lpuart2 {
+	current-speed = <115200>;
+	pinctrl-0 = <&pinmux_flexcomm2_lpuart>;
+	pinctrl-names = "default";
+};
+
+&flexcomm4_lpuart4 {
+	current-speed = <115200>;
+	pinctrl-0 = <&pinmux_flexcomm4_lpuart>;
+	pinctrl-names = "default";
+};
+
+&flexcomm3_lpi2c3 {
+	pinctrl-0 = <&pinmux_flexcomm3_lpi2c>;
+	pinctrl-names = "default";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+};
+
+/*
+ * MCXN947 board uses OS timer as the kernel timer
+ * In case we need to switch to SYSTICK timer, then
+ * replace &os_timer with &systick
+ */
+&os_timer {
+	status = "disabled";
+};
+
+&systick {
+	status = "okay";
+};
+
+&sram {
+	sramg: memory@20050000 {
+		compatible = "mmio-sram";
+		reg = <0x20050000 DT_SIZE_K(64)>;
+	};
+	sramh: memory@20060000 {
+		compatible = "mmio-sram";
+		reg = <0x20060000 DT_SIZE_K(32)>;
+	};
+};
+
+&flash {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/*
+		 * Partition sizes must be aligned
+		 * to the flash memory sector size of 8KB.
+		 */
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x00000000 DT_SIZE_K(80)>;
+		};
+		/* For the MCUBoot "upgrade only" method,
+		 * the slot sizes must be equal.
+		 */
+		slot0_partition: partition@14000 {
+			label = "image-0";
+			reg = <0x00014000 DT_SIZE_K(984)>;
+		};
+		slot1_partition: partition@10A000 {
+			label = "image-1";
+			reg = <0x0010A000 DT_SIZE_K(984)>;
+		};
+		/* storage_partition is placed in WINBOND flash memory*/
+	};
+};
+
+&flexspi {
+	pinctrl-0 = <&pinmux_flexspi>;
+	pinctrl-names = "default";
+	ahb-prefetch;
+	ahb-bufferable;
+	ahb-cacheable;
+	ahb-read-addr-opt;
+	combination-mode;
+	rx-clock-source = <1>;
+
+	/* WINBOND flash memory*/
+	w25q64jwtbjq: w25q64jwtbjq@0 {
+		compatible = "nxp,imx-flexspi-nor";
+		status = "disabled";
+		size = <67108864>;
+		reg = <0>;
+		spi-max-frequency = <133000000>;
+		jedec-id = [ef 40 17];
+		erase-block-size = <4096>;
+		write-block-size = <1>;
+		cs-interval-unit = <1>;
+		cs-interval = <2>;
+		cs-hold-time = <3>;
+		cs-setup-time = <3>;
+		data-valid-time = <2>;
+		column-space = <0>;
+	};
+};
+
+&dac0 {
+	pinctrl-0 = <&pinmux_dac0>;
+	pinctrl-names = "default";
+};
+
+&sai1 {
+	pinctrl-0 = <&pinmux_sai1>;
+	pinctrl-names = "default";
+};
+
+&enet {
+	pinctrl-0 = <&pinmux_enet_qos>;
+	pinctrl-names = "default";
+};
+
+&enet_mac {
+	phy-connection-type = "rmii";
+	zephyr,random-mac-address;
+	phy-handle = <&phy>;
+};
+
+&enet_mdio {
+	phy: ethernet-phy@0 {
+		compatible = "ethernet-phy";
+		reg = <0>;
+		status = "okay";
+	};
+};
+
+&flexpwm1_pwm0 {
+	pinctrl-0 = <&pinmux_flexpwm1_pwm0>;
+	pinctrl-names = "default";
+};
+
+&usdhc0 {
+	pinctrl-0 = <&pinmux_usdhc0>;
+	pinctrl-1 = <&pinmux_usdhc0>;
+	pinctrl-2 = <&pinmux_usdhc0>;
+	cd-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
+	pwr-gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
+	pinctrl-names = "default", "slow", "med";
+	no-1-8-v;
+};
+
+&lpadc0 {
+	pinctrl-0 = <&pinmux_lpadc0>;
+	pinctrl-names = "default";
+};
+
+zephyr_mipi_dbi_parallel: &flexio0_lcd {
+	/* DMA channels 0, muxed to FlexIO TX */
+	dmas = <&edma0 0 61>;
+	dma-names = "tx";
+	shifters-count = <8>;
+	timers-count = <1>;
+	enwr-pin = <1>;
+	rd-pin = <0>;
+	data-pin-start = <16>;
+	reset-gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>;
+	cs-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+	rs-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
+	pinctrl-0 = <&pinmux_flexio_lcd>;
+	pinctrl-names = "default";
+};
+
+&lpcmp2 {
+	pinctrl-0 = <&pinmux_lpcmp2>;
+	pinctrl-names = "default";
+};
+
+&i3c1 {
+	pinctrl-0 = <&pinmux_i3c1>;
+	pinctrl-names = "default";
+};
+
+&flexcan0 {
+	pinctrl-0 = <&pinmux_flexcan0>;
+	pinctrl-names = "default";
+};
+
+&sc_timer {
+	pinctrl-0 = <&pinmux_sctimer>;
+	pinctrl-names = "default";
+};

boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0.dts

@@ -0,0 +1,14 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include "mcx_n9xx_evk_mcxn947_cpu0.dtsi"
+
+/ {
+	model = "NXP MCX-N9XX-EVK board";
+	compatible = "nxp,mcxn947", "nxp,mcx";
+};

boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0.dtsi

@@ -0,0 +1,243 @@
+/*
+ * Copyright 2024-2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Common dts file to enable supported features for CPU 0.
+ * This file is included by both the default variant
+ * which is run from internal flash and the QSPI variant.
+ */
+/dts-v1/;
+
+#include <nxp/nxp_mcxn94x.dtsi>
+#include "mcx_n9xx_evk.dtsi"
+
+/ {
+	cpus {
+		/delete-node/ cpu@1;
+	};
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash;
+		zephyr,flash-controller = &fmu;
+		zephyr,code-partition = &slot0_partition;
+		zephyr,uart-mcumgr = &flexcomm4_lpuart4;
+		zephyr,console = &flexcomm4_lpuart4;
+		zephyr,shell-uart = &flexcomm4_lpuart4;
+		zephyr,canbus = &flexcan0;
+		zephyr,code-cpu1-partition = &slot1_partition;
+	};
+
+	aliases{
+		watchdog0 = &wwdt0;
+		pwm-0 = &flexpwm1_pwm0;
+		pwm-1 = &sc_timer;
+		rtc = &rtc;
+	};
+};
+
+/*
+ * Default for this board is to allocate SRAM0-5 to cpu0 but the
+ * application can have an application specific device tree to
+ * allocate the SRAM0-7 differently.
+ *
+ * For example, SRAM0-6 could be allocated to cpu0 with only SRAM7
+ * for cpu1. This would require the value of sram0 to have a DT_SIZE_K
+ * of 384. You would have to make updates to cpu1 sram settings as well.
+ */
+&sram0 {
+	compatible = "mmio-sram";
+	reg = <0x20000000 DT_SIZE_K(320)>;
+};
+
+&mbox {
+	status = "okay";
+};
+
+&gpio4 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpio3 {
+	status = "okay";
+};
+
+&green_led {
+	status = "okay";
+};
+
+&red_led {
+	status = "okay";
+};
+
+&user_button_2 {
+	status = "okay";
+};
+
+&edma0 {
+	status = "okay";
+};
+
+&flexcomm1 {
+	status = "okay";
+};
+
+&flexcomm1_lpspi1 {
+	status = "okay";
+};
+
+&flexcomm2 {
+	status = "okay";
+};
+
+&flexcomm2_lpi2c2 {
+	status = "okay";
+};
+
+/*
+ *LPFLEXCOMM supports UART and I2C on the same instance, enable this for
+ * LFLEXCOMM2
+ */
+&flexcomm2_lpuart2 {
+	status = "okay";
+};
+
+&flexcomm4 {
+	status = "okay";
+};
+
+&flexcomm4_lpuart4 {
+	status = "okay";
+};
+
+&flexcomm3 {
+	status = "okay";
+};
+
+&flexcomm3_lpi2c3 {
+	status = "okay";
+};
+
+&flexspi {
+	status = "okay";
+};
+
+&w25q64jwtbjq {
+	status = "okay";
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		storage_partition: partition@0 {
+			label = "storage";
+			reg = <0x0 DT_SIZE_M(8)>;
+		};
+	};
+};
+
+&dac0 {
+	status = "okay";
+};
+
+&enet {
+	status = "okay";
+};
+
+&enet_mac {
+	status = "okay";
+};
+
+&enet_mdio {
+	status = "okay";
+};
+
+&wwdt0 {
+	status = "okay";
+};
+
+&flexpwm1_pwm0 {
+	status = "okay";
+};
+
+&flexcan0 {
+	status = "okay";
+};
+
+&ctimer0 {
+	status = "okay";
+};
+
+&usdhc0 {
+	status = "okay";
+	sdmmc {
+		compatible = "zephyr,sdmmc-disk";
+		disk-name = "SD";
+		status = "okay";
+	};
+};
+
+&vref {
+	status = "okay";
+};
+
+&lpadc0 {
+	status = "okay";
+};
+
+zephyr_udc0: &usb1 {
+	status = "okay";
+	phy-handle = <&usbphy1>;
+};
+
+&usbphy1 {
+	status = "okay";
+	tx-d-cal = <4>;
+	tx-cal-45-dp-ohms = <7>;
+	tx-cal-45-dm-ohms = <7>;
+};
+
+&lpcmp2 {
+	status = "okay";
+};
+
+&lptmr0 {
+	status = "okay";
+};
+
+&i3c1 {
+	status = "okay";
+};
+
+&flexio0 {
+	status = "okay";
+};
+
+&mrt0_channel0 {
+	status = "okay";
+};
+
+&rtc {
+	status = "okay";
+};
+
+&sc_timer {
+	status = "okay";
+};
+
+&sai1 {
+	status = "okay";
+};

boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0.yaml

@@ -0,0 +1,34 @@
+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+identifier: mcx_n9xx_evk/mcxn947/cpu0
+name: NXP MCX-N9XX-EVK (CPU0)
+type: mcu
+arch: arm
+ram: 320
+flash: 2048
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - adc
+  - can
+  - counter
+  - dac
+  - dma
+  - flash
+  - gpio
+  - i2c
+  - i2s
+  - i3c
+  - pwm
+  - regulator
+  - rtc
+  - sdhc
+  - spi
+  - usb_device
+  - watchdog
+vendor: nxp

boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0_defconfig

@@ -0,0 +1,17 @@
+#
+# Copyright 2024-2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_GPIO=y
+
+CONFIG_ARM_MPU=y
+CONFIG_HW_STACK_PROTECTION=y
+
+# Enable TrustZone-M
+CONFIG_TRUSTED_EXECUTION_SECURE=y

boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0_qspi.dts

@@ -0,0 +1,44 @@
+/*
+ * Copyright 2024-2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include "mcx_n9xx_evk_mcxn947_cpu0.dtsi"
+
+/delete-node/ &slot0_partition;
+/delete-node/ &slot1_partition;
+/delete-node/ &storage_partition;
+
+/ {
+	model = "NXP MCX-N9XX-EVK board, QSPI variant";
+	compatible = "nxp,mcxn947", "nxp,mcx";
+
+	chosen {
+		zephyr,flash = &w25q64jwtbjq;
+	};
+
+};
+
+&w25q64jwtbjq {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		slot0_partition: partition@0 {
+			label = "image-0";
+			reg = <0x00000000 DT_SIZE_M(3)>;
+		};
+		slot1_partition: partition@300000 {
+			label = "image-1";
+			reg = <0x00300000 DT_SIZE_M(3)>;
+		};
+		storage_partition: partition@600000 {
+			label = "storage";
+			reg = <0x00600000 DT_SIZE_M(2)>;
+		};
+	};
+};

boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0_qspi.yaml

@@ -0,0 +1,32 @@
+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+identifier: mcx_n9xx_evk/mcxn947/cpu0/qspi
+name: NXP MCX-N9XX-EVK QSPI (CPU0)
+type: mcu
+arch: arm
+ram: 320
+flash: 8192
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - adc
+  - can
+  - counter
+  - dac
+  - dma
+  - flash
+  - gpio
+  - i2c
+  - i3c
+  - pwm
+  - regulator
+  - sdhc
+  - spi
+  - usb_device
+  - watchdog
+vendor: nxp

boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0_qspi_defconfig

@@ -0,0 +1,17 @@
+#
+# Copyright 2024-2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_GPIO=y
+
+CONFIG_ARM_MPU=y
+CONFIG_HW_STACK_PROTECTION=y
+
+# Enable TrustZone-M
+CONFIG_TRUSTED_EXECUTION_SECURE=y

boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu1.dts

@@ -0,0 +1,76 @@
+/*
+ * Copyright 2024-2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nxp/nxp_mcxn94x.dtsi>
+#include "mcx_n9xx_evk.dtsi"
+
+/ {
+	model = "NXP MCX-N9XX-EVK board";
+	compatible = "nxp,mcxn947", "nxp,mcx";
+
+	cpus {
+		/delete-node/ cpu@0;
+	};
+
+	chosen {
+		zephyr,sram = &sramg;
+		zephyr,flash = &flash;
+		zephyr,flash-controller = &fmu;
+		zephyr,code-partition = &slot1_partition;
+		zephyr,console = &flexcomm2_lpuart2;
+		zephyr,shell-uart = &flexcomm2_lpuart2;
+	};
+};
+
+&flexcomm2 {
+	status = "okay";
+};
+
+&flexcomm2_lpuart2 {
+	status = "okay";
+};
+
+&mbox {
+	status = "okay";
+};
+
+&gpio4 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpio3 {
+	status = "okay";
+};
+
+&green_led {
+	status = "okay";
+};
+
+&red_led {
+	status = "okay";
+};
+
+&user_button_2 {
+	status = "okay";
+};
+
+&edma0 {
+	status = "okay";
+};

boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu1.yaml

@@ -0,0 +1,19 @@
+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+identifier: mcx_n9xx_evk/mcxn947/cpu1
+name: NXP FRDM MCXN947 (CPU1)
+type: mcu
+arch: arm
+ram: 64
+flash: 200
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - dma
+  - gpio
+vendor: nxp

boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu1_defconfig

@@ -0,0 +1,13 @@
+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_GPIO=y
+
+CONFIG_USE_DT_CODE_PARTITION=y

samples/drivers/adc/adc_dt/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay

@@ -0,0 +1,50 @@
+/*
+ * Copyright 2024-2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/adc/adc.h>
+#include <zephyr/dt-bindings/adc/mcux-lpadc.h>
+
+/ {
+	zephyr,user {
+		/* adjust channel number according to pinmux in board.dts */
+		io-channels = <&lpadc0 0>, <&lpadc0 1>;
+	};
+};
+
+&lpadc0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	/*
+	 * To use this sample:
+	 * LPADC0 CH1A and CH1B are set up in differential mode (B-A)
+	 * - Connect LPADC0 CH1A signal to voltage between 0~1.8V (J20 pin 20)
+	 * - Connect LPADC0 CH1B signal to voltage between 0~1.8V (J20 pin 24)
+	 * LPADC0 CH2A is set up in single ended mode
+	 * - Connect LPADC0 CH2A signal to voltage between 0~1.8V (J20 pin 28)
+	 */
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_EXTERNAL1";
+		zephyr,vref-mv = <1800>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <13>;
+		zephyr,input-positive = <MCUX_LPADC_CH1B>;
+		zephyr,input-negative = <MCUX_LPADC_CH1A>;
+	};
+
+	channel@1 {
+		reg = <1>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_EXTERNAL1";
+		zephyr,vref-mv = <1800>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+		zephyr,input-positive = <MCUX_LPADC_CH2A>;
+	};
+};

samples/drivers/adc/adc_dt/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.overlay

@@ -0,0 +1,50 @@
+/*
+ * Copyright 2024-2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/adc/adc.h>
+#include <zephyr/dt-bindings/adc/mcux-lpadc.h>
+
+/ {
+	zephyr,user {
+		/* adjust channel number according to pinmux in board.dts */
+		io-channels = <&lpadc0 0>, <&lpadc0 1>;
+	};
+};
+
+&lpadc0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	/*
+	 * To use this sample:
+	 * LPADC0 CH1A and CH1B are set up in differential mode (B-A)
+	 * - Connect LPADC0 CH1A signal to voltage between 0~1.8V (J20 pin 20)
+	 * - Connect LPADC0 CH1B signal to voltage between 0~1.8V (J20 pin 24)
+	 * LPADC0 CH2A is set up in single ended mode
+	 * - Connect LPADC0 CH2A signal to voltage between 0~1.8V (J20 pin 28)
+	 */
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_EXTERNAL1";
+		zephyr,vref-mv = <1800>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <13>;
+		zephyr,input-positive = <MCUX_LPADC_CH1B>;
+		zephyr,input-negative = <MCUX_LPADC_CH1A>;
+	};
+
+	channel@1 {
+		reg = <1>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_EXTERNAL1";
+		zephyr,vref-mv = <1800>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+		zephyr,input-positive = <MCUX_LPADC_CH2A>;
+	};
+};

samples/drivers/adc/adc_dt/sample.yaml

@@ -34,6 +34,7 @@ tests:
       - longan_nano/gd32vf103/lite
       - rd_rw612_bga
       - frdm_mcxn947/mcxn947/cpu0
+      - mcx_n9xx_evk/mcxn947/cpu0
       - frdm_mcxc242
       - ucans32k1sic
       - xg24_rb4187c

samples/drivers/dac/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay

@@ -0,0 +1,17 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+
+	/*
+	 * Please note on the MCX-N9XX-EVK board, DAC0 output signal port is J1-4.
+	 */
+	zephyr,user {
+		dac = <&dac0>;
+		dac-channel-id = <0>;
+		dac-resolution = <12>;
+	};
+};

samples/drivers/dac/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.overlay

@@ -0,0 +1,17 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+
+	/*
+	 * Please note on the MCX-N9XX-EVK board, DAC0 output signal port is J1-4.
+	 */
+	zephyr,user {
+		dac = <&dac0>;
+		dac-channel-id = <0>;
+		dac-resolution = <12>;
+	};
+};

samples/drivers/display/sample.yaml

@@ -107,6 +107,7 @@ tests:
       - platform:mimxrt1050_evk/mimxrt1052:SHIELD=rk043fn66hs_ctg
       - platform:mimxrt1040_evk/mimxrt1042:SHIELD=rk043fn66hs_ctg
       - platform:frdm_mcxn947/mcxn947/cpu0:SHIELD=lcd_par_s035_8080
+      - platform:mcx_n9xx_evk/mcxn947/cpu0:SHIELD=lcd_par_s035_8080
       - platform:frdm_mcxn236/mcxn236:SHIELD=lcd_par_s035_8080
       - platform:frdm_mcxa156/mcxa156:SHIELD=lcd_par_s035_8080
       - platform:frdm_rw612:SHIELD=lcd_par_s035_spi

samples/drivers/mbox/CMakeLists.txt

@@ -20,6 +20,7 @@ if(CONFIG_BOARD_NRF5340DK_NRF5340_CPUAPP OR
    CONFIG_BOARD_MIMXRT1180_EVK_MIMXRT1189_CM33 OR
    CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU0 OR
    CONFIG_BOARD_FRDM_MCXN947_MCXN947_CPU0 OR
+   CONFIG_BOARD_MCX_N9XX_EVK_MCXN947_CPU0 OR
    CONFIG_BOARD_ESP32_DEVKITC_WROOM_ESP32_PROCPU OR
    CONFIG_BOARD_ESP32S3_DEVKITM_ESP32S3_PROCPU OR
    CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUAPP OR

samples/drivers/mbox/Kconfig.sysbuild

@@ -17,6 +17,7 @@ config REMOTE_BOARD
 	default "mimxrt1180_evk/mimxrt1189/cm7" if $(BOARD) = "mimxrt1180_evk"
 	default "lpcxpresso55s69/lpc55s69/cpu1" if $(BOARD) = "lpcxpresso55s69"
 	default "frdm_mcxn947/mcxn947/cpu1" if $(BOARD) = "frdm_mcxn947"
+	default "mcx_n9xx_evk/mcxn947/cpu1" if $(BOARD) = "mcx_n9xx_evk"
 	default "nrf54h20dk/nrf54h20/cpuapp" if "$(BOARD)${BOARD_QUALIFIERS}" = "nrf54h20dk/nrf54h20/cpurad"
 	default "nrf54l09pdk/nrf54l09/cpuflpr" if $(BOARD) = "nrf54l09pdk"
 	default "nrf54l15dk/nrf54l15/cpuflpr" if $(BOARD) = "nrf54l15dk"

samples/drivers/mbox/boards/mcx_n9xx_evk_mcxn947_cpu0.conf

@@ -0,0 +1 @@
+CONFIG_SECOND_CORE_MCUX=y

samples/drivers/mbox/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay

@@ -0,0 +1,13 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	mbox-consumer {
+		compatible = "vnd,mbox-consumer";
+		mboxes = <&mbox 1>, <&mbox 0>;
+		mbox-names = "tx", "rx";
+	};
+};

samples/drivers/mbox/remote/CMakeLists.txt

@@ -18,6 +18,7 @@ if(CONFIG_BOARD_NRF5340DK_NRF5340_CPUNET OR
    CONFIG_BOARD_MIMXRT1180_EVK_MIMXRT1189_CM7 OR
    CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU1 OR
    CONFIG_BOARD_FRDM_MCXN947_MCXN947_CPU1 OR
+   CONFIG_BOARD_MCX_N9XX_EVK_MCXN947_CPU1 OR
    CONFIG_BOARD_ESP32_DEVKITC_WROOM_ESP32_APPCPU OR
    CONFIG_BOARD_ESP32S3_DEVKITM_ESP32S3_APPCPU OR
    CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUPPR OR

samples/drivers/mbox/remote/boards/mcx_n9xx_evk_mcxn947_cpu1.conf

@@ -0,0 +1 @@
+CONFIG_SECOND_CORE_MCUX=y

samples/drivers/mbox/remote/boards/mcx_n9xx_evk_mcxn947_cpu1.overlay

@@ -0,0 +1,13 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	mbox-consumer {
+		compatible = "vnd,mbox-consumer";
+		mboxes = <&mbox 0>, <&mbox 1>;
+		mbox-names = "tx", "rx";
+	};
+};

samples/drivers/mbox_data/CMakeLists.txt

@@ -12,6 +12,7 @@ set(REMOTE_ZEPHYR_DIR ${CMAKE_CURRENT_BINARY_DIR}/../remote/zephyr)
 if(CONFIG_BOARD_MIMXRT1170_EVK_MIMXRT1176_CM7 OR
    CONFIG_BOARD_MIMXRT1160_EVK_MIMXRT1166_CM7 OR
    CONFIG_BOARD_FRDM_MCXN947_MCXN947_CPU0 OR
+   CONFIG_BOARD_MCX_N9XX_EVK_MCXN947_CPU0 OR
    CONFIG_BOARD_MIMXRT1180_EVK_MIMXRT1189_CM33 OR
    CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU0)
   message(STATUS "${BOARD}${BOARD_QUALIFIERS} compile as Main in this sample")

samples/drivers/mbox_data/Kconfig.sysbuild

@@ -12,3 +12,4 @@ string
 	default "mimxrt1180_evk/mimxrt1189/cm7" if $(BOARD) = "mimxrt1180_evk"
 	default "lpcxpresso55s69/lpc55s69/cpu1" if $(BOARD) = "lpcxpresso55s69"
 	default "frdm_mcxn947/mcxn947/cpu1" if $(BOARD) = "frdm_mcxn947"
+	default "mcx_n9xx_evk/mcxn947/cpu1" if $(BOARD) = "mcx_n9xx_evk"

samples/drivers/mbox_data/boards/mcx_n9xx_evk_mcxn947_cpu0.conf

@@ -0,0 +1 @@
+CONFIG_SECOND_CORE_MCUX=y

samples/drivers/mbox_data/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay

@@ -0,0 +1,13 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	mbox-consumer {
+		compatible = "vnd,mbox-consumer";
+		mboxes = <&mbox 1>, <&mbox 0>;
+		mbox-names = "tx", "rx";
+	};
+};

samples/drivers/mbox_data/remote/CMakeLists.txt

@@ -10,6 +10,7 @@ find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
 if(CONFIG_BOARD_MIMXRT1170_EVK_MIMXRT1176_CM4 OR
    CONFIG_BOARD_MIMXRT1160_EVK_MIMXRT1166_CM4 OR
    CONFIG_BOARD_FRDM_MCXN947_MCXN947_CPU1 OR
+   CONFIG_BOARD_MCX_N9XX_EVK_MCXN947_CPU1 OR
    CONFIG_BOARD_MIMXRT1180_EVK_MIMXRT1189_CM7 OR
    CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU1)
   message(STATUS "${BOARD}${BOARD_QUALIFIERS} compile as remote in this sample")

samples/drivers/mbox_data/remote/boards/mcx_n9xx_evk_mcxn947_cpu1.conf

@@ -0,0 +1 @@
+CONFIG_SECOND_CORE_MCUX=y

samples/drivers/mbox_data/remote/boards/mcx_n9xx_evk_mcxn947_cpu1.overlay

@@ -0,0 +1,13 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	mbox-consumer {
+		compatible = "vnd,mbox-consumer";
+		mboxes = <&mbox 0>, <&mbox 1>;
+		mbox-names = "tx", "rx";
+	};
+};

samples/sensor/mcux_lpcmp/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay

@@ -0,0 +1,14 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Sample requires node labeled lpcmp0, map to lpcmp2
+ * Apply input voltage to LPCMP on header J1-pin 14 (P1_2)
+ */
+/delete-node/ &lpcmp0;
+lpcmp0: &lpcmp2 {
+	function-clock = "CMP_CLOCK";
+};

samples/sensor/mcux_lpcmp/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.overlay

@@ -0,0 +1,14 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Sample requires node labeled lpcmp0, map to lpcmp2
+ * Apply input voltage to LPCMP on header J1-pin 14 (P1_2)
+ */
+/delete-node/ &lpcmp0;
+lpcmp0: &lpcmp2 {
+	function-clock = "CMP_CLOCK";
+};

samples/sensor/mcux_lpcmp/sample.yaml

@@ -4,6 +4,7 @@ sample:
 common:
   platform_allow:
     - frdm_mcxn947/mcxn947/cpu0
+    - mcx_n9xx_evk/mcxn947/cpu0
     - frdm_mcxn236
     - frdm_mcxa156
   integration_platforms:

samples/sensor/thermometer/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay

@@ -0,0 +1,27 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <freq.h>
+
+/ {
+	aliases {
+		ambient-temp0 = &p3t1755;
+	};
+};
+
+&i3c1 {
+	status = "okay";
+
+	i2c-scl-hz = <DT_FREQ_K(400)>;
+	i3c-scl-hz = <DT_FREQ_M(4)>;
+	i3c-od-scl-hz = <DT_FREQ_K(1500)>;
+
+	p3t1755: p3t1755@4800000236152a0090 {
+		compatible = "nxp,p3t1755";
+		reg = <0x48 0x0236 0x152a0090>;
+		status = "okay";
+	};
+};

samples/sensor/thermometer/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.overlay

@@ -0,0 +1,27 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <freq.h>
+
+/ {
+	aliases {
+		ambient-temp0 = &p3t1755;
+	};
+};
+
+&i3c1 {
+	status = "okay";
+
+	i2c-scl-hz = <DT_FREQ_K(400)>;
+	i3c-scl-hz = <DT_FREQ_M(4)>;
+	i3c-od-scl-hz = <DT_FREQ_K(1500)>;
+
+	p3t1755: p3t1755@4800000236152a0090 {
+		compatible = "nxp,p3t1755";
+		reg = <0x48 0x0236 0x152a0090>;
+		status = "okay";
+	};
+};

samples/subsys/ipc/ipc_service/static_vrings/CMakeLists.txt

@@ -19,6 +19,7 @@ if(NOT (CONFIG_BOARD_NRF5340DK_NRF5340_CPUAPP OR
         CONFIG_BOARD_MIMXRT1160_EVK_MIMXRT1166_CM7 OR
         CONFIG_BOARD_MIMXRT1170_EVK_MIMXRT1176_CM7 OR
         CONFIG_BOARD_FRDM_MCXN947_MCXN947_CPU0 OR
+        CONFIG_BOARD_MCX_N9XX_EVK_MCXN947_CPU0 OR
         CONFIG_BOARD_MIMXRT1180_EVK_MIMXRT1189_CM33
        )
   )

samples/subsys/ipc/ipc_service/static_vrings/Kconfig.sysbuild

@@ -14,4 +14,5 @@ string
 	default "mimxrt1170_evk/mimxrt1176/cm4" if $(BOARD) = "mimxrt1170_evk"
 	default "mimxrt1170_evkb/mimxrt1176/cm4" if $(BOARD) = "mimxrt1170_evkb"
 	default "frdm_mcxn947/mcxn947/cpu1" if $(BOARD) = "frdm_mcxn947"
+	default "mcx_n9xx_evk/mcxn947/cpu1" if $(BOARD) = "mcx_n9xx_evk"
 	default "mimxrt1180_evk/mimxrt1189/cm7" if $(BOARD) = "mimxrt1180_evk"

samples/subsys/ipc/ipc_service/static_vrings/boards/mcx_n9xx_evk_mcxn947_cpu0.conf

@@ -0,0 +1 @@
+CONFIG_SECOND_CORE_MCUX=y

samples/subsys/ipc/ipc_service/static_vrings/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay

@@ -0,0 +1,51 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/ipc_service/static_vrings.h>
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+
+/ {
+	/* Define memory regions for IPC
+	 * Note that shared memory must have specific MPU attributes set.
+	 */
+	sram1_ipc0: memory@20060000{
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x20060000 DT_SIZE_K(16)>;
+		zephyr,memory-region="SRAM1_IPC0";
+		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO))>;
+	};
+
+	sram1_ipc1: memory@20064000{
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x20064000 DT_SIZE_K(16)>;
+		zephyr,memory-region="SRAM1_IPC1";
+		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO))>;
+	};
+
+	ipc {
+		/delete-node/ ipc0;
+
+		ipc0: ipc0 {
+			compatible = "zephyr,ipc-openamp-static-vrings";
+			memory-region = <&sram1_ipc0>;
+			mboxes = <&mbox 0>, <&mbox 1>;
+			mbox-names = "tx", "rx";
+			role = "host";
+			status = "okay";
+		};
+
+		ipc1: ipc1 {
+			compatible = "zephyr,ipc-openamp-static-vrings";
+			memory-region = <&sram1_ipc1>;
+			mboxes = <&mbox 2>, <&mbox 3>;
+			mbox-names = "tx", "rx";
+			role = "host";
+			zephyr,priority = <1 PRIO_COOP>;
+			zephyr,buffer-size = <128>;
+			status = "okay";
+		};
+	};
+};

samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mcx_n9xx_evk_mcxn947_cpu1.conf

@@ -0,0 +1 @@
+CONFIG_SECOND_CORE_MCUX=y

samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mcx_n9xx_evk_mcxn947_cpu1.overlay

@@ -0,0 +1,51 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/ipc_service/static_vrings.h>
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+
+/ {
+	/* Define memory regions for IPC
+	 * Note that shared memory must have specific MPU attributes set.
+	 */
+	 sram1_ipc0: memory@20060000{
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x20060000 DT_SIZE_K(16)>;
+		zephyr,memory-region="SRAM1_IPC0";
+		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO))>;
+	};
+
+	sram1_ipc1: memory@20064000{
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x20064000 DT_SIZE_K(16)>;
+		zephyr,memory-region="SRAM1_IPC1";
+		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO))>;
+	};
+
+	ipc {
+		/delete-node/ ipc0;
+
+		ipc0: ipc0 {
+			compatible = "zephyr,ipc-openamp-static-vrings";
+			memory-region = <&sram1_ipc0>;
+			mboxes = <&mbox 0>, <&mbox 1>;
+			mbox-names = "rx", "tx";
+			role = "remote";
+			status = "okay";
+		};
+
+		ipc1: ipc1 {
+			compatible = "zephyr,ipc-openamp-static-vrings";
+			memory-region = <&sram1_ipc1>;
+			mboxes = <&mbox 2>, <&mbox 3>;
+			mbox-names = "rx", "tx";
+			role = "remote";
+			zephyr,priority = <1 PRIO_COOP>;
+			zephyr,buffer-size = <128>;
+			status = "okay";
+		};
+	};
+};

samples/subsys/ipc/openamp/Kconfig.sysbuild

@@ -14,4 +14,5 @@ string
 	default "mimxrt1160_evk/mimxrt1166/cm4" if $(BOARD) = "mimxrt1160_evk"
 	default "mimxrt1170_evkb/mimxrt1176/cm4" if $(BOARD) = "mimxrt1170_evkb"
 	default "frdm_mcxn947/mcxn947/cpu1" if $(BOARD) = "frdm_mcxn947"
+	default "mcx_n9xx_evk/mcxn947/cpu1" if $(BOARD) = "mcx_n9xx_evk"
 	default "mimxrt1180_evk/mimxrt1189/cm7" if $(BOARD) = "mimxrt1180_evk"

samples/subsys/ipc/openamp/boards/mcx_n9xx_evk_mcxn947_cpu0.conf

@@ -0,0 +1 @@
+CONFIG_SECOND_CORE_MCUX=y

samples/subsys/ipc/openamp/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay

@@ -0,0 +1,28 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	chosen {
+		/*
+		 * shared memory reserved for the inter-processor communication
+		 */
+
+		zephyr,ipc_shm = &sramh;
+		zephyr,ipc = &mailbox0;
+	};
+
+	/* Delete MBOX Driver node */
+	/delete-node/ mbox@b2000;
+	soc {
+		mailbox0:mailbox@400b2000 {
+			compatible = "nxp,lpc-mailbox";
+			reg = <0x400b2000 0xEC>;
+			interrupts = <54 0>;
+			resets = <&reset NXP_SYSCON_RESET(0, 26)>;
+			status = "okay";
+		};
+	};
+};

samples/subsys/ipc/openamp/remote/boards/mcx_n9xx_evk_mcxn947_cpu1.conf

@@ -0,0 +1 @@
+CONFIG_SECOND_CORE_MCUX=y

samples/subsys/ipc/openamp/remote/boards/mcx_n9xx_evk_mcxn947_cpu1.overlay

@@ -0,0 +1,28 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	chosen {
+		/*
+		 * shared memory reserved for the inter-processor communication
+		 */
+
+		zephyr,ipc_shm = &sramh;
+		zephyr,ipc = &mailbox0;
+	};
+
+	/* Delete MBOX Driver node */
+	/delete-node/ mbox@b2000;
+	soc {
+		mailbox0:mailbox@400b2000 {
+			compatible = "nxp,lpc-mailbox";
+			reg = <0x400b2000 0xEC>;
+			interrupts = <54 0>;
+			resets = <&reset NXP_SYSCON_RESET(0, 26)>;
+			status = "okay";
+		};
+	};
+};

samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml

@@ -33,6 +33,7 @@ tests:
     extra_args: EXTRA_CONF_FILE="overlay-udp.conf"
     platform_allow:
       - frdm_mcxn947/mcxn947/cpu0
+      - mcx_n9xx_evk/mcxn947/cpu0
       - frdm_k64f
     integration_platforms:
       - frdm_k64f
@@ -42,6 +43,7 @@ tests:
       - DTC_OVERLAY_FILE="usb.overlay"
     platform_allow:
       - frdm_mcxn947/mcxn947/cpu0
+      - mcx_n9xx_evk/mcxn947/cpu0
       - nrf52833dk/nrf52820
       - nrf52833dk/nrf52833
       - nrf52840dk/nrf52840
@@ -64,6 +66,7 @@ tests:
       - twr_ke18f
       - twr_kv58f220m
       - frdm_mcxn947/mcxn947/cpu0
+      - mcx_n9xx_evk/mcxn947/cpu0
       - lpcxpresso55s06
       - lpcxpresso55s16
       - lpcxpresso55s28
@@ -123,6 +126,7 @@ tests:
       - twr_ke18f
       - twr_kv58f220m
       - frdm_mcxn947/mcxn947/cpu0
+      - mcx_n9xx_evk/mcxn947/cpu0
       - lpcxpresso55s06
       - lpcxpresso55s16
       - lpcxpresso55s28

tests/boot/test_mcuboot/testcase.yaml

@@ -21,6 +21,7 @@ tests:
       - rddrone_fmuk66
       - twr_ke18f
       - frdm_mcxn947/mcxn947/cpu0
+      - mcx_n9xx_evk/mcxn947/cpu0
       - lpcxpresso55s06
       - lpcxpresso55s16
       - lpcxpresso55s28

tests/drivers/adc/adc_api/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay

@@ -0,0 +1,38 @@
+/*
+ * Copyright 2024 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/adc/adc.h>
+#include <zephyr/dt-bindings/adc/mcux-lpadc.h>
+
+/ {
+	zephyr,user {
+		io-channels = <&lpadc0 0>, <&lpadc0 1>;
+	};
+};
+
+&lpadc0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_EXTERNAL1";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+		zephyr,vref-mv = <1800>;
+		zephyr,input-positive = <MCUX_LPADC_CH1A>;
+	};
+
+	channel@1 {
+		reg = <1>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_EXTERNAL1";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+		zephyr,vref-mv = <1800>;
+		zephyr,input-positive = <MCUX_LPADC_CH2A>;
+	};
+};

tests/drivers/adc/adc_api/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.overlay

@@ -0,0 +1,36 @@
+/*
+ * Copyright 2024 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/adc/adc.h>
+#include <zephyr/dt-bindings/adc/mcux-lpadc.h>
+
+/ {
+	zephyr,user {
+		io-channels = <&lpadc0 0>, <&lpadc0 1>;
+	};
+};
+
+&lpadc0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_EXTERNAL1";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+		zephyr,input-positive = <MCUX_LPADC_CH1A>;
+	};
+
+	channel@1 {
+		reg = <1>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_EXTERNAL1";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+		zephyr,input-positive = <MCUX_LPADC_CH2A>;
+	};
+};

tests/drivers/can/timing/boards/mcx_n9xx_evk_mcxn947_cpu0.conf

@@ -0,0 +1 @@
+CONFIG_TEST_ALL_BITRATES=y

tests/drivers/can/timing/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.conf

@@ -0,0 +1 @@
+CONFIG_TEST_ALL_BITRATES=y

tests/drivers/dac/dac_api/src/test_dac.c

@@ -49,6 +49,7 @@
 	defined(CONFIG_BOARD_FRDM_K64F) || \
 	defined(CONFIG_BOARD_FRDM_K22F) || \
 	defined(CONFIG_BOARD_FRDM_MCXN947) || \
+	defined(CONFIG_BOARD_MCX_N9XX_EVK) || \
 	defined(CONFIG_BOARD_FRDM_MCXA156) || \
 	defined(CONFIG_BOARD_SEEEDUINO_XIAO) || \
 	defined(CONFIG_BOARD_ARDUINO_MKRZERO) || \

tests/drivers/i2c/i2c_target_api/boards/mcx_n9xx_evk_mcxn947_cpu0.conf

@@ -0,0 +1 @@
+CONFIG_I2C_VIRTUAL=n

tests/drivers/i2c/i2c_target_api/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay

@@ -0,0 +1,51 @@
+/*
+ * Copyright 2024-2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+&pinctrl {
+	pinmux_flexcomm1_lpi2c: pinmux_flexcomm1_lpi2c {
+		group0 {
+			pinmux = <FC1_P0_PIO0_24>,
+				<FC1_P1_PIO0_25>;
+			slew-rate = "fast";
+			drive-strength = "low";
+			input-enable;
+			bias-pull-up;
+			drive-open-drain;
+		};
+	};
+};
+
+&flexcomm1 {
+	status = "okay";
+};
+
+/* We cannot enable SPI and I2C on the same flexcomm */
+&flexcomm1_lpspi1 {
+	status = "disabled";
+};
+
+/* To test this sample, connect
+ * LPI2C1 SCL(J2-12, P0_25/FC1_P1)    -->        LPI2C2 SCL(J2-20, P4_1/FC2_P1)
+ * LPI2C1 SDA(J2-8, P0_24/FC1_P0)     -->        LPI2C2 SDA(J2-18, P4_0/FC2_P0)
+ */
+&flexcomm1_lpi2c1 {
+	pinctrl-0 = <&pinmux_flexcomm1_lpi2c>;
+	pinctrl-names = "default";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	status = "okay";
+	eeprom0: eeprom@54 {
+		compatible = "zephyr,i2c-target-eeprom";
+		reg = <0x54>;
+		size = <256>;
+	};
+};
+
+&flexcomm2_lpi2c2 {
+	eeprom1: eeprom@56 {
+		compatible = "zephyr,i2c-target-eeprom";
+		reg = <0x56>;
+		size = <256>;
+	};
+};

tests/drivers/i2c/i2c_target_api/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.conf

@@ -0,0 +1 @@
+CONFIG_I2C_VIRTUAL=n

tests/drivers/i2c/i2c_target_api/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.overlay

@@ -0,0 +1,51 @@
+/*
+ * Copyright 2024-2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+&pinctrl {
+	pinmux_flexcomm1_lpi2c: pinmux_flexcomm1_lpi2c {
+		group0 {
+			pinmux = <FC1_P0_PIO0_24>,
+				<FC1_P1_PIO0_25>;
+			slew-rate = "fast";
+			drive-strength = "low";
+			input-enable;
+			bias-pull-up;
+			drive-open-drain;
+		};
+	};
+};
+
+&flexcomm1 {
+	status = "okay";
+};
+
+/* We cannot enable SPI and I2C on the same flexcomm */
+&flexcomm1_lpspi1 {
+	status = "disabled";
+};
+
+/* To test this sample, connect
+ * LPI2C1 SCL(J2-12, P0_25/FC1_P1)    -->        LPI2C2 SCL(J2-20, P4_1/FC2_P1)
+ * LPI2C1 SDA(J2-8, P0_24/FC1_P0)     -->        LPI2C2 SDA(J2-18, P4_0/FC2_P0)
+ */
+&flexcomm1_lpi2c1 {
+	pinctrl-0 = <&pinmux_flexcomm1_lpi2c>;
+	pinctrl-names = "default";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	status = "okay";
+	eeprom0: eeprom@54 {
+		compatible = "zephyr,i2c-target-eeprom";
+		reg = <0x54>;
+		size = <1024>;
+	};
+};
+
+&flexcomm2_lpi2c2 {
+	eeprom1: eeprom@56 {
+		compatible = "zephyr,i2c-target-eeprom";
+		reg = <0x56>;
+		size = <1024>;
+	};
+};

tests/drivers/i2c/i2c_target_api/testcase.yaml

@@ -38,6 +38,7 @@ tests:
   drivers.i2c.target_api.single_role:
     platform_allow:
       - frdm_mcxn947/mcxn947/cpu0
+      - mcx_n9xx_evk/mcxn947/cpu0
       - mcxw72_evk/mcxw727c/cpu0
       - mimxrt1170_evk@B/mimxrt1176/cm7
       - mimxrt1170_evk/mimxrt1176/cm7

tests/drivers/i2s/i2s_api/testcase.yaml

@@ -7,6 +7,7 @@ tests:
     filter: not CONFIG_I2S_TEST_USE_GPIO_LOOPBACK
     platform_exclude:
       - frdm_mcxn947/mcxn947/cpu0
+      - mcx_n9xx_evk/mcxn947/cpu0
       - mimxrt595_evk/mimxrt595s/cm33
       - mimxrt685_evk/mimxrt685s/cm33
   drivers.i2s.gpio_loopback:
@@ -20,6 +21,7 @@ tests:
     harness: ztest
     platform_exclude:
       - frdm_mcxn947/mcxn947/cpu0
+      - mcx_n9xx_evk/mcxn947/cpu0
       - mimxrt595_evk/mimxrt595s/cm33
       - mimxrt685_evk/mimxrt685s/cm33
     harness_config:

tests/drivers/i2s/i2s_speed/Readme.txt

@@ -26,6 +26,15 @@ signals externally on the EVK.  These are the HW changes required to run this te
         - Short SYNC J1-pin13 (SAI1_RX_FS/P3_19)   to J3-pin13 (SAI0_TX_FS/P2_7)
         - Short Data J1-pin15 (SAI1_RXD0/P3_21)    to J3-pin7  (SAI0_TXD0/P2_2)
 
+MCX-N9XX-EVK:
+This board uses CONFIG_I2S_TEST_SEPARATE_DEVICES=n and connects TX and RX blocks in one
+SAI peripheral by shorting signals externally on the EVK.  These are the HW changes
+required to run this test:
+	- Populate JP16 and JP20
+	- Short BCLK JP20-pin3 (SAI1_RX_BCLK/P3_18) to JP20-pin1  (SAI1_TX_BCLK/P3_16)
+	- SHort SYNC JP16-pin3 (SAI1_RX_FS  /P3_19) to JP16-pin1  (SAI1_TX_FS  /P3_17)
+        - Short Data J20-pin14 (SAI1_RXD0   /P2_9)  to JP20-pin13 (SAI1_TXD0   /P2_8)
+
 MIMXRT1060-EVK[B/C]:
 This board uses a single SAI and connects the TX and RX signals by shorting externally on the EVK.
 These are the HW changes required to run this test on MIMXRT1060-EVK[B/C]:

tests/drivers/i2s/i2s_speed/boards/mcx_n9xx_evk_mcxn947_cpu0.conf

@@ -0,0 +1,25 @@
+#
+# Copyright (c) 2025, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+# SAI peripheral does not have loopback mode but we can connect CLK, SYNC,
+# RXD and TXD of one SAI for test purpose.
+CONFIG_I2S_TEST_SEPARATE_DEVICES=n
+
+# CONFIG_DMA_TCD_QUEUE_SIZE sets size of queue used to chain DMA blocks (TCDs)
+# together, and should be sized as needed by the application.  If not large
+# enough, the DMA may starve.  Symptoms of this issue include transmit blocks
+# repeated, or RX blocks skipped. For I2S driver, queue size must be at least 3.
+CONFIG_DMA_TCD_QUEUE_SIZE=4
+
+# Repeat test continually to help find intermittent issues
+CONFIG_ZTEST_RETEST_IF_PASSED=y
+
+# I2S and DMA logging can occur in interrupt context, and interfere with I2S
+# stream timing.  If using either logging, set logging to deferred
+# CONFIG_LOG_MODE_DEFERRED=y
+
+CONFIG_DMA_LOG_LEVEL_OFF=y
+CONFIG_I2S_LOG_LEVEL_OFF=y

tests/drivers/i2s/i2s_speed/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay

@@ -0,0 +1,23 @@
+/ {
+	aliases {
+		i2s-node0 = &sai1;
+	};
+};
+
+&sai1 {
+	mclk-output;
+};
+
+&pinmux_sai1 {
+	group0 {
+		pinmux = <SAI1_TX_BCLK_PIO3_16>,
+			<SAI1_TX_FS_PIO3_17>,
+			<SAI1_TXD0_PIO2_8>,
+			<SAI1_RX_FS_PIO3_19>,
+			<SAI1_RX_BCLK_PIO3_18>,
+			<SAI1_RXD0_PIO2_9>;
+		drive-strength = "high";
+		slew-rate = "fast";
+		input-enable;
+	};
+};

tests/drivers/pwm/pwm_api/boards/mcx_n9xx_evk_mcxn947_cpu0_sctimer.overlay

@@ -0,0 +1,12 @@
+/*
+ * Copyright 2024-2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Disable flexpwm node as it is mapped to pwm-0 alias which is picked up first by the test.
+ * PWM signal is visible on J3-7.
+ */
+&flexpwm1_pwm0 {
+	status = "disabled";
+};

tests/drivers/pwm/pwm_api/testcase.yaml

@@ -41,11 +41,13 @@ tests:
     extra_args: DTC_OVERLAY_FILE="boards/nrf54h20dk_nrf54h20_cpuapp_fast.overlay"
     platform_allow:
       - nrf54h20dk/nrf54h20/cpuapp
-  drivers.pwm.frdm_mcxn947_mcxn947_cpu0_sctimer:
+  drivers.pwm.mcxn947_cpu0_sctimer:
     extra_args: DTC_OVERLAY_FILE="boards/frdm_mcxn947_mcxn947_cpu0_sctimer.overlay"
     platform_allow:
       - frdm_mcxn947/mcxn947/cpu0
       - frdm_mcxn947/mcxn947/cpu0/qspi
+      - mcx_n9xx_evk/mcxn947/cpu0
+      - mcx_n9xx_evk/mcxn947/cpu0/qspi
   drivers.pwm.native_sim:
     platform_allow:
       - native_sim

tests/drivers/regulator/voltage/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay

@@ -0,0 +1,47 @@
+/*
+ * Copyright 2024-2025 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/adc/adc.h>
+#include <zephyr/dt-bindings/adc/mcux-lpadc.h>
+#include <zephyr/dt-bindings/regulator/nxp_vref.h>
+
+/* To do this test, connect LPADC0 channel 2A(J20 pin 28) to VREF_OUT (JP28-1) */
+
+/ {
+	resources: resources {
+		compatible = "test-regulator-voltage";
+		regulators = <&vref>;
+		tolerance-microvolt = <10000>;
+		set-read-delay-ms = <1>;
+		adc-avg-count = <10>;
+		io-channels = <&lpadc0 0>;
+		min-microvolt = <1000000>;
+		max-microvolt = <2100000>;
+	};
+};
+
+&vref {
+	regulator-initial-mode = <NXP_VREF_MODE_INTERNAL_REGULATOR>;
+};
+
+&lpadc0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	/* In this case, the LPADC reference source cannot be set to VREFO,
+	 * switch the reference source to VDD_ANA.
+	 */
+	voltage-ref= <2>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_EXTERNAL0";
+		zephyr,vref-mv = <3300>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+		zephyr,input-positive = <MCUX_LPADC_CH2A>;
+	};
+};

tests/drivers/regulator/voltage/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.overlay

@@ -0,0 +1,47 @@
+/*
+ * Copyright 2024-2025 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/adc/adc.h>
+#include <zephyr/dt-bindings/adc/mcux-lpadc.h>
+#include <zephyr/dt-bindings/regulator/nxp_vref.h>
+
+/* To do this test, connect LPADC0 channel 2A(J20 pin 28) to VREF_OUT (JP28-1) */
+
+/ {
+	resources: resources {
+		compatible = "test-regulator-voltage";
+		regulators = <&vref>;
+		tolerance-microvolt = <10000>;
+		set-read-delay-ms = <1>;
+		adc-avg-count = <10>;
+		io-channels = <&lpadc0 0>;
+		min-microvolt = <1000000>;
+		max-microvolt = <2100000>;
+	};
+};
+
+&vref {
+	regulator-initial-mode = <NXP_VREF_MODE_INTERNAL_REGULATOR>;
+};
+
+&lpadc0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	/* In this case, the LPADC reference source cannot be set to VREFO,
+	 * switch the reference source to VDD_ANA.
+	 */
+	voltage-ref= <2>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_EXTERNAL0";
+		zephyr,vref-mv = <3300>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+		zephyr,input-positive = <MCUX_LPADC_CH2A>;
+	};
+};

tests/drivers/regulator/voltage/testcase.yaml

@@ -20,6 +20,7 @@ tests:
       - mimxrt685_evk/mimxrt685s/cm33
       - lpcxpresso55s36
       - frdm_mcxn947/mcxn947/cpu0
+      - mcx_n9xx_evk/mcxn947/cpu0
     harness_config:
       fixture: gpio_loopback
   drivers.regulator.voltage.rpi_pico_vreg:

tests/drivers/spi/spi_loopback/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay

@@ -0,0 +1,19 @@
+/*
+ * Copyright 2024-2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Connect J2-10 and J2-8 */
+&flexcomm1_lpspi1 {
+	slow@0 {
+		compatible = "test-spi-loopback-slow";
+		reg = <0>;
+		spi-max-frequency = <500000>;
+	};
+	fast@0 {
+		compatible = "test-spi-loopback-fast";
+		reg = <0>;
+		spi-max-frequency = <16000000>;
+	};
+};

tests/drivers/spi/spi_loopback/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.overlay

@@ -0,0 +1,19 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Connect J2-10 and J2-8 */
+&flexcomm1_lpspi1 {
+	slow@0 {
+		compatible = "test-spi-loopback-slow";
+		reg = <0>;
+		spi-max-frequency = <500000>;
+	};
+	fast@0 {
+		compatible = "test-spi-loopback-fast";
+		reg = <0>;
+		spi-max-frequency = <16000000>;
+	};
+};

tests/drivers/uart/uart_async_api/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay

@@ -0,0 +1,9 @@
+/*
+ * Copyright 2024-2025 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * To test this sample connect P4_2(J1-4) to P4_3(J1-2)
+ */
+dut: &flexcomm2_lpuart2 {};

tests/drivers/uart/uart_async_api/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.overlay

@@ -0,0 +1,9 @@
+/*
+ * Copyright 2024 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * To test this sample connect P4_2(J1-4) to P4_3(J1-2)
+ */
+dut: &flexcomm2_lpuart2 {};