drivers: reset: Add MPFS MSS driver

Add driver for Microchip PolarFire SoC (MPFS) peripheral clock and soft
reset control.

Normally, the peripheral clocks and reset state are controlled by the
Hart Software Services (HSS) running on the Monitor processor.  As an
alternative to using HSS services, applications can now enable the reset
controller in a device tree overly, for example:

&reset {
  status = "okay";
};

&uart4 {
  resets = <&reset MSS_RESET_ID_MMUART4>;
};

Embedded the reset controller node in system controller node.

Signed-off-by: Frank Kühndel <frank.kuehndel@embedded-brains.de>
Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
Signed-off-by: Conor Paxton <conor.paxton@microchip.com>

drivers/reset/CMakeLists.txt

@@ -13,3 +13,4 @@ zephyr_library_sources_ifdef(CONFIG_RESET_NPCX reset_npcx.c)
 zephyr_library_sources_ifdef(CONFIG_RESET_NXP_SYSCON reset_lpc_syscon.c)
 zephyr_library_sources_ifdef(CONFIG_RESET_NXP_RSTCTL reset_nxp_rstctl.c)
 zephyr_library_sources_ifdef(CONFIG_RESET_MMIO reset_mmio.c)
+zephyr_library_sources_ifdef(CONFIG_RESET_MCHP_MSS reset_mchp_mss.c)

drivers/reset/Kconfig

@@ -37,5 +37,6 @@ rsource "Kconfig.npcx"
 rsource "Kconfig.lpc_syscon"
 rsource "Kconfig.nxp_rstctl"
 rsource "Kconfig.mmio"
+rsource "Kconfig.mchp_mss"
 
 endif # RESET

drivers/reset/Kconfig.mchp_mss

@@ -0,0 +1,9 @@
+# Copyright (c) 2025 Microchip Technology Inc
+# SPDX-License-Identifier: Apache-2.0
+
+config RESET_MCHP_MSS
+	bool "Microchip PolarFire SoC and PIC64GX reset driver"
+	depends on DT_HAS_MICROCHIP_MPFS_RESET_ENABLED
+	help
+	  This option enables the reset driver for Microchip's PolarFire SoC
+	  and PIC64GX platform.

drivers/reset/reset_mchp_mss.c

@@ -0,0 +1,93 @@
+/*
+ * Copyright (C) 2025 embedded brains GmbH & Co. KG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT microchip_mpfs_reset
+
+#include <zephyr/arch/cpu.h>
+#include <zephyr/device.h>
+#include <zephyr/drivers/reset.h>
+
+#define SUBBLK_CLOCK_CR_OFFSET 0x84U
+
+#define SOFT_RESET_CR_OFFSET 0x88U
+
+#define RESET_MSS_REG_BIT(id) ((id) & 0x1fU)
+
+/* Bit 17 is related to the FPGA, bits 30 and 31 are reserved */
+#define RESET_MSS_VALID_BITS 0x3ffdffffU
+
+struct reset_mss_config {
+	uintptr_t base;
+};
+
+static int reset_mss_status(const struct device *dev, uint32_t id, uint8_t *status)
+{
+	const struct reset_mss_config *config = dev->config;
+
+	/* Device is in reset if the clock is turned off or held in soft reset */
+	*status = sys_test_bit(config->base + SUBBLK_CLOCK_CR_OFFSET, RESET_MSS_REG_BIT(id)) == 0 ||
+		  sys_test_bit(config->base + SOFT_RESET_CR_OFFSET, RESET_MSS_REG_BIT(id) != 0);
+
+	return 0;
+}
+
+static int reset_mss_line_assert(const struct device *dev, uint32_t id)
+{
+	const struct reset_mss_config *config = dev->config;
+	unsigned int bit = RESET_MSS_REG_BIT(id);
+
+	if (!IS_BIT_SET(RESET_MSS_VALID_BITS, bit)) {
+		return -EINVAL;
+	}
+
+	/* Turn off clock */
+	sys_clear_bit(config->base + SUBBLK_CLOCK_CR_OFFSET, bit);
+
+	/* Hold in reset */
+	sys_set_bit(config->base + SOFT_RESET_CR_OFFSET, bit);
+
+	return 0;
+}
+
+static int reset_mss_line_deassert(const struct device *dev, uint32_t id)
+{
+	const struct reset_mss_config *config = dev->config;
+	unsigned int bit = RESET_MSS_REG_BIT(id);
+
+	if (!IS_BIT_SET(RESET_MSS_VALID_BITS, bit)) {
+		return -EINVAL;
+	}
+
+	/* Turn on clock */
+	sys_set_bit(config->base + SUBBLK_CLOCK_CR_OFFSET, bit);
+
+	/* Remove soft reset */
+	sys_clear_bit(config->base + SOFT_RESET_CR_OFFSET, bit);
+
+	return 0;
+}
+
+static int reset_mss_line_toggle(const struct device *dev, uint32_t id)
+{
+	reset_mss_line_assert(dev, id);
+	reset_mss_line_deassert(dev, id);
+
+	return 0;
+}
+
+static DEVICE_API(reset, reset_mss_driver_api) = {
+	.status = reset_mss_status,
+	.line_assert = reset_mss_line_assert,
+	.line_deassert = reset_mss_line_deassert,
+	.line_toggle = reset_mss_line_toggle
+};
+
+static const struct reset_mss_config reset_mss_config = {
+	.base = DT_REG_ADDR(DT_INST_PARENT(0))
+};
+
+DEVICE_DT_INST_DEFINE(0, NULL, NULL, NULL, &reset_mss_config, PRE_KERNEL_1,
+		      CONFIG_RESET_INIT_PRIORITY, &reset_mss_driver_api);

dts/bindings/reset/microchip,mpfs-reset.yaml

@@ -0,0 +1,18 @@
+#
+# Copyright (C) 2025 embedded brains GmbH & Co. KG
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+description: Microchip MPFS Reset Controller (SOFT_RESET_CR, SUBBLK_CLOCK_CR)
+
+compatible: "microchip,mpfs-reset"
+
+include: [base.yaml, reset-controller.yaml]
+
+properties:
+  "#reset-cells":
+    const: 1
+
+reset-cells:
+- id

dts/riscv/microchip/mpfs.dtsi

@@ -6,6 +6,7 @@
 
 #include <skeleton.dtsi>
 #include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/reset/mchp_mss_reset.h>
 
 / {
 	#address-cells = <1>;
@@ -150,6 +151,16 @@
 			status = "disabled";
 		};
 
+		mpfs_top_sysreg: syscon@20002000 {
+			compatible = "syscon";
+			reg = <0x20002000 0x1000>;
+			reset: reset {
+				compatible = "microchip,mpfs-reset";
+				#reset-cells = <1>;
+				status = "disabled";
+			};
+		};
+
 		uart0: uart@20000000 {
 			compatible = "ns16550";
 			reg = <0x20000000 0x1000>;

include/zephyr/dt-bindings/reset/mchp_mss_reset.h

@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2025 embedded brains GmbH & Co. KG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_MCHP_MSS_RESET_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_MCHP_MSS_RESET_H_
+
+/*
+ * The reset ID encodes the bit index of the SUBBLK_CLOCK_CR and SOFT_RESET_CR
+ * registers associated with the device.
+ */
+#define MSS_RESET_ID_ENVM    0x0
+#define MSS_RESET_ID_MAC0    0x1
+#define MSS_RESET_ID_MAC1    0x2
+#define MSS_RESET_ID_MMC     0x3
+#define MSS_RESET_ID_TIMER   0x4
+#define MSS_RESET_ID_MMUART0 0x5
+#define MSS_RESET_ID_MMUART1 0x6
+#define MSS_RESET_ID_MMUART2 0x7
+#define MSS_RESET_ID_MMUART3 0x8
+#define MSS_RESET_ID_MMUART4 0x9
+#define MSS_RESET_ID_SPI0    0xa
+#define MSS_RESET_ID_SPI1    0xb
+#define MSS_RESET_ID_I2C0    0xc
+#define MSS_RESET_ID_I2C1    0xd
+#define MSS_RESET_ID_CAN0    0xe
+#define MSS_RESET_ID_CAN1    0xf
+#define MSS_RESET_ID_USB     0x10
+#define MSS_RESET_ID_RSVD    0x11
+#define MSS_RESET_ID_RTC     0x12
+#define MSS_RESET_ID_QSPI    0x13
+#define MSS_RESET_ID_GPIO0   0x14
+#define MSS_RESET_ID_GPIO1   0x15
+#define MSS_RESET_ID_GPIO2   0x16
+#define MSS_RESET_ID_DDRC    0x17
+#define MSS_RESET_ID_FIC0    0x18
+#define MSS_RESET_ID_FIC1    0x19
+#define MSS_RESET_ID_FIC2    0x1a
+#define MSS_RESET_ID_FIC3    0x1b
+#define MSS_RESET_ID_ATHENA  0x1c
+#define MSS_RESET_ID_CFM     0x1d
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_MCHP_MSS_RESET_H_ */