boards: qemu_nios2: drop board definition

Remove qemu_nios2, more removals will follow.

Part of #89280

Signed-off-by: Anas Nashif <anas.nashif@intel.com>

boards/qemu/nios2/Kconfig

@@ -1,5 +0,0 @@
-# Copyright (c) 2018 Intel Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-config BOARD_QEMU_NIOS2
-	select QEMU_TARGET

boards/qemu/nios2/Kconfig.defconfig

@@ -1,9 +0,0 @@
-# Copyright (c) 2018 Intel Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-if BOARD_QEMU_NIOS2
-
-config BUILD_OUTPUT_BIN
-	default n
-
-endif

boards/qemu/nios2/Kconfig.qemu_nios2

@@ -1,5 +0,0 @@
-# Copyright (c) 2018 Intel Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-config BOARD_QEMU_NIOS2
-	select SOC_QEMU_NIOS2

boards/qemu/nios2/board.cmake

@@ -1,13 +0,0 @@
-# Copyright (c) 2018 Intel Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-set(SUPPORTED_EMU_PLATFORMS qemu)
-
-set(QEMU_CPU_TYPE_${ARCH} nios2)
-
-set(QEMU_FLAGS_${ARCH}
-  -machine altera_10m50_zephyr
-  -nographic
-  )
-
-board_set_debugger_ifnset(qemu)

boards/qemu/nios2/board.yml

@@ -1,6 +0,0 @@
-board:
-  name: qemu_nios2
-  full_name: QEMU Emulation for Altera Nios-II
-  vendor: altr
-  socs:
-  - name: qemu_nios2

boards/qemu/nios2/doc/index.rst

@@ -1,127 +0,0 @@
-.. zephyr:board:: qemu_nios2
-
-Overview
-********
-
-This board configuration will use QEMU to emulate the Altera MAX 10 platform.
-
-This configuration provides support for an Altera Nios-II CPU and these devices:
-
-* Internal Interrupt Controller
-* Altera Avalon Timer
-* NS16550 UART
-
-.. note::
-   This board configuration makes no claims about its suitability for use
-   with an actual ti_lm3s6965 hardware system, or any other hardware system.
-
-Hardware
-********
-Supported Features
-==================
-
-The following hardware features are supported:
-
-+--------------+------------+----------------------+
-| Interface    | Controller | Driver/Component     |
-+==============+============+======================+
-| IIC          | on-chip    | Internal interrupt   |
-|              |            | controller           |
-+--------------+------------+----------------------+
-| NS16550      | on-chip    | serial port          |
-| UART         |            |                      |
-+--------------+------------+----------------------+
-| TIMER        | on-chip    | system clock         |
-+--------------+------------+----------------------+
-
-The kernel currently does not support other hardware features on this platform.
-
-Devices
-========
-System Clock
-------------
-
-This board configuration uses a system clock frequency of 50 MHz.
-
-Serial Port
------------
-
-This board configuration uses a single serial communication channel with the
-CPU's UART0.
-
-If SLIP networking is enabled (see below), an additional serial port will be
-used for it.
-
-Known Problems or Limitations
-==============================
-
-The following platform features are unsupported:
-
-* Memory protection through optional MPU.  However, using a XIP kernel
-  effectively provides TEXT/RODATA write protection in ROM.
-* Writing to the hardware's flash memory
-* Serial port in Direct Memory Access (DMA) mode
-* Serial Peripheral Interface (SPI) flash
-* General-Purpose Input/Output (GPIO)
-* Inter-Integrated Circuit (I2C)
-* Ethernet
-
-
-Programming and Debugging
-*************************
-
-.. zephyr:board-supported-runners::
-
-Use this configuration to run basic Zephyr applications and kernel tests in the QEMU
-emulated environment, for example, with the :zephyr:code-sample:`synchronization` sample:
-
-.. zephyr-app-commands::
-   :zephyr-app: samples/synchronization
-   :host-os: unix
-   :board: qemu_nios2
-   :goals: run
-
-This will build an image with the synchronization sample app, boot it using
-QEMU, and display the following console output:
-
-.. code-block:: console
-
-        ***** BOOTING ZEPHYR OS v1.8.99 - BUILD: Jun 27 2017 13:09:26 *****
-        threadA: Hello World from arm!
-        threadB: Hello World from arm!
-        threadA: Hello World from arm!
-        threadB: Hello World from arm!
-        threadA: Hello World from arm!
-        threadB: Hello World from arm!
-        threadA: Hello World from arm!
-        threadB: Hello World from arm!
-        threadA: Hello World from arm!
-        threadB: Hello World from arm!
-
-Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`.
-
-Debugging
-=========
-
-Refer to the detailed overview about :ref:`application_debugging`.
-
-Networking
-==========
-
-The board supports SLIP networking over an emulated serial port
-(``CONFIG_NET_SLIP_TAP=y``). The detailed setup is described in
-:ref:`networking_with_qemu`.
-
-References
-**********
-
-* `CPU Documentation <https://www.altera.com/en_US/pdfs/literature/hb/nios2/n2cpu-nii5v1gen2.pdf>`_
-* `Nios II Processor Booting Methods in MAX 10 FPGA Devices <https://www.altera.com/en_US/pdfs/literature/an/an730.pdf>`_
-* `Embedded Peripherals IP User Guide <https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_embedded_ip.pdf>`_
-* `MAX 10 FPGA Configuration User Guide <https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/max-10/ug_m10_config.pdf>`_
-* `MAX 10 FPGA Development Kit User Guide <https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug-max10m50-fpga-dev-kit.pdf>`_
-* `Nios II Command-Line Tools <https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/nios2/edh_ed51004.pdf>`_
-* `Quartus II Scripting Reference Manual <https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/manual/tclscriptrefmnl.pdf>`_
-
-
-.. _Altera Lite Distribution: http://dl.altera.com/?edition=lite

boards/qemu/nios2/qemu_nios2.dts

@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: Apache-2.0 */
-
-/dts-v1/;
-
-#include <intel/nios2-qemu.dtsi>
-
-/ {
-	model = "qemu_nios2";
-	compatible = "qemu,nios2";
-
-	aliases {
-		uart-0 = &jtag_uart;
-		uart-1 = &ns16550_uart;
-	};
-
-	chosen {
-		zephyr,sram = &sram0;
-		zephyr,flash = &flash0;
-		zephyr,console = &ns16550_uart;
-		zephyr,shell-uart = &ns16550_uart;
-	};
-};
-
-&jtag_uart {
-	status = "okay";
-	current-speed = <115200>;
-};
-
-&ns16550_uart {
-	status = "okay";
-	current-speed = <115200>;
-};

boards/qemu/nios2/qemu_nios2.yaml

@@ -1,16 +0,0 @@
-identifier: qemu_nios2
-name: QEMU Emulation for NIOS II
-type: qemu
-simulation:
-  - name: qemu
-arch: nios2
-ram: 128
-flash: 128
-toolchain:
-  - zephyr
-testing:
-  default: true
-  ignore_tags:
-    - net
-    - bluetooth
-vendor: qemu

boards/qemu/nios2/qemu_nios2_defconfig

@@ -1,10 +0,0 @@
-# Copyright (c) 2018 Intel Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-CONFIG_HAS_ALTERA_HAL=y
-CONFIG_CONSOLE=y
-CONFIG_SERIAL=y
-CONFIG_UART_CONSOLE=y
-CONFIG_INCLUDE_RESET_VECTOR=n
-CONFIG_EXTRA_EXCEPTION_INFO=y
-CONFIG_QEMU_ICOUNT_SHIFT=4

cmake/emu/qemu.cmake

@@ -282,7 +282,7 @@ elseif(QEMU_NET_STACK)
   endif()
 endif(QEMU_PIPE_STACK)
 
-if(CONFIG_CAN AND NOT (CONFIG_NIOS2 OR CONFIG_SOC_LEON3))
+if(CONFIG_CAN AND NOT (CONFIG_SOC_LEON3))
   # Add CAN bus 0
   list(APPEND QEMU_FLAGS -object can-bus,id=canbus0)
 

samples/basic/hash_map/src/main.c

@@ -77,7 +77,7 @@ int main(void)
 			}
 		}
 	/* These architectures / boards seem to have trouble with basic timekeeping atm */
-	} while (!IS_ENABLED(CONFIG_ARCH_POSIX) && !IS_ENABLED(CONFIG_BOARD_QEMU_NIOS2));
+	} while (!IS_ENABLED(CONFIG_ARCH_POSIX));
 
 out:
 

soc/altr/qemu_nios2/CMakeLists.txt

@@ -1,7 +0,0 @@
-# Copyright (c) 2018 Intel Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-zephyr_include_directories(include)
-zephyr_include_directories(.)
-
-set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")

soc/altr/qemu_nios2/Kconfig

@@ -1,8 +0,0 @@
-# Copyright (c) 2018 Intel Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_QEMU_NIOS2
-	select NIOS2
-	select HAS_MUL_INSTRUCTION
-	select HAS_DIV_INSTRUCTION
-	select HAS_MULX_INSTRUCTION

soc/altr/qemu_nios2/Kconfig.defconfig

@@ -1,9 +0,0 @@
-# Copyright (c) 2018 Intel Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_QEMU_NIOS2
-
-config SYS_CLOCK_HW_CYCLES_PER_SEC
-	default 50000000
-
-endif

soc/altr/qemu_nios2/Kconfig.soc

@@ -1,8 +0,0 @@
-# Copyright (c) 2018 Intel Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_QEMU_NIOS2
-	bool
-
-config SOC
-	default "qemu_nios2" if SOC_QEMU_NIOS2

soc/altr/qemu_nios2/include/layout.h

@@ -1,14 +0,0 @@
-/*
- * Copyright (c) 2016 Intel Corporation
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <system.h>
-
-/* To simulate XIP on QEMU, we split RAM into two chunks, with the
- * higher-addressed chunk considered "ROM"
- */
-
-#define _RESET_VECTOR		_ROM_ADDR
-#define	_EXC_VECTOR		ALT_CPU_EXCEPTION_ADDR

soc/altr/qemu_nios2/include/linker.h

@@ -1,107 +0,0 @@
-/*
- * linker.h - Linker script mapping information
- *
- * Machine generated for CPU 'nios2_gen2_0' in SOPC Builder design 'ghrd_10m50da'
- * SOPC Builder design path: ../../ghrd_10m50da.sopcinfo
- *
- * Generated: Tue May 03 11:35:27 MYT 2016
- */
-
-/*
- * DO NOT MODIFY THIS FILE
- *
- * Changing this file will have subtle consequences
- * which will almost certainly lead to a nonfunctioning
- * system. If you do modify this file, be aware that your
- * changes will be overwritten and lost when this file
- * is generated again.
- *
- * DO NOT MODIFY THIS FILE
- */
-
-/*
- * License Agreement
- *
- * Copyright (c) 2008
- * Altera Corporation, San Jose, California, USA.
- * All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * This agreement shall be governed in all respects by the laws of the State
- * of California and by the laws of the United States of America.
- */
-
-#ifndef __LINKER_H_
-#define __LINKER_H_
-
-
-/*
- * BSP controls alt_load() behavior in crt0.
- *
- */
-
-#define ALT_LOAD_EXPLICITLY_CONTROLLED
-
-
-/*
- * Base address and span (size in bytes) of each linker region
- *
- */
-
-#define ONCHIP_FLASH_0_DATA_REGION_BASE 0x20
-#define ONCHIP_FLASH_0_DATA_REGION_SPAN 753632
-#define ONCHIP_MEMORY2_0_BEFORE_EXCEPTION_REGION_BASE 0x400000
-#define ONCHIP_MEMORY2_0_BEFORE_EXCEPTION_REGION_SPAN 32
-#define ONCHIP_MEMORY2_0_REGION_BASE 0x400020
-#define ONCHIP_MEMORY2_0_REGION_SPAN 262112
-#define RESET_REGION_BASE 0x0
-#define RESET_REGION_SPAN 32
-
-
-/*
- * Devices associated with code sections
- *
- */
-
-#define ALT_EXCEPTIONS_DEVICE ONCHIP_MEMORY2_0
-#define ALT_RESET_DEVICE ONCHIP_FLASH_0_DATA
-#define ALT_RODATA_DEVICE ONCHIP_MEMORY2_0
-#define ALT_RWDATA_DEVICE ONCHIP_MEMORY2_0
-#define ALT_TEXT_DEVICE ONCHIP_FLASH_0_DATA
-
-
-/*
- * Initialization code at the reset address is allowed (e.g. no external bootloader).
- *
- */
-
-#define ALT_ALLOW_CODE_AT_RESET
-
-
-/*
- * The alt_load() facility is called from crt0 to copy sections into RAM.
- *
- */
-
-#define ALT_LOAD_COPY_EXCEPTIONS
-#define ALT_LOAD_COPY_RODATA
-#define ALT_LOAD_COPY_RWDATA
-
-#endif /* __LINKER_H_ */

soc/altr/qemu_nios2/include/system.h

@@ -1,281 +0,0 @@
-/*
- * DO NOT MODIFY THIS FILE
- *
- * Changing this file will have subtle consequences
- * which will almost certainly lead to a nonfunctioning
- * system. If you do modify this file, be aware that your
- * changes will be overwritten and lost when this file
- * is generated again.
- *
- * DO NOT MODIFY THIS FILE
- */
-
-/*
- * License Agreement
- *
- * Copyright (c) 2008
- * Altera Corporation, San Jose, California, USA.
- * All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * This agreement shall be governed in all respects by the laws of the State
- * of California and by the laws of the United States of America.
- */
-
-#ifndef __SYSTEM_H_
-#define __SYSTEM_H_
-
-#include "linker.h"
-
-/*
- * CPU configuration
- *
- */
-
-#define ALT_CPU_ARCHITECTURE "altera_nios2_gen2"
-#define ALT_CPU_BIG_ENDIAN 0
-#define ALT_CPU_BREAK_ADDR 0x00200820
-#define ALT_CPU_CPU_ARCH_NIOS2_R1
-#define ALT_CPU_CPU_FREQ 50000000u
-#define ALT_CPU_CPU_ID_SIZE 1
-#define ALT_CPU_CPU_ID_VALUE 0x00000000
-#define ALT_CPU_CPU_IMPLEMENTATION "tiny"
-#define ALT_CPU_DATA_ADDR_WIDTH 0x17
-#define ALT_CPU_DCACHE_LINE_SIZE 0
-#define ALT_CPU_DCACHE_LINE_SIZE_LOG2 0
-#define ALT_CPU_DCACHE_SIZE 0
-#define ALT_CPU_EXCEPTION_ADDR 0x00400020
-#define ALT_CPU_FLASH_ACCELERATOR_LINES 0
-#define ALT_CPU_FLASH_ACCELERATOR_LINE_SIZE 0
-#define ALT_CPU_FLUSHDA_SUPPORTED
-#define ALT_CPU_FREQ 50000000
-#define ALT_CPU_HARDWARE_DIVIDE_PRESENT 1
-#define ALT_CPU_HARDWARE_MULTIPLY_PRESENT 1
-#define ALT_CPU_HARDWARE_MULX_PRESENT 1
-#define ALT_CPU_HAS_DEBUG_CORE 1
-#define ALT_CPU_HAS_DEBUG_STUB
-#define ALT_CPU_HAS_ILLEGAL_INSTRUCTION_EXCEPTION
-#define ALT_CPU_HAS_JMPI_INSTRUCTION
-#define ALT_CPU_ICACHE_LINE_SIZE 0
-#define ALT_CPU_ICACHE_LINE_SIZE_LOG2 0
-#define ALT_CPU_ICACHE_SIZE 0
-#define ALT_CPU_INST_ADDR_WIDTH 0x17
-#define ALT_CPU_NAME "nios2_gen2_0"
-#define ALT_CPU_OCI_VERSION 1
-#define ALT_CPU_RESET_ADDR 0x00000000
-#define ALT_CPU_HAS_EXTRA_EXCEPTION_INFO 1
-
-
-#define ALT_DEVICE_FAMILY "MAX 10"
-#define ALT_ENHANCED_INTERRUPT_API_PRESENT
-#define ALT_IRQ_BASE NULL
-#define ALT_LOG_PORT "/dev/null"
-#define ALT_LOG_PORT_BASE 0x0
-#define ALT_LOG_PORT_DEV null
-#define ALT_LOG_PORT_TYPE ""
-#define ALT_NUM_EXTERNAL_INTERRUPT_CONTROLLERS 0
-#define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1
-#define ALT_NUM_INTERRUPT_CONTROLLERS 1
-#define ALT_STDERR "/dev/jtag_uart_0"
-#define ALT_STDERR_BASE 0x201000
-#define ALT_STDERR_DEV jtag_uart_0
-#define ALT_STDERR_IS_JTAG_UART
-#define ALT_STDERR_PRESENT
-#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
-#define ALT_STDIN "/dev/jtag_uart_0"
-#define ALT_STDIN_BASE 0x201000
-#define ALT_STDIN_DEV jtag_uart_0
-#define ALT_STDIN_IS_JTAG_UART
-#define ALT_STDIN_PRESENT
-#define ALT_STDIN_TYPE "altera_avalon_jtag_uart"
-#define ALT_STDOUT "/dev/jtag_uart_0"
-#define ALT_STDOUT_BASE 0x201000
-#define ALT_STDOUT_DEV jtag_uart_0
-#define ALT_STDOUT_IS_JTAG_UART
-#define ALT_STDOUT_PRESENT
-#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart"
-#define ALT_SYSTEM_NAME "ghrd_10m50da"
-
-
-/*
- * a_16550_uart_0 configuration
- *
- */
-
-#define ALT_MODULE_CLASS_a_16550_uart_0 altera_16550_uart
-#define A_16550_UART_0_BASE 0x440000
-#define A_16550_UART_0_FIFO_DEPTH 64
-#define A_16550_UART_0_FIFO_MODE 1
-#define A_16550_UART_0_FIO_HWFC 0
-#define A_16550_UART_0_FIO_SWFC 0
-#define A_16550_UART_0_FREQ 50000000
-#define A_16550_UART_0_IRQ 1
-#define A_16550_UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0
-#define A_16550_UART_0_NAME "/dev/a_16550_uart_0"
-#define A_16550_UART_0_SPAN 512
-#define A_16550_UART_0_TYPE "altera_16550_uart"
-
-
-/*
- * hal configuration
- *
- */
-
-#define ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API
-#define ALT_MAX_FD 32
-#define ALT_SYS_CLK none
-#define ALT_TIMESTAMP_CLK none
-
-
-/*
- * jtag_uart_0 configuration
- *
- */
-
-#define ALT_MODULE_CLASS_jtag_uart_0 altera_avalon_jtag_uart
-#define JTAG_UART_0_BASE 0x201000
-#define JTAG_UART_0_IRQ 0
-#define JTAG_UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0
-#define JTAG_UART_0_NAME "/dev/jtag_uart_0"
-#define JTAG_UART_0_READ_DEPTH 64
-#define JTAG_UART_0_READ_THRESHOLD 8
-#define JTAG_UART_0_SPAN 8
-#define JTAG_UART_0_TYPE "altera_avalon_jtag_uart"
-#define JTAG_UART_0_WRITE_DEPTH 64
-#define JTAG_UART_0_WRITE_THRESHOLD 8
-
-
-/*
- * onchip_flash_0_csr configuration
- *
- */
-
-#define ALT_MODULE_CLASS_onchip_flash_0_csr altera_onchip_flash
-#define ONCHIP_FLASH_0_CSR_BASE 0x200000
-#define ONCHIP_FLASH_0_CSR_BYTES_PER_PAGE 8192
-#define ONCHIP_FLASH_0_CSR_IRQ -1
-#define ONCHIP_FLASH_0_CSR_IRQ_INTERRUPT_CONTROLLER_ID -1
-#define ONCHIP_FLASH_0_CSR_NAME "/dev/onchip_flash_0_csr"
-#define ONCHIP_FLASH_0_CSR_READ_ONLY_MODE 0
-#define ONCHIP_FLASH_0_CSR_SECTOR1_ENABLED 1
-#define ONCHIP_FLASH_0_CSR_SECTOR1_END_ADDR 0x7fff
-#define ONCHIP_FLASH_0_CSR_SECTOR1_START_ADDR 0
-#define ONCHIP_FLASH_0_CSR_SECTOR2_ENABLED 1
-#define ONCHIP_FLASH_0_CSR_SECTOR2_END_ADDR 0xffff
-#define ONCHIP_FLASH_0_CSR_SECTOR2_START_ADDR 0x8000
-#define ONCHIP_FLASH_0_CSR_SECTOR3_ENABLED 1
-#define ONCHIP_FLASH_0_CSR_SECTOR3_END_ADDR 0x6ffff
-#define ONCHIP_FLASH_0_CSR_SECTOR3_START_ADDR 0x10000
-#define ONCHIP_FLASH_0_CSR_SECTOR4_ENABLED 1
-#define ONCHIP_FLASH_0_CSR_SECTOR4_END_ADDR 0xb7fff
-#define ONCHIP_FLASH_0_CSR_SECTOR4_START_ADDR 0x70000
-#define ONCHIP_FLASH_0_CSR_SECTOR5_ENABLED 0
-#define ONCHIP_FLASH_0_CSR_SECTOR5_END_ADDR 0xffffffff
-#define ONCHIP_FLASH_0_CSR_SECTOR5_START_ADDR 0xffffffff
-#define ONCHIP_FLASH_0_CSR_SPAN 8
-#define ONCHIP_FLASH_0_CSR_TYPE "altera_onchip_flash"
-
-
-/*
- * onchip_flash_0_data configuration
- *
- */
-
-#define ALT_MODULE_CLASS_onchip_flash_0_data altera_onchip_flash
-#define ONCHIP_FLASH_0_DATA_BASE 0x0
-#define ONCHIP_FLASH_0_DATA_BYTES_PER_PAGE 8192
-#define ONCHIP_FLASH_0_DATA_IRQ -1
-#define ONCHIP_FLASH_0_DATA_IRQ_INTERRUPT_CONTROLLER_ID -1
-#define ONCHIP_FLASH_0_DATA_NAME "/dev/onchip_flash_0_data"
-#define ONCHIP_FLASH_0_DATA_READ_ONLY_MODE 0
-#define ONCHIP_FLASH_0_DATA_SECTOR1_ENABLED 1
-#define ONCHIP_FLASH_0_DATA_SECTOR1_END_ADDR 0x7fff
-#define ONCHIP_FLASH_0_DATA_SECTOR1_START_ADDR 0
-#define ONCHIP_FLASH_0_DATA_SECTOR2_ENABLED 1
-#define ONCHIP_FLASH_0_DATA_SECTOR2_END_ADDR 0xffff
-#define ONCHIP_FLASH_0_DATA_SECTOR2_START_ADDR 0x8000
-#define ONCHIP_FLASH_0_DATA_SECTOR3_ENABLED 1
-#define ONCHIP_FLASH_0_DATA_SECTOR3_END_ADDR 0x6ffff
-#define ONCHIP_FLASH_0_DATA_SECTOR3_START_ADDR 0x10000
-#define ONCHIP_FLASH_0_DATA_SECTOR4_ENABLED 1
-#define ONCHIP_FLASH_0_DATA_SECTOR4_END_ADDR 0xb7fff
-#define ONCHIP_FLASH_0_DATA_SECTOR4_START_ADDR 0x70000
-#define ONCHIP_FLASH_0_DATA_SECTOR5_ENABLED 0
-#define ONCHIP_FLASH_0_DATA_SECTOR5_END_ADDR 0xffffffff
-#define ONCHIP_FLASH_0_DATA_SECTOR5_START_ADDR 0xffffffff
-#define ONCHIP_FLASH_0_DATA_SPAN 753664
-#define ONCHIP_FLASH_0_DATA_TYPE "altera_onchip_flash"
-
-
-/*
- * onchip_memory2_0 configuration
- *
- */
-
-#define ALT_MODULE_CLASS_onchip_memory2_0 altera_avalon_onchip_memory2
-#define ONCHIP_MEMORY2_0_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
-#define ONCHIP_MEMORY2_0_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
-#define ONCHIP_MEMORY2_0_BASE 0x400000
-#define ONCHIP_MEMORY2_0_CONTENTS_INFO ""
-#define ONCHIP_MEMORY2_0_DUAL_PORT 0
-#define ONCHIP_MEMORY2_0_GUI_RAM_BLOCK_TYPE "AUTO"
-#define ONCHIP_MEMORY2_0_INIT_CONTENTS_FILE "ghrd_10m50da_onchip_memory2_0"
-#define ONCHIP_MEMORY2_0_INIT_MEM_CONTENT 0
-#define ONCHIP_MEMORY2_0_INSTANCE_ID "NONE"
-#define ONCHIP_MEMORY2_0_IRQ -1
-#define ONCHIP_MEMORY2_0_IRQ_INTERRUPT_CONTROLLER_ID -1
-#define ONCHIP_MEMORY2_0_NAME "/dev/onchip_memory2_0"
-#define ONCHIP_MEMORY2_0_NON_DEFAULT_INIT_FILE_ENABLED 0
-#define ONCHIP_MEMORY2_0_RAM_BLOCK_TYPE "AUTO"
-#define ONCHIP_MEMORY2_0_READ_DURING_WRITE_MODE "DONT_CARE"
-#define ONCHIP_MEMORY2_0_SINGLE_CLOCK_OP 0
-#define ONCHIP_MEMORY2_0_SIZE_MULTIPLE 1
-#define ONCHIP_MEMORY2_0_SIZE_VALUE 262144
-#define ONCHIP_MEMORY2_0_SPAN 262144
-#define ONCHIP_MEMORY2_0_TYPE "altera_avalon_onchip_memory2"
-#define ONCHIP_MEMORY2_0_WRITABLE 1
-
-
-/*
- * timer_0 configuration
- *
- */
-
-#define ALT_MODULE_CLASS_timer_0 altera_avalon_timer
-#define TIMER_0_ALWAYS_RUN 0
-#define TIMER_0_BASE 0x440200
-#define TIMER_0_COUNTER_SIZE 32
-#define TIMER_0_FIXED_PERIOD 0
-#define TIMER_0_FREQ 50000000
-#define TIMER_0_IRQ 2
-#define TIMER_0_IRQ_INTERRUPT_CONTROLLER_ID 0
-#define TIMER_0_LOAD_VALUE 49999
-#define TIMER_0_MULT 0.001
-#define TIMER_0_NAME "/dev/timer_0"
-#define TIMER_0_PERIOD 1
-#define TIMER_0_PERIOD_UNITS "ms"
-#define TIMER_0_RESET_OUTPUT 0
-#define TIMER_0_SNAPSHOT 1
-#define TIMER_0_SPAN 32
-#define TIMER_0_TICKS_PER_SEC 1000
-#define TIMER_0_TIMEOUT_PULSE_OUTPUT 0
-#define TIMER_0_TYPE "altera_avalon_timer"
-
-#endif /* __SYSTEM_H_ */

soc/altr/qemu_nios2/linker.ld

@@ -1,20 +0,0 @@
-/*
- * Copyright (c) 2016 Intel Corporation
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * @brief Linker script for the Nios II/e CPU with timer and 16550 UART
- */
-
-#include <layout.h>
-#include <zephyr/devicetree.h>
-
-#define _RAM_ADDR	DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
-#define _RAM_SIZE	DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
-
-#define _ROM_ADDR	DT_REG_ADDR(DT_CHOSEN(zephyr_flash))
-#define _ROM_SIZE	DT_REG_SIZE(DT_CHOSEN(zephyr_flash))
-
-#include <zephyr/arch/nios2/linker.ld>

soc/altr/qemu_nios2/soc.h

@@ -1,13 +0,0 @@
-/*
- * Copyright (c) 2018 Intel Corporation
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-
-#ifndef __SOC_H_
-#define __SOC_H_
-
-#include <system.h>
-
-#endif

soc/altr/qemu_nios2/soc.yml

@@ -1,2 +0,0 @@
-socs:
-  - name: qemu_nios2

tests/benchmarks/ipi_metric/testcase.yaml

@@ -13,7 +13,6 @@ common:
   platform_exclude:
     - qemu_malta/qemu_malta
     - qemu_malta/qemu_malta/be
-    - qemu_nios2
   integration_platforms:
     - qemu_x86_64
     - qemu_cortex_a53/qemu_cortex_a53/smp

tests/benchmarks/thread_metric/testcase.yaml

@@ -13,7 +13,6 @@ common:
   platform_exclude:
     - qemu_malta/qemu_malta
     - qemu_malta/qemu_malta/be
-    - qemu_nios2
   integration_platforms:
     - qemu_x86
     - qemu_cortex_a53

tests/lib/mpsc_pbuf/testcase.yaml

@@ -9,7 +9,6 @@ tests:
       - qemu_cortex_m3
       - qemu_cortex_r5
       - qemu_leon3
-      - qemu_nios2
       - qemu_riscv32
       - qemu_riscv64
       - qemu_x86

tests/posix/common/testcase.yaml

@@ -6,9 +6,6 @@ common:
   platform_key:
     - arch
     - simulation
-  platform_exclude:
-    # consistently overflows flash
-    - qemu_nios2
   filter: not CONFIG_NATIVE_LIBC
 tests:
   portability.posix.common: {}