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This patch adds a minimal driver for the MAX98091 audio codec. Currently, playback functionality is supported. Co-developed-by: Rutvij Trivedi <rutvij.trivedi@siliconsignals.io> Signed-off-by: Rutvij Trivedi <rutvij.trivedi@siliconsignals.io> Co-developed-by: Tarang Raval <tarang.raval@siliconsignals.io> Signed-off-by: Tarang Raval <tarang.raval@siliconsignals.io> Signed-off-by: Silicon Signals <siliconsignalsforgit@gmail.com>pull/91480/head
Silicon Signals
1 month ago
committed by
Dan Kalowsky
6 changed files with 567 additions and 0 deletions
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# Copyright (c) 2025 Silicon Signals Pvt. Ltd. |
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# SPDX-License-Identifier: Apache-2.0 |
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config AUDIO_CODEC_MAX98091 |
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bool "Maxim MAX98091 codec support" |
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default y |
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select I2C |
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depends on DT_HAS_MAXIM_MAX98091_ENABLED |
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help |
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Enable support for the MAX98091 I2S codec via I2C. |
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/*
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* SPDX-License-Identifier: Apache-2.0 |
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* |
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* Copyright (c) 2025 Silicon Signals Pvt. Ltd. |
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* Author: Rutvij Trivedi <rutvij.trivedi@siliconsignals.io> |
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* Author: Tarang Raval <tarang.raval@siliconsignals.io> |
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*/ |
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#include <zephyr/drivers/i2c.h> |
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#include <zephyr/audio/codec.h> |
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#include <zephyr/device.h> |
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#include <zephyr/logging/log.h> |
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#include "max98091.h" |
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LOG_MODULE_REGISTER(maxim_max98091); |
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#define DT_DRV_COMPAT maxim_max98091 |
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struct max98091_config { |
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struct i2c_dt_spec i2c; |
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uint32_t mclk_freq; |
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}; |
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static void max98091_write_reg(const struct device *dev, uint8_t reg, uint8_t val) |
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{ |
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const struct max98091_config *const dev_cfg = dev->config; |
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i2c_reg_write_byte_dt(&dev_cfg->i2c, reg, val); |
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} |
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static void max98091_read_reg(const struct device *dev, uint8_t reg, uint8_t *val) |
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{ |
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const struct max98091_config *const dev_cfg = dev->config; |
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i2c_reg_read_byte_dt(&dev_cfg->i2c, reg, val); |
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} |
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static void max98091_update_reg(const struct device *dev, uint8_t reg, uint8_t mask, uint8_t val) |
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{ |
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const struct max98091_config *const dev_cfg = dev->config; |
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i2c_reg_update_byte_dt(&dev_cfg->i2c, reg, mask, val); |
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} |
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static void max98091_soft_reset(const struct device *dev) |
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{ |
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max98091_write_reg(dev, M98091_REG_SOFTWARE_RESET, 0x01); |
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k_msleep(20); |
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} |
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/* Configuration Functions */ |
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static int max98091_protocol_config(const struct device *dev, audio_dai_type_t dai_type) |
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{ |
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uint8_t fmt_reg = 0; |
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switch (dai_type) { |
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case AUDIO_DAI_TYPE_I2S: |
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fmt_reg |= M98091_I2S_S_MASK; |
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break; |
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case AUDIO_DAI_TYPE_LEFT_JUSTIFIED: |
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fmt_reg |= M98091_LJ_S_MASK; |
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break; |
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case AUDIO_DAI_TYPE_RIGHT_JUSTIFIED: |
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fmt_reg |= M98091_RJ_S_MASK; |
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break; |
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default: |
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LOG_ERR("Unsupported DAI type: %d", dai_type); |
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return -EINVAL; |
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} |
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max98091_write_reg(dev, M98091_REG_DAI_INTERFACE, fmt_reg); |
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LOG_DBG("Protocol configured: 0x%02x", fmt_reg); |
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return 0; |
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} |
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static int max98091_audio_fmt_config(const struct device *dev, audio_dai_cfg_t *cfg) |
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{ |
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uint8_t sample_rate; |
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uint8_t channels; |
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uint8_t word_size; |
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switch (cfg->i2s.frame_clk_freq) { |
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case 8000: |
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sample_rate = M98091_SR_8K_MASK; |
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break; |
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case 16000: |
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sample_rate = M98091_SR_16K_MASK; |
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break; |
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case 32000: |
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sample_rate = M98091_SR_32K_MASK; |
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break; |
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case 44100: |
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sample_rate = M98091_SR_44K1_MASK; |
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break; |
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case 48000: |
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sample_rate = M98091_SR_48K_MASK; |
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break; |
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case 96000: |
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sample_rate = M98091_SR_96K_MASK; |
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break; |
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default: |
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LOG_ERR("Unsupported sample rate: %d", cfg->i2s.frame_clk_freq); |
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return -EINVAL; |
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} |
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max98091_write_reg(dev, M98091_REG_QUICK_SAMPLE_RATE, sample_rate); |
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switch (cfg->i2s.channels) { |
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case 1: /* Mono */ |
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channels = 1; |
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break; |
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case 2: /* Stereo */ |
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channels = 0; |
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break; |
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default: |
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LOG_ERR("Unsupported channels: %d", cfg->i2s.channels); |
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return -EINVAL; |
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} |
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max98091_update_reg(dev, M98091_REG_IO_CONFIGURATION, M98091_DMONO_MASK, channels); |
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switch (cfg->i2s.word_size) { |
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case 16: |
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word_size = M98091_16B_WS; |
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break; |
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default: |
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LOG_ERR("Word size %d bits not supported; falling back to 16 bits", |
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cfg->i2s.word_size); |
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word_size = M98091_16B_WS; |
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break; |
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} |
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max98091_update_reg(dev, M98091_REG_INTERFACE_FORMAT, M98091_WS_MASK, word_size); |
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return 0; |
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} |
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static void max98091_set_system_clock(const struct device *dev, uint32_t mclk_freq) |
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{ |
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uint8_t psclk; |
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if (mclk_freq >= 10000000 && mclk_freq <= 20000000) { |
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psclk = M98091_PSCLK_DIV1; |
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} else if (mclk_freq > 20000000 && mclk_freq <= 40000000) { |
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psclk = M98091_PSCLK_DIV2; |
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} else if (mclk_freq > 40000000 && mclk_freq <= 60000000) { |
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psclk = M98091_PSCLK_DIV4; |
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} else { |
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LOG_ERR("Invalid MCLK frequency: %u", mclk_freq); |
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return; |
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} |
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max98091_write_reg(dev, M98091_REG_SYSTEM_CLOCK, psclk); |
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LOG_DBG("System clock set: PSCLK=0x%02x", psclk); |
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max98091_update_reg(dev, M98091_REG_MASTER_MODE, M98091_MAS_MASK, 0); |
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} |
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static int max98091_set_volume_or_mute(const struct device *dev, audio_channel_t channel, int value, |
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bool is_volume) |
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{ |
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uint8_t hp_mask = is_volume ? M98091_HPVOLL_MASK : M98091_HPLM_MASK; |
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uint8_t spk_mask = is_volume ? M98091_SPVOLL_MASK : M98091_SPLM_MASK; |
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switch (channel) { |
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case AUDIO_CHANNEL_FRONT_LEFT: |
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max98091_update_reg(dev, M98091_REG_LEFT_SPK_VOLUME, spk_mask, value); |
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return 0; |
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case AUDIO_CHANNEL_FRONT_RIGHT: |
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max98091_update_reg(dev, M98091_REG_RIGHT_SPK_VOLUME, spk_mask, value); |
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return 0; |
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case AUDIO_CHANNEL_HEADPHONE_LEFT: |
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max98091_update_reg(dev, M98091_REG_LEFT_HP_VOLUME, hp_mask, value); |
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return 0; |
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case AUDIO_CHANNEL_HEADPHONE_RIGHT: |
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max98091_update_reg(dev, M98091_REG_RIGHT_HP_VOLUME, hp_mask, value); |
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return 0; |
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case AUDIO_CHANNEL_ALL: |
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max98091_update_reg(dev, M98091_REG_LEFT_SPK_VOLUME, spk_mask, value); |
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max98091_update_reg(dev, M98091_REG_RIGHT_SPK_VOLUME, spk_mask, value); |
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max98091_update_reg(dev, M98091_REG_LEFT_HP_VOLUME, hp_mask, value); |
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max98091_update_reg(dev, M98091_REG_RIGHT_HP_VOLUME, hp_mask, value); |
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return 0; |
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default: |
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return -EINVAL; |
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} |
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} |
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static int max98091_out_volume_config(const struct device *dev, audio_channel_t channel, int volume) |
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{ |
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return max98091_set_volume_or_mute(dev, channel, volume, true); |
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} |
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static int max98091_out_mute_config(const struct device *dev, audio_channel_t channel, bool mute) |
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{ |
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return max98091_set_volume_or_mute(dev, channel, mute, false); |
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} |
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/* Audio Path Configuration */ |
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static void max98091_configure_output(const struct device *dev) |
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{ |
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max98091_update_reg(dev, M98091_REG_IO_CONFIGURATION, M98091_SDIEN_MASK, M98091_SDIEN_MASK); |
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max98091_write_reg(dev, M98091_REG_LEFT_SPK_MIXER, M98091_MIXSPL_DACL_MASK); |
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max98091_write_reg(dev, M98091_REG_RIGHT_SPK_MIXER, M98091_MIXSPR_DACR_MASK); |
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/* select DAC only source */ |
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max98091_write_reg(dev, M98091_REG_HP_CONTROL, 0x00); |
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/* M98091_HPREN_MASK, M98091_HPLEN_MASK, M98091_SPREN_MASK,
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* M98091_SPLEN_MASK, M98091_DAREN_MASK, M98091_DALEN_MASK |
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*/ |
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max98091_write_reg(dev, M98091_REG_OUTPUT_ENABLE, 0xf3); |
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max98091_out_volume_config(dev, AUDIO_CHANNEL_ALL, M98091_DEFAULT_VOLUME); |
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max98091_out_mute_config(dev, AUDIO_CHANNEL_ALL, false); |
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} |
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static void max98091_start_output(const struct device *dev) |
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{ |
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ARG_UNUSED(dev); |
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} |
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static void max98091_stop_output(const struct device *dev) |
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{ |
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ARG_UNUSED(dev); |
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} |
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static int max98091_set_property(const struct device *dev, audio_property_t property, |
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audio_channel_t channel, audio_property_value_t val) |
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{ |
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switch (property) { |
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case AUDIO_PROPERTY_OUTPUT_VOLUME: |
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max98091_out_volume_config(dev, channel, val.vol); |
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case AUDIO_PROPERTY_OUTPUT_MUTE: |
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max98091_out_mute_config(dev, channel, val.mute); |
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default: |
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return -EINVAL; |
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} |
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} |
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static int max98091_configure(const struct device *dev, struct audio_codec_cfg *cfg) |
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{ |
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const struct max98091_config *const dev_cfg = dev->config; |
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if (cfg->dai_type >= AUDIO_DAI_TYPE_INVALID) { |
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LOG_ERR("dai_type not supported"); |
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return -EINVAL; |
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} |
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max98091_soft_reset(dev); |
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if (cfg->dai_route == AUDIO_ROUTE_BYPASS) { |
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return 0; |
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} |
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/* Put the audio codec into shutdown mode */ |
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max98091_write_reg(dev, M98091_REG_DEVICE_SHUTDOWN, 0x00); |
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max98091_write_reg(dev, M98091_REG_DAC_CONTROL, 0x00); |
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max98091_write_reg(dev, M98091_REG_TDM_CONTROL, 0x00); |
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/* Set DLY = 1 to conform to the I2S standard.
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* DLY is only effective when TDM = 0 |
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*/ |
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max98091_write_reg(dev, M98091_REG_INTERFACE_FORMAT, M98091_DLY_MASK); |
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/* Configure system clock */ |
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max98091_set_system_clock(dev, dev_cfg->mclk_freq); |
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max98091_protocol_config(dev, cfg->dai_type); |
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max98091_audio_fmt_config(dev, &cfg->dai_cfg); |
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/* Configure audio paths based on route */ |
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switch (cfg->dai_route) { |
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case AUDIO_ROUTE_PLAYBACK: |
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max98091_configure_output(dev); |
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break; |
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default: |
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LOG_DBG("Unsupported audio route selected"); |
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break; |
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} |
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/* Bring the audio codec out of shutdown mode */ |
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max98091_write_reg(dev, M98091_REG_DEVICE_SHUTDOWN, M98091_SHDNN_MASK); |
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return 0; |
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} |
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static const struct audio_codec_api max98091_api = { |
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.configure = max98091_configure, |
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.start_output = max98091_start_output, |
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.stop_output = max98091_stop_output, |
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.set_property = max98091_set_property, |
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}; |
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static int max98091_init(const struct device *dev) |
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{ |
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const struct max98091_config *cfg_tan = dev->config; |
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uint8_t device_id; |
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if (!i2c_is_ready_dt(&cfg_tan->i2c)) { |
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LOG_ERR("I2C bus not ready"); |
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return -ENODEV; |
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} |
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max98091_read_reg(dev, M98091_REG_REVISION_ID, &device_id); |
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if (device_id >= M98091_REVA && (device_id <= M98091_REVA + 0x0f)) { |
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LOG_INF("MAX98091 Device ID: 0x%02X", device_id); |
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return 0; |
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} |
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LOG_ERR("Invalid MAX98091 Device ID: 0x%02X", device_id); |
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return -EINVAL; |
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} |
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#define MAX98091_INIT(inst) \ |
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static const struct max98091_config max98091_config_##inst = { \ |
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.i2c = I2C_DT_SPEC_INST_GET(inst), \ |
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.mclk_freq = DT_INST_PROP(inst, mclk_frequency)}; \ |
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DEVICE_DT_INST_DEFINE(inst, max98091_init, NULL, NULL, &max98091_config_##inst, \ |
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POST_KERNEL, CONFIG_AUDIO_CODEC_INIT_PRIORITY, &max98091_api); |
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DT_INST_FOREACH_STATUS_OKAY(MAX98091_INIT) |
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/*
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* SPDX-License-Identifier: Apache-2.0 |
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* |
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* Copyright (c) 2025 Silicon Signals Pvt. Ltd. |
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* Author: Rutvij Trivedi <rutvij.trivedi@siliconsignals.io> |
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* Author: Tarang Raval <tarang.raval@siliconsignals.io> |
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*/ |
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#ifndef ZEPHYR_INCLUDE_CODEC_MAX98091_H_ |
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#define ZEPHYR_INCLUDE_CODEC_MAX98091_H_ |
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/*
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* MAX98091 Register Definitions |
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*/ |
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#define M98091_REG_SOFTWARE_RESET 0x00 |
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#define M98091_REG_DEVICE_STATUS 0x01 |
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#define M98091_REG_JACK_STATUS 0x02 |
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#define M98091_REG_INTERRUPT_S 0x03 |
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#define M98091_REG_MASTER_CLOCK 0x04 |
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#define M98091_REG_QUICK_SAMPLE_RATE 0x05 |
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#define M98091_REG_DAI_INTERFACE 0x06 |
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#define M98091_REG_DAC_PATH 0x07 |
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#define M98091_REG_MIC_DIRECT_TO_ADC 0x08 |
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#define M98091_REG_LINE_TO_ADC 0x09 |
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#define M98091_REG_ANALOG_MIC_LOOP 0x0A |
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#define M98091_REG_ANALOG_LINE_LOOP 0x0B |
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#define M98091_REG_RESERVED 0x0C |
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#define M98091_REG_LINE_INPUT_CONFIG 0x0D |
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#define M98091_REG_LINE_INPUT_LEVEL 0x0E |
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#define M98091_REG_INPUT_MODE 0x0F |
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#define M98091_REG_MIC1_INPUT_LEVEL 0x10 |
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#define M98091_REG_MIC2_INPUT_LEVEL 0x11 |
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#define M98091_REG_MIC_BIAS_VOLTAGE 0x12 |
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#define M98091_REG_DIGITAL_MIC_ENABLE 0x13 |
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#define M98091_REG_DIGITAL_MIC_CONFIG 0x14 |
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#define M98091_REG_LEFT_ADC_MIXER 0x15 |
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#define M98091_REG_RIGHT_ADC_MIXER 0x16 |
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#define M98091_REG_LEFT_ADC_LEVEL 0x17 |
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#define M98091_REG_RIGHT_ADC_LEVEL 0x18 |
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#define M98091_REG_ADC_BIQUAD_LEVEL 0x19 |
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#define M98091_REG_ADC_SIDETONE 0x1A |
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#define M98091_REG_SYSTEM_CLOCK 0x1B |
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#define M98091_REG_CLOCK_MODE 0x1C |
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#define M98091_REG_CLOCK_RATIO_NI_MSB 0x1D |
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#define M98091_REG_CLOCK_RATIO_NI_LSB 0x1E |
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#define M98091_REG_CLOCK_RATIO_MI_MSB 0x1F |
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#define M98091_REG_CLOCK_RATIO_MI_LSB 0x20 |
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#define M98091_REG_MASTER_MODE 0x21 |
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#define M98091_REG_INTERFACE_FORMAT 0x22 |
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#define M98091_REG_TDM_CONTROL 0x23 |
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#define M98091_REG_TDM_FORMAT 0x24 |
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#define M98091_REG_IO_CONFIGURATION 0x25 |
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#define M98091_REG_FILTER_CONFIG 0x26 |
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#define M98091_REG_DAI_PLAYBACK_LEVEL 0x27 |
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#define M98091_REG_DAI_PLAYBACK_LEVEL_EQ 0x28 |
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#define M98091_REG_LEFT_HP_MIXER 0x29 |
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#define M98091_REG_RIGHT_HP_MIXER 0x2A |
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#define M98091_REG_HP_CONTROL 0x2B |
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#define M98091_REG_LEFT_HP_VOLUME 0x2C |
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#define M98091_REG_RIGHT_HP_VOLUME 0x2D |
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#define M98091_REG_LEFT_SPK_MIXER 0x2E |
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#define M98091_REG_RIGHT_SPK_MIXER 0x2F |
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#define M98091_REG_SPK_CONTROL 0x30 |
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#define M98091_REG_LEFT_SPK_VOLUME 0x31 |
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#define M98091_REG_RIGHT_SPK_VOLUME 0x32 |
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#define M98091_REG_DRC_TIMING 0x33 |
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#define M98091_REG_DRC_COMPRESSOR 0x34 |
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#define M98091_REG_DRC_EXPANDER 0x35 |
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#define M98091_REG_DRC_GAIN 0x36 |
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#define M98091_REG_RCV_LOUTL_MIXER 0x37 |
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#define M98091_REG_RCV_LOUTL_CONTROL 0x38 |
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#define M98091_REG_RCV_LOUTL_VOLUME 0x39 |
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#define M98091_REG_LOUTR_MIXER 0x3A |
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#define M98091_REG_LOUTR_CONTROL 0x3B |
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#define M98091_REG_LOUTR_VOLUME 0x3C |
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#define M98091_REG_JACK_DETECT 0x3D |
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#define M98091_REG_INPUT_ENABLE 0x3E |
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#define M98091_REG_OUTPUT_ENABLE 0x3F |
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#define M98091_REG_LEVEL_CONTROL 0x40 |
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#define M98091_REG_DSP_FILTER_ENABLE 0x41 |
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#define M98091_REG_BIAS_CONTROL 0x42 |
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#define M98091_REG_DAC_CONTROL 0x43 |
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#define M98091_REG_ADC_CONTROL 0x44 |
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#define M98091_REG_DEVICE_SHUTDOWN 0x45 |
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#define M98091_REG_EQUALIZER_BASE 0x46 |
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#define M98091_REG_RECORD_BIQUAD_BASE 0xAF |
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#define M98091_REG_DMIC3_VOLUME 0xBE |
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#define M98091_REG_DMIC4_VOLUME 0xBF |
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#define M98091_REG_DMIC34_BQ_PREATTEN 0xC0 |
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#define M98091_REG_RECORD_TDM_SLOT 0xC1 |
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#define M98091_REG_SAMPLE_RATE 0xC2 |
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#define M98091_REG_DMIC34_BIQUAD_BASE 0xC3 |
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#define M98091_REG_REVISION_ID 0xFF |
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|
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/* MAX98090 Register Bit Fields */ |
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/* M98091_REG_SOFTWARE_RESET */ |
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#define M98091_SWRESET_MASK BIT(7) |
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|
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/* M98091_REG_QUICK_SAMPLE_RATE */ |
||||
#define M98091_SR_96K_MASK BIT(5) |
||||
#define M98091_SR_32K_MASK BIT(4) |
||||
#define M98091_SR_48K_MASK BIT(3) |
||||
#define M98091_SR_44K1_MASK BIT(2) |
||||
#define M98091_SR_16K_MASK BIT(1) |
||||
#define M98091_SR_8K_MASK BIT(0) |
||||
|
||||
/* M98091_REG_DAI_INTERFACE */ |
||||
#define M98091_RJ_M_MASK BIT(5) |
||||
#define M98091_RJ_S_MASK BIT(4) |
||||
#define M98091_LJ_M_MASK BIT(3) |
||||
#define M98091_LJ_S_MASK BIT(2) |
||||
#define M98091_I2S_M_MASK BIT(1) |
||||
#define M98091_I2S_S_MASK BIT(0) |
||||
|
||||
/* M98091_REG_SYSTEM_CLOCK */ |
||||
#define M98091_PSCLK_DISABLED (0 << 4) |
||||
#define M98091_PSCLK_DIV1 BIT(4) |
||||
#define M98091_PSCLK_DIV2 (2 << 4) |
||||
#define M98091_PSCLK_DIV4 (3 << 4) |
||||
|
||||
/* M98091_REG_MASTER_MODE */ |
||||
#define M98091_MAS_MASK BIT(7) |
||||
|
||||
/* M98091_REG_INTERFACE_FORMAT */ |
||||
#define M98091_RJ_MASK BIT(5) |
||||
#define M98091_WCI_MASK BIT(4) |
||||
#define M98091_BCI_MASK BIT(3) |
||||
#define M98091_DLY_MASK BIT(2) |
||||
#define M98091_WS_MASK (3 << 0) |
||||
#define M98091_16B_WS (0 << 0) |
||||
|
||||
/* M98091_REG_IO_CONFIGURATION */ |
||||
#define M98091_LTEN_MASK BIT(5) |
||||
#define M98091_LBEN_MASK BIT(4) |
||||
#define M98091_DMONO_MASK BIT(3) |
||||
#define M98091_HIZOFF_MASK BIT(2) |
||||
#define M98091_SDOEN_MASK BIT(1) |
||||
#define M98091_SDIEN_MASK BIT(0) |
||||
|
||||
/* M98091_REG_LEFT_HP_MIXER */ |
||||
#define M98091_MIXHPL_MIC2_MASK BIT(5) |
||||
#define M98091_MIXHPL_MIC1_MASK BIT(4) |
||||
#define M98091_MIXHPL_LINEB_MASK BIT(3) |
||||
#define M98091_MIXHPL_LINEA_MASK BIT(2) |
||||
#define M98091_MIXHPL_DACR_MASK BIT(1) |
||||
#define M98091_MIXHPL_DACL_MASK BIT(0) |
||||
#define M98091_MIXHPL_MASK (63 << 0) |
||||
|
||||
/* M98091_REG_RIGHT_HP_MIXER */ |
||||
#define M98091_MIXHPR_MIC2_MASK BIT(5) |
||||
#define M98091_MIXHPR_MIC1_MASK BIT(4) |
||||
#define M98091_MIXHPR_LINEB_MASK BIT(3) |
||||
#define M98091_MIXHPR_LINEA_MASK BIT(2) |
||||
#define M98091_MIXHPR_DACR_MASK BIT(1) |
||||
#define M98091_MIXHPR_DACL_MASK BIT(0) |
||||
#define M98091_MIXHPR_MASK (63 << 0) |
||||
|
||||
/* M98091_REG_HP_CONTROL */ |
||||
#define M98091_MIXHPRSEL_MASK BIT(5) |
||||
#define M98091_MIXHPLSEL_MASK BIT(4) |
||||
#define M98091_MIXHPRG_MASK (3 << 2) |
||||
#define M98091_MIXHPLG_MASK (3 << 0) |
||||
|
||||
/* M98091_REG_LEFT_HP_VOLUME */ |
||||
#define M98091_HPLM_MASK BIT(7) |
||||
#define M98091_HPVOLL_MASK (31 << 0) |
||||
|
||||
/* M98091_REG_LEFT_SPK_MIXER */ |
||||
#define M98091_MIXSPL_MIC2_MASK BIT(5) |
||||
#define M98091_MIXSPL_MIC1_MASK BIT(4) |
||||
#define M98091_MIXSPL_LINEB_MASK BIT(3) |
||||
#define M98091_MIXSPL_LINEA_MASK BIT(2) |
||||
#define M98091_MIXSPL_DACR_MASK BIT(1) |
||||
#define M98091_MIXSPL_DACL_MASK BIT(0) |
||||
#define M98091_MIXSPL_MASK (63 << 0) |
||||
|
||||
/* M98091_REG_RIGHT_SPK_MIXER */ |
||||
#define M98091_SPK_SLAVE_MASK BIT(6) |
||||
#define M98091_MIXSPR_MIC2_MASK BIT(5) |
||||
#define M98091_MIXSPR_MIC1_MASK BIT(4) |
||||
#define M98091_MIXSPR_LINEB_MASK BIT(3) |
||||
#define M98091_MIXSPR_LINEA_MASK BIT(2) |
||||
#define M98091_MIXSPR_DACR_MASK BIT(1) |
||||
#define M98091_MIXSPR_DACL_MASK BIT(0) |
||||
#define M98091_MIXSPR_MASK (63 << 0) |
||||
|
||||
/* M98091_REG_SPK_CONTROL */ |
||||
#define M98091_MIXSPRG_MASK (3 << 2) |
||||
#define M98091_MIXSPLG_MASK (3 << 0) |
||||
|
||||
/* M98091_REG_LEFT_SPK_VOLUME */ |
||||
#define M98091_SPLM_MASK BIT(7) |
||||
#define M98091_SPVOLL_MASK (63 << 0) |
||||
|
||||
/* M98091_REG_OUTPUT_ENABLE */ |
||||
#define M98091_HPREN_MASK BIT(7) |
||||
#define M98091_HPLEN_MASK BIT(6) |
||||
#define M98091_SPREN_MASK BIT(5) |
||||
#define M98091_SPLEN_MASK BIT(4) |
||||
#define M98091_RCVLEN_MASK BIT(3) |
||||
#define M98091_RCVREN_MASK BIT(2) |
||||
#define M98091_DAREN_MASK BIT(1) |
||||
#define M98091_DALEN_MASK BIT(0) |
||||
|
||||
/* M98091_REG_DEVICE_SHUTDOWN */ |
||||
#define M98091_SHDNN_MASK BIT(7) |
||||
|
||||
#define M98091_DEFAULT_VOLUME 0x2A |
||||
#define M98091_REVA 0x50 |
||||
|
||||
#endif |
||||
@ -0,0 +1,16 @@
@@ -0,0 +1,16 @@
|
||||
# Copyright (c) 2025 Silicon Signals Pvt. Ltd. |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
description: MAX98091 I2S Audio Codec |
||||
|
||||
compatible: "maxim,max98091" |
||||
|
||||
include: [i2c-device.yaml] |
||||
|
||||
properties: |
||||
reg: |
||||
required: true |
||||
mclk-frequency: |
||||
type: int |
||||
required: true |
||||
description: External MCLK frequency in Hz |
||||
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Reference in new issue