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xtensa: support for more than 32 interrupts 

This change add support for using more than 32 interrupts.

Signed-off-by: William Tambe <williamt@cadence.com>
pull/82801/merge
William Tambe 2 weeks ago committed by Dan Kalowsky
parent
dcdc7d315e
commit
abeccfec28
19 changed files with 564 additions and 113 deletions
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  1. 47
      arch/xtensa/core/irq_manage.c
  2. 61
      arch/xtensa/core/irq_offload.c
  3. 11
      arch/xtensa/core/startup/reset_vector.S
  4. 118
      arch/xtensa/core/vector_handlers.c
  5. 10
      arch/xtensa/core/xtensa_intgen.py
  6. 96
      arch/xtensa/core/xtensa_intgen.tmpl
  7. 131
      include/zephyr/arch/xtensa/irq.h
  8. 16
      soc/cdns/sample_controller32/include/_soc_inthandlers.h
  9. 16
      soc/cdns/xtensa_sample_controller/include/_soc_inthandlers.h
  10. 16
      soc/espressif/common/include/_soc_inthandlers.h
  11. 12
      soc/intel/intel_adsp/ace/_soc_inthandlers.h
  12. 16
      soc/intel/intel_adsp/cavs/_soc_inthandlers.h
  13. 16
      soc/nxp/imx/imx8/adsp/_soc_inthandlers.h
  14. 16
      soc/nxp/imx/imx8m/adsp/_soc_inthandlers.h
  15. 32
      soc/nxp/imx/imx8ulp/adsp/_soc_inthandlers.h
  16. 16
      soc/nxp/imx/imx8x/adsp/_soc_inthandlers.h
  17. 10
      soc/nxp/imxrt/imxrt5xx/f1/include/_soc_inthandlers.h
  18. 12
      soc/nxp/imxrt/imxrt6xx/hifi4/include/_soc_inthandlers.h
  19. 25
      subsys/testsuite/include/zephyr/interrupt_util.h

47
arch/xtensa/core/irq_manage.c
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@ -74,6 +74,28 @@ void z_irq_spurious(const void *arg)
__asm__ volatile("rsr.intenable %0" : "=r"(ie)); __asm__ volatile("rsr.intenable %0" : "=r"(ie));
LOG_ERR(" ** Spurious INTERRUPT(s) %p, INTENABLE = %p", LOG_ERR(" ** Spurious INTERRUPT(s) %p, INTENABLE = %p",
(void *)irqs, (void *)ie); (void *)irqs, (void *)ie);
#if XCHAL_NUM_INTERRUPTS > 32
__asm__ volatile("rsr.interrupt1 %0" : "=r"(irqs));
__asm__ volatile("rsr.intenable1 %0" : "=r"(ie));
LOG_ERR(" ** Spurious INTERRUPT1(s) %p, INTENABLE1 = %p",
(void *)irqs, (void *)ie);
#endif
#if XCHAL_NUM_INTERRUPTS > 64
__asm__ volatile("rsr.interrupt2 %0" : "=r"(irqs));
__asm__ volatile("rsr.intenable2 %0" : "=r"(ie));
LOG_ERR(" ** Spurious INTERRUPT2(s) %p, INTENABLE2 = %p",
(void *)irqs, (void *)ie);
#endif
#if XCHAL_NUM_INTERRUPTS > 96
__asm__ volatile("rsr.interrupt3 %0" : "=r"(irqs));
__asm__ volatile("rsr.intenable3 %0" : "=r"(ie));
LOG_ERR(" ** Spurious INTERRUPT3(s) %p, INTENABLE3 = %p",
(void *)irqs, (void *)ie);
#endif
xtensa_fatal_error(K_ERR_SPURIOUS_IRQ, NULL); xtensa_fatal_error(K_ERR_SPURIOUS_IRQ, NULL);
} }
@ -81,7 +103,30 @@ int xtensa_irq_is_enabled(unsigned int irq)
{ {
uint32_t ie; uint32_t ie;
#if XCHAL_NUM_INTERRUPTS > 32
switch (irq >> 5) {
case 0:
__asm__ volatile("rsr.intenable %0" : "=r"(ie));
break;
case 1:
__asm__ volatile("rsr.intenable1 %0" : "=r"(ie));
break;
#if XCHAL_NUM_INTERRUPTS > 64
case 2:
__asm__ volatile("rsr.intenable2 %0" : "=r"(ie));
break;
#endif
#if XCHAL_NUM_INTERRUPTS > 96
case 3:
__asm__ volatile("rsr.intenable3 %0" : "=r"(ie));
break;
#endif
default:
break;
}
#else
__asm__ volatile("rsr.intenable %0" : "=r"(ie)); __asm__ volatile("rsr.intenable %0" : "=r"(ie));
#endif
return (ie & (1 << irq)) != 0U; return (ie & (1 << (irq & 31U))) != 0U;
} }

61
arch/xtensa/core/irq_offload.c
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@ -31,10 +31,63 @@ void arch_irq_offload(irq_offload_routine_t routine, const void *parameter)
offload_params[cpu_id].fn = routine; offload_params[cpu_id].fn = routine;
offload_params[cpu_id].arg = parameter; offload_params[cpu_id].arg = parameter;
__asm__ volatile("rsr %0, INTENABLE" : "=r"(intenable)); #if XCHAL_NUM_INTERRUPTS > 32
intenable |= BIT(ZSR_IRQ_OFFLOAD_INT); switch ((ZSR_IRQ_OFFLOAD_INT) >> 5) {
__asm__ volatile("wsr %0, INTENABLE; wsr %0, INTSET; rsync" case 0:
:: "r"(intenable), "r"(BIT(ZSR_IRQ_OFFLOAD_INT))); __asm__ volatile("rsr.intenable %0" : "=r"(intenable));
break;
case 1:
__asm__ volatile("rsr.intenable1 %0" : "=r"(intenable));
break;
#if XCHAL_NUM_INTERRUPTS > 64
case 2:
__asm__ volatile("rsr.intenable2 %0" : "=r"(intenable));
break;
#endif
#if XCHAL_NUM_INTERRUPTS > 96
case 3:
__asm__ volatile("rsr.intenable3 %0" : "=r"(intenable));
break;
#endif
default:
break;
}
#else
__asm__ volatile("rsr.intenable %0" : "=r"(intenable));
#endif
intenable |= BIT((ZSR_IRQ_OFFLOAD_INT & 31U));
#if XCHAL_NUM_INTERRUPTS > 32
switch ((ZSR_IRQ_OFFLOAD_INT) >> 5) {
case 0:
__asm__ volatile("wsr.intenable %0; wsr.intset %0; rsync"
:: "r"(intenable), "r"(BIT((ZSR_IRQ_OFFLOAD_INT & 31U))));
break;
case 1:
__asm__ volatile("wsr.intenable1 %0; wsr.intset1 %0; rsync"
:: "r"(intenable), "r"(BIT((ZSR_IRQ_OFFLOAD_INT & 31U))));
break;
#if XCHAL_NUM_INTERRUPTS > 64
case 2:
__asm__ volatile("wsr.intenable2 %0; wsr.intset2 %0; rsync"
:: "r"(intenable), "r"(BIT((ZSR_IRQ_OFFLOAD_INT & 31U))));
break;
#endif
#if XCHAL_NUM_INTERRUPTS > 96
case 3:
__asm__ volatile("wsr.intenable3 %0; wsr.intset3 %0; rsync"
:: "r"(intenable), "r"(BIT((ZSR_IRQ_OFFLOAD_INT & 31U))));
break;
#endif
default:
break;
}
#else
__asm__ volatile("wsr.intenable %0; wsr.intset %0; rsync"
:: "r"(intenable), "r"(BIT((ZSR_IRQ_OFFLOAD_INT & 31U))));
#endif
arch_irq_unlock(key); arch_irq_unlock(key);
} }

11
arch/xtensa/core/startup/reset_vector.S
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@ -150,7 +150,16 @@ _ResetHandler:
/* make sure that interrupts are shut off (*before* we lower /* make sure that interrupts are shut off (*before* we lower
* PS.INTLEVEL and PS.EXCM!) * PS.INTLEVEL and PS.EXCM!)
*/ */
wsr a0, INTENABLE wsr.intenable a0
#if (XCHAL_NUM_INTERRUPTS > 32)
wsr.intenable1 a0
#endif
#if (XCHAL_NUM_INTERRUPTS > 64)
wsr.intenable2 a0
#endif
#if (XCHAL_NUM_INTERRUPTS > 96)
wsr.intenable3 a0
#endif
#endif #endif
#if !XCHAL_HAVE_FULL_RESET #if !XCHAL_HAVE_FULL_RESET

118
arch/xtensa/core/vector_handlers.c
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@ -286,20 +286,116 @@ static inline void *return_to(void *interrupted)
* This may be unused depending on number of interrupt levels * This may be unused depending on number of interrupt levels
* supported by the SoC. * supported by the SoC.
*/ */
#define DEF_INT_C_HANDLER(l) \
__unused void *xtensa_int##l##_c(void *interrupted_stack) \ #if XCHAL_NUM_INTERRUPTS <= 32
{ \ #define DEF_INT_C_HANDLER(l) \
uint32_t irqs, intenable, m; \ __unused void *xtensa_int##l##_c(void *interrupted_stack) \
usage_stop(); \ { \
__asm__ volatile("rsr.interrupt %0" : "=r"(irqs)); \ uint32_t irqs, intenable, m; \
usage_stop(); \
__asm__ volatile("rsr.interrupt %0" : "=r"(irqs)); \
__asm__ volatile("rsr.intenable %0" : "=r"(intenable)); \ __asm__ volatile("rsr.intenable %0" : "=r"(intenable)); \
irqs &= intenable; \ irqs &= intenable; \
while ((m = _xtensa_handle_one_int##l(irqs))) { \ while ((m = _xtensa_handle_one_int##l(0, irqs))) { \
irqs ^= m; \ irqs ^= m; \
__asm__ volatile("wsr.intclear %0" : : "r"(m)); \ __asm__ volatile("wsr.intclear %0" : : "r"(m)); \
} \ } \
return return_to(interrupted_stack); \ return return_to(interrupted_stack); \
}
#endif /* XCHAL_NUM_INTERRUPTS <= 32 */
#if XCHAL_NUM_INTERRUPTS > 32 && XCHAL_NUM_INTERRUPTS <= 64
#define DEF_INT_C_HANDLER(l) \
__unused void *xtensa_int##l##_c(void *interrupted_stack) \
{ \
uint32_t irqs, intenable, m; \
usage_stop(); \
__asm__ volatile("rsr.interrupt %0" : "=r"(irqs)); \
__asm__ volatile("rsr.intenable %0" : "=r"(intenable)); \
irqs &= intenable; \
while ((m = _xtensa_handle_one_int##l(0, irqs))) { \
irqs ^= m; \
__asm__ volatile("wsr.intclear %0" : : "r"(m)); \
} \
__asm__ volatile("rsr.interrupt1 %0" : "=r"(irqs)); \
__asm__ volatile("rsr.intenable1 %0" : "=r"(intenable)); \
irqs &= intenable; \
while ((m = _xtensa_handle_one_int##l(1, irqs))) { \
irqs ^= m; \
__asm__ volatile("wsr.intclear1 %0" : : "r"(m)); \
} \
return return_to(interrupted_stack); \
}
#endif /* XCHAL_NUM_INTERRUPTS > 32 && XCHAL_NUM_INTERRUPTS <= 64 */
#if XCHAL_NUM_INTERRUPTS > 64 && XCHAL_NUM_INTERRUPTS <= 96
#define DEF_INT_C_HANDLER(l) \
__unused void *xtensa_int##l##_c(void *interrupted_stack) \
{ \
uint32_t irqs, intenable, m; \
usage_stop(); \
__asm__ volatile("rsr.interrupt %0" : "=r"(irqs)); \
__asm__ volatile("rsr.intenable %0" : "=r"(intenable)); \
irqs &= intenable; \
while ((m = _xtensa_handle_one_int##l(0, irqs))) { \
irqs ^= m; \
__asm__ volatile("wsr.intclear %0" : : "r"(m)); \
} \
__asm__ volatile("rsr.interrupt1 %0" : "=r"(irqs)); \
__asm__ volatile("rsr.intenable1 %0" : "=r"(intenable)); \
irqs &= intenable; \
while ((m = _xtensa_handle_one_int##l(1, irqs))) { \
irqs ^= m; \
__asm__ volatile("wsr.intclear1 %0" : : "r"(m)); \
} \
__asm__ volatile("rsr.interrupt2 %0" : "=r"(irqs)); \
__asm__ volatile("rsr.intenable2 %0" : "=r"(intenable)); \
irqs &= intenable; \
while ((m = _xtensa_handle_one_int##l(2, irqs))) { \
irqs ^= m; \
__asm__ volatile("wsr.intclear2 %0" : : "r"(m)); \
} \
return return_to(interrupted_stack); \
}
#endif /* XCHAL_NUM_INTERRUPTS > 64 && XCHAL_NUM_INTERRUPTS <= 96 */
#if XCHAL_NUM_INTERRUPTS > 96
#define DEF_INT_C_HANDLER(l) \
__unused void *xtensa_int##l##_c(void *interrupted_stack) \
{ \
uint32_t irqs, intenable, m; \
usage_stop(); \
__asm__ volatile("rsr.interrupt %0" : "=r"(irqs)); \
__asm__ volatile("rsr.intenable %0" : "=r"(intenable)); \
irqs &= intenable; \
while ((m = _xtensa_handle_one_int##l(0, irqs))) { \
irqs ^= m; \
__asm__ volatile("wsr.intclear %0" : : "r"(m)); \
} \
__asm__ volatile("rsr.interrupt1 %0" : "=r"(irqs)); \
__asm__ volatile("rsr.intenable1 %0" : "=r"(intenable)); \
irqs &= intenable; \
while ((m = _xtensa_handle_one_int##l(1, irqs))) { \
irqs ^= m; \
__asm__ volatile("wsr.intclear1 %0" : : "r"(m)); \
} \
__asm__ volatile("rsr.interrupt2 %0" : "=r"(irqs)); \
__asm__ volatile("rsr.intenable2 %0" : "=r"(intenable)); \
irqs &= intenable; \
while ((m = _xtensa_handle_one_int##l(2, irqs))) { \
irqs ^= m; \
__asm__ volatile("wsr.intclear2 %0" : : "r"(m)); \
} \
__asm__ volatile("rsr.interrupt3 %0" : "=r"(irqs)); \
__asm__ volatile("rsr.intenable3 %0" : "=r"(intenable)); \
irqs &= intenable; \
while ((m = _xtensa_handle_one_int##l(3, irqs))) { \
irqs ^= m; \
__asm__ volatile("wsr.intclear3 %0" : : "r"(m)); \
} \
return return_to(interrupted_stack); \
} }
#endif /* XCHAL_NUM_INTERRUPTS > 96 */
#if XCHAL_HAVE_NMI #if XCHAL_HAVE_NMI
#define MAX_INTR_LEVEL XCHAL_NMILEVEL #define MAX_INTR_LEVEL XCHAL_NMILEVEL

10
arch/xtensa/core/xtensa_intgen.py
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@ -117,7 +117,8 @@ for lvl in range(0, max+1):
# Emit the handlers # Emit the handlers
for lvl in ints_by_lvl: for lvl in ints_by_lvl:
cprint("static inline int _xtensa_handle_one_int" + str(lvl) + "(unsigned int mask)") cprint("static inline int _xtensa_handle_one_int" +
str(lvl) + "(unsigned int set, unsigned int mask)")
cprint("{") cprint("{")
if not ints_by_lvl[lvl]: if not ints_by_lvl[lvl]:
@ -128,11 +129,14 @@ for lvl in ints_by_lvl:
cprint("int irq;") cprint("int irq;")
print("") print("")
emit_int_handler(sorted(ints_by_lvl[lvl])) if int(len(ints_by_lvl[lvl])) > 32:
emit_int_handler((sorted(ints_by_lvl[lvl]))[0:31])
else:
emit_int_handler(sorted(ints_by_lvl[lvl]))
cprint("return 0;") cprint("return 0;")
cprint("handle_irq:") cprint("handle_irq:")
cprint("_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);") cprint("_sw_isr_table[set * 32 + irq].isr(_sw_isr_table[set * 32 + irq].arg);")
cprint("return mask;") cprint("return mask;")
cprint("}") cprint("}")
cprint("") cprint("")

96
arch/xtensa/core/xtensa_intgen.tmpl
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@ -41,3 +41,99 @@ __xtensa_int_level_magic__ 28 XCHAL_INT28_LEVEL
__xtensa_int_level_magic__ 29 XCHAL_INT29_LEVEL __xtensa_int_level_magic__ 29 XCHAL_INT29_LEVEL
__xtensa_int_level_magic__ 30 XCHAL_INT30_LEVEL __xtensa_int_level_magic__ 30 XCHAL_INT30_LEVEL
__xtensa_int_level_magic__ 31 XCHAL_INT31_LEVEL __xtensa_int_level_magic__ 31 XCHAL_INT31_LEVEL
__xtensa_int_level_magic__ 32 XCHAL_INT32_LEVEL
__xtensa_int_level_magic__ 33 XCHAL_INT33_LEVEL
__xtensa_int_level_magic__ 34 XCHAL_INT34_LEVEL
__xtensa_int_level_magic__ 35 XCHAL_INT35_LEVEL
__xtensa_int_level_magic__ 36 XCHAL_INT36_LEVEL
__xtensa_int_level_magic__ 37 XCHAL_INT37_LEVEL
__xtensa_int_level_magic__ 38 XCHAL_INT38_LEVEL
__xtensa_int_level_magic__ 39 XCHAL_INT39_LEVEL
__xtensa_int_level_magic__ 40 XCHAL_INT40_LEVEL
__xtensa_int_level_magic__ 41 XCHAL_INT41_LEVEL
__xtensa_int_level_magic__ 42 XCHAL_INT42_LEVEL
__xtensa_int_level_magic__ 43 XCHAL_INT43_LEVEL
__xtensa_int_level_magic__ 44 XCHAL_INT44_LEVEL
__xtensa_int_level_magic__ 45 XCHAL_INT45_LEVEL
__xtensa_int_level_magic__ 46 XCHAL_INT46_LEVEL
__xtensa_int_level_magic__ 47 XCHAL_INT47_LEVEL
__xtensa_int_level_magic__ 48 XCHAL_INT48_LEVEL
__xtensa_int_level_magic__ 49 XCHAL_INT49_LEVEL
__xtensa_int_level_magic__ 50 XCHAL_INT50_LEVEL
__xtensa_int_level_magic__ 51 XCHAL_INT51_LEVEL
__xtensa_int_level_magic__ 52 XCHAL_INT52_LEVEL
__xtensa_int_level_magic__ 53 XCHAL_INT53_LEVEL
__xtensa_int_level_magic__ 54 XCHAL_INT54_LEVEL
__xtensa_int_level_magic__ 55 XCHAL_INT55_LEVEL
__xtensa_int_level_magic__ 56 XCHAL_INT56_LEVEL
__xtensa_int_level_magic__ 57 XCHAL_INT57_LEVEL
__xtensa_int_level_magic__ 58 XCHAL_INT58_LEVEL
__xtensa_int_level_magic__ 59 XCHAL_INT59_LEVEL
__xtensa_int_level_magic__ 60 XCHAL_INT60_LEVEL
__xtensa_int_level_magic__ 61 XCHAL_INT61_LEVEL
__xtensa_int_level_magic__ 62 XCHAL_INT62_LEVEL
__xtensa_int_level_magic__ 63 XCHAL_INT63_LEVEL
__xtensa_int_level_magic__ 64 XCHAL_INT64_LEVEL
__xtensa_int_level_magic__ 65 XCHAL_INT65_LEVEL
__xtensa_int_level_magic__ 66 XCHAL_INT66_LEVEL
__xtensa_int_level_magic__ 67 XCHAL_INT67_LEVEL
__xtensa_int_level_magic__ 68 XCHAL_INT68_LEVEL
__xtensa_int_level_magic__ 69 XCHAL_INT69_LEVEL
__xtensa_int_level_magic__ 70 XCHAL_INT70_LEVEL
__xtensa_int_level_magic__ 71 XCHAL_INT71_LEVEL
__xtensa_int_level_magic__ 72 XCHAL_INT72_LEVEL
__xtensa_int_level_magic__ 73 XCHAL_INT73_LEVEL
__xtensa_int_level_magic__ 74 XCHAL_INT74_LEVEL
__xtensa_int_level_magic__ 75 XCHAL_INT75_LEVEL
__xtensa_int_level_magic__ 76 XCHAL_INT76_LEVEL
__xtensa_int_level_magic__ 77 XCHAL_INT77_LEVEL
__xtensa_int_level_magic__ 78 XCHAL_INT78_LEVEL
__xtensa_int_level_magic__ 79 XCHAL_INT79_LEVEL
__xtensa_int_level_magic__ 80 XCHAL_INT80_LEVEL
__xtensa_int_level_magic__ 81 XCHAL_INT81_LEVEL
__xtensa_int_level_magic__ 82 XCHAL_INT82_LEVEL
__xtensa_int_level_magic__ 83 XCHAL_INT83_LEVEL
__xtensa_int_level_magic__ 84 XCHAL_INT84_LEVEL
__xtensa_int_level_magic__ 85 XCHAL_INT85_LEVEL
__xtensa_int_level_magic__ 86 XCHAL_INT86_LEVEL
__xtensa_int_level_magic__ 87 XCHAL_INT87_LEVEL
__xtensa_int_level_magic__ 88 XCHAL_INT88_LEVEL
__xtensa_int_level_magic__ 89 XCHAL_INT89_LEVEL
__xtensa_int_level_magic__ 90 XCHAL_INT90_LEVEL
__xtensa_int_level_magic__ 91 XCHAL_INT91_LEVEL
__xtensa_int_level_magic__ 92 XCHAL_INT92_LEVEL
__xtensa_int_level_magic__ 93 XCHAL_INT93_LEVEL
__xtensa_int_level_magic__ 94 XCHAL_INT94_LEVEL
__xtensa_int_level_magic__ 95 XCHAL_INT95_LEVEL
__xtensa_int_level_magic__ 96 XCHAL_INT96_LEVEL
__xtensa_int_level_magic__ 97 XCHAL_INT97_LEVEL
__xtensa_int_level_magic__ 98 XCHAL_INT98_LEVEL
__xtensa_int_level_magic__ 99 XCHAL_INT99_LEVEL
__xtensa_int_level_magic__ 100 XCHAL_INT100_LEVEL
__xtensa_int_level_magic__ 101 XCHAL_INT101_LEVEL
__xtensa_int_level_magic__ 102 XCHAL_INT102_LEVEL
__xtensa_int_level_magic__ 103 XCHAL_INT103_LEVEL
__xtensa_int_level_magic__ 104 XCHAL_INT104_LEVEL
__xtensa_int_level_magic__ 105 XCHAL_INT105_LEVEL
__xtensa_int_level_magic__ 106 XCHAL_INT106_LEVEL
__xtensa_int_level_magic__ 107 XCHAL_INT107_LEVEL
__xtensa_int_level_magic__ 108 XCHAL_INT108_LEVEL
__xtensa_int_level_magic__ 109 XCHAL_INT109_LEVEL
__xtensa_int_level_magic__ 110 XCHAL_INT110_LEVEL
__xtensa_int_level_magic__ 111 XCHAL_INT111_LEVEL
__xtensa_int_level_magic__ 112 XCHAL_INT112_LEVEL
__xtensa_int_level_magic__ 113 XCHAL_INT113_LEVEL
__xtensa_int_level_magic__ 114 XCHAL_INT114_LEVEL
__xtensa_int_level_magic__ 115 XCHAL_INT115_LEVEL
__xtensa_int_level_magic__ 116 XCHAL_INT116_LEVEL
__xtensa_int_level_magic__ 117 XCHAL_INT117_LEVEL
__xtensa_int_level_magic__ 118 XCHAL_INT118_LEVEL
__xtensa_int_level_magic__ 119 XCHAL_INT119_LEVEL
__xtensa_int_level_magic__ 120 XCHAL_INT120_LEVEL
__xtensa_int_level_magic__ 121 XCHAL_INT121_LEVEL
__xtensa_int_level_magic__ 122 XCHAL_INT122_LEVEL
__xtensa_int_level_magic__ 123 XCHAL_INT123_LEVEL
__xtensa_int_level_magic__ 124 XCHAL_INT124_LEVEL
__xtensa_int_level_magic__ 125 XCHAL_INT125_LEVEL
__xtensa_int_level_magic__ 126 XCHAL_INT126_LEVEL
__xtensa_int_level_magic__ 127 XCHAL_INT127_LEVEL

131
include/zephyr/arch/xtensa/irq.h
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@ -18,7 +18,7 @@
*/ */
/* /*
* Call this function to enable the specified interrupts. * Call these functions to enable the specified interrupts.
* *
* mask - Bit mask of interrupts to be enabled. * mask - Bit mask of interrupts to be enabled.
*/ */
@ -30,10 +30,40 @@ static inline void z_xt_ints_on(unsigned int mask)
val |= mask; val |= mask;
__asm__ volatile("wsr.intenable %0; rsync" : : "r"(val)); __asm__ volatile("wsr.intenable %0; rsync" : : "r"(val));
} }
#if XCHAL_NUM_INTERRUPTS > 32
static inline void z_xt_ints1_on(unsigned int mask)
{
int val;
__asm__ volatile("rsr.intenable1 %0" : "=r"(val));
val |= mask;
__asm__ volatile("wsr.intenable1 %0; rsync" : : "r"(val));
}
#endif
#if XCHAL_NUM_INTERRUPTS > 64
static inline void z_xt_ints2_on(unsigned int mask)
{
int val;
__asm__ volatile("rsr.intenable2 %0" : "=r"(val));
val |= mask;
__asm__ volatile("wsr.intenable2 %0; rsync" : : "r"(val));
}
#endif
#if XCHAL_NUM_INTERRUPTS > 96
static inline void z_xt_ints3_on(unsigned int mask)
{
int val;
__asm__ volatile("rsr.intenable3 %0" : "=r"(val));
val |= mask;
__asm__ volatile("wsr.intenable3 %0; rsync" : : "r"(val));
}
#endif
/* /*
* Call this function to disable the specified interrupts. * Call these functions to disable the specified interrupts.
* *
* mask - Bit mask of interrupts to be disabled. * mask - Bit mask of interrupts to be disabled.
*/ */
@ -45,10 +75,40 @@ static inline void z_xt_ints_off(unsigned int mask)
val &= ~mask; val &= ~mask;
__asm__ volatile("wsr.intenable %0; rsync" : : "r"(val)); __asm__ volatile("wsr.intenable %0; rsync" : : "r"(val));
} }
#if XCHAL_NUM_INTERRUPTS > 32
static inline void z_xt_ints1_off(unsigned int mask)
{
int val;
__asm__ volatile("rsr.intenable1 %0" : "=r"(val));
val &= ~mask;
__asm__ volatile("wsr.intenable1 %0; rsync" : : "r"(val));
}
#endif
#if XCHAL_NUM_INTERRUPTS > 64
static inline void z_xt_ints2_off(unsigned int mask)
{
int val;
__asm__ volatile("rsr.intenable2 %0" : "=r"(val));
val &= ~mask;
__asm__ volatile("wsr.intenable2 %0; rsync" : : "r"(val));
}
#endif
#if XCHAL_NUM_INTERRUPTS > 96
static inline void z_xt_ints3_off(unsigned int mask)
{
int val;
__asm__ volatile("rsr.intenable3 %0" : "=r"(val));
val &= ~mask;
__asm__ volatile("wsr.intenable3 %0; rsync" : : "r"(val));
}
#endif
/* /*
* Call this function to set the specified (s/w) interrupt. * Call these functions to set the specified (s/w) interrupt.
*/ */
static inline void z_xt_set_intset(unsigned int arg) static inline void z_xt_set_intset(unsigned int arg)
{ {
@ -58,6 +118,25 @@ static inline void z_xt_set_intset(unsigned int arg)
ARG_UNUSED(arg); ARG_UNUSED(arg);
#endif #endif
} }
#if XCHAL_NUM_INTERRUPTS > 32
static inline void z_xt_set_intset1(unsigned int arg)
{
__asm__ volatile("wsr.intset1 %0; rsync" : : "r"(arg));
}
#endif
#if XCHAL_NUM_INTERRUPTS > 64
static inline void z_xt_set_intset2(unsigned int arg)
{
__asm__ volatile("wsr.intset2 %0; rsync" : : "r"(arg));
}
#endif
#if XCHAL_NUM_INTERRUPTS > 96
static inline void z_xt_set_intset3(unsigned int arg)
{
__asm__ volatile("wsr.intset3 %0; rsync" : : "r"(arg));
}
#endif
/** /**
* INTERNAL_HIDDEN @endcond * INTERNAL_HIDDEN @endcond
@ -117,7 +196,30 @@ extern int z_soc_irq_connect_dynamic(unsigned int irq, unsigned int priority,
*/ */
static ALWAYS_INLINE void xtensa_irq_enable(uint32_t irq) static ALWAYS_INLINE void xtensa_irq_enable(uint32_t irq)
{ {
#if XCHAL_NUM_INTERRUPTS > 32
switch (irq >> 5) {
case 0:
z_xt_ints_on(1 << irq);
break;
case 1:
z_xt_ints1_on(1 << irq);
break;
#if XCHAL_NUM_INTERRUPTS > 64
case 2:
z_xt_ints2_on(1 << irq);
break;
#endif
#if XCHAL_NUM_INTERRUPTS > 96
case 3:
z_xt_ints3_on(1 << irq);
break;
#endif
default:
break;
}
#else
z_xt_ints_on(1 << irq); z_xt_ints_on(1 << irq);
#endif
} }
/** /**
@ -127,7 +229,30 @@ static ALWAYS_INLINE void xtensa_irq_enable(uint32_t irq)
*/ */
static ALWAYS_INLINE void xtensa_irq_disable(uint32_t irq) static ALWAYS_INLINE void xtensa_irq_disable(uint32_t irq)
{ {
#if XCHAL_NUM_INTERRUPTS > 32
switch (irq >> 5) {
case 0:
z_xt_ints_off(1 << irq);
break;
case 1:
z_xt_ints1_off(1 << irq);
break;
#if XCHAL_NUM_INTERRUPTS > 64
case 2:
z_xt_ints2_off(1 << irq);
break;
#endif
#if XCHAL_NUM_INTERRUPTS > 96
case 3:
z_xt_ints3_off(1 << irq);
break;
#endif
default:
break;
}
#else
z_xt_ints_off(1 << irq); z_xt_ints_off(1 << irq);
#endif
} }
/** Implementation of @ref arch_irq_lock. */ /** Implementation of @ref arch_irq_lock. */

16
soc/cdns/sample_controller32/include/_soc_inthandlers.h
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@ -90,7 +90,7 @@
#error core-isa.h interrupt level does not match dispatcher! #error core-isa.h interrupt level does not match dispatcher!
#endif #endif
static inline int _xtensa_handle_one_int1(unsigned int mask) static inline int _xtensa_handle_one_int1(unsigned int set, unsigned int mask)
{ {
int irq; int irq;
@ -193,7 +193,7 @@ handle_irq:
return mask; return mask;
} }
static inline int _xtensa_handle_one_int2(unsigned int mask) static inline int _xtensa_handle_one_int2(unsigned int set, unsigned int mask)
{ {
int irq; int irq;
@ -208,7 +208,7 @@ handle_irq:
return mask; return mask;
} }
static inline int _xtensa_handle_one_int3(unsigned int mask) static inline int _xtensa_handle_one_int3(unsigned int set, unsigned int mask)
{ {
int irq; int irq;
@ -241,7 +241,7 @@ handle_irq:
return mask; return mask;
} }
static inline int _xtensa_handle_one_int4(unsigned int mask) static inline int _xtensa_handle_one_int4(unsigned int set, unsigned int mask)
{ {
int irq; int irq;
@ -256,7 +256,7 @@ handle_irq:
return mask; return mask;
} }
static inline int _xtensa_handle_one_int5(unsigned int mask) static inline int _xtensa_handle_one_int5(unsigned int set, unsigned int mask)
{ {
int irq; int irq;
@ -271,7 +271,7 @@ handle_irq:
return mask; return mask;
} }
static inline int _xtensa_handle_one_int7(unsigned int mask) static inline int _xtensa_handle_one_int7(unsigned int set, unsigned int mask)
{ {
int irq; int irq;
@ -286,11 +286,11 @@ handle_irq:
return mask; return mask;
} }
static inline int _xtensa_handle_one_int0(unsigned int mask) static inline int _xtensa_handle_one_int0(unsigned int set, unsigned int mask)
{ {
return 0; return 0;
} }
static inline int _xtensa_handle_one_int6(unsigned int mask) static inline int _xtensa_handle_one_int6(unsigned int set, unsigned int mask)
{ {
return 0; return 0;
} }

16
soc/cdns/xtensa_sample_controller/include/_soc_inthandlers.h
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@ -80,12 +80,12 @@
#error core-isa.h interrupt level does not match dispatcher! #error core-isa.h interrupt level does not match dispatcher!
#endif #endif
static inline int _xtensa_handle_one_int0(unsigned int mask) static inline int _xtensa_handle_one_int0(unsigned int set, unsigned int mask)
{ {
return 0; return 0;
} }
static inline int _xtensa_handle_one_int1(unsigned int mask) static inline int _xtensa_handle_one_int1(unsigned int set, unsigned int mask)
{ {
if (mask & 0x7f) { if (mask & 0x7f) {
if (mask & 0x7) { if (mask & 0x7) {
@ -189,7 +189,7 @@ static inline int _xtensa_handle_one_int1(unsigned int mask)
return 0; return 0;
} }
static inline int _xtensa_handle_one_int2(unsigned int mask) static inline int _xtensa_handle_one_int2(unsigned int set, unsigned int mask)
{ {
if (mask & (1 << 8)) { if (mask & (1 << 8)) {
const struct _isr_table_entry *e = &_sw_isr_table[8]; const struct _isr_table_entry *e = &_sw_isr_table[8];
@ -200,7 +200,7 @@ static inline int _xtensa_handle_one_int2(unsigned int mask)
return 0; return 0;
} }
static inline int _xtensa_handle_one_int3(unsigned int mask) static inline int _xtensa_handle_one_int3(unsigned int set, unsigned int mask)
{ {
if (mask & 0x600) { if (mask & 0x600) {
if (mask & (1 << 9)) { if (mask & (1 << 9)) {
@ -232,7 +232,7 @@ static inline int _xtensa_handle_one_int3(unsigned int mask)
return 0; return 0;
} }
static inline int _xtensa_handle_one_int4(unsigned int mask) static inline int _xtensa_handle_one_int4(unsigned int set, unsigned int mask)
{ {
if (mask & (1 << 12)) { if (mask & (1 << 12)) {
const struct _isr_table_entry *e = &_sw_isr_table[12]; const struct _isr_table_entry *e = &_sw_isr_table[12];
@ -243,7 +243,7 @@ static inline int _xtensa_handle_one_int4(unsigned int mask)
return 0; return 0;
} }
static inline int _xtensa_handle_one_int5(unsigned int mask) static inline int _xtensa_handle_one_int5(unsigned int set, unsigned int mask)
{ {
if (mask & (1 << 13)) { if (mask & (1 << 13)) {
const struct _isr_table_entry *e = &_sw_isr_table[13]; const struct _isr_table_entry *e = &_sw_isr_table[13];
@ -254,12 +254,12 @@ static inline int _xtensa_handle_one_int5(unsigned int mask)
return 0; return 0;
} }
static inline int _xtensa_handle_one_int6(unsigned int mask) static inline int _xtensa_handle_one_int6(unsigned int set, unsigned int mask)
{ {
return 0; return 0;
} }
static inline int _xtensa_handle_one_int7(unsigned int mask) static inline int _xtensa_handle_one_int7(unsigned int set, unsigned int mask)
{ {
if (mask & (1 << 14)) { if (mask & (1 << 14)) {
const struct _isr_table_entry *e = &_sw_isr_table[14]; const struct _isr_table_entry *e = &_sw_isr_table[14];

16
soc/espressif/common/include/_soc_inthandlers.h
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@ -117,7 +117,7 @@
#error core-isa.h interrupt level does not match dispatcher! #error core-isa.h interrupt level does not match dispatcher!
#endif #endif
static inline int _xtensa_handle_one_int1(unsigned int mask) static inline int _xtensa_handle_one_int1(unsigned int set, unsigned int mask)
{ {
int irq; int irq;
@ -220,7 +220,7 @@ handle_irq:
return mask; return mask;
} }
static inline int _xtensa_handle_one_int3(unsigned int mask) static inline int _xtensa_handle_one_int3(unsigned int set, unsigned int mask)
{ {
int irq; int irq;
@ -263,7 +263,7 @@ handle_irq:
return mask; return mask;
} }
static inline int _xtensa_handle_one_int7(unsigned int mask) static inline int _xtensa_handle_one_int7(unsigned int set, unsigned int mask)
{ {
int irq; int irq;
@ -278,7 +278,7 @@ handle_irq:
return mask; return mask;
} }
static inline int _xtensa_handle_one_int5(unsigned int mask) static inline int _xtensa_handle_one_int5(unsigned int set, unsigned int mask)
{ {
int irq; int irq;
@ -303,7 +303,7 @@ handle_irq:
return mask; return mask;
} }
static inline int _xtensa_handle_one_int2(unsigned int mask) static inline int _xtensa_handle_one_int2(unsigned int set, unsigned int mask)
{ {
int irq; int irq;
@ -328,7 +328,7 @@ handle_irq:
return mask; return mask;
} }
static inline int _xtensa_handle_one_int4(unsigned int mask) static inline int _xtensa_handle_one_int4(unsigned int set, unsigned int mask)
{ {
int irq; int irq;
@ -361,11 +361,11 @@ handle_irq:
return mask; return mask;
} }
static inline int _xtensa_handle_one_int0(unsigned int mask) static inline int _xtensa_handle_one_int0(unsigned int set, unsigned int mask)
{ {
return 0; return 0;
} }
static inline int _xtensa_handle_one_int6(unsigned int mask) static inline int _xtensa_handle_one_int6(unsigned int set, unsigned int mask)
{ {
return 0; return 0;
} }

12
soc/intel/intel_adsp/ace/_soc_inthandlers.h
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@ -45,7 +45,7 @@
#error core-isa.h interrupt level does not match dispatcher! #error core-isa.h interrupt level does not match dispatcher!
#endif #endif
static inline int _xtensa_handle_one_int1(unsigned int mask) static inline int _xtensa_handle_one_int1(unsigned int set, unsigned int mask)
{ {
int irq; int irq;
@ -65,7 +65,7 @@ handle_irq:
return mask; return mask;
} }
static inline int _xtensa_handle_one_int2(unsigned int mask) static inline int _xtensa_handle_one_int2(unsigned int set, unsigned int mask)
{ {
int irq; int irq;
@ -90,7 +90,7 @@ handle_irq:
return mask; return mask;
} }
static inline int _xtensa_handle_one_int3(unsigned int mask) static inline int _xtensa_handle_one_int3(unsigned int set, unsigned int mask)
{ {
int irq; int irq;
@ -115,7 +115,7 @@ handle_irq:
return mask; return mask;
} }
static inline int _xtensa_handle_one_int5(unsigned int mask) static inline int _xtensa_handle_one_int5(unsigned int set, unsigned int mask)
{ {
/* It is a Non-maskable interrupt handler. /* It is a Non-maskable interrupt handler.
* The non-maskable interrupt have no corresponding bit in INTERRUPT and INTENABLE registers * The non-maskable interrupt have no corresponding bit in INTERRUPT and INTENABLE registers
@ -125,11 +125,11 @@ static inline int _xtensa_handle_one_int5(unsigned int mask)
return 0; return 0;
} }
static inline int _xtensa_handle_one_int0(unsigned int mask) static inline int _xtensa_handle_one_int0(unsigned int set, unsigned int mask)
{ {
return 0; return 0;
} }
static inline int _xtensa_handle_one_int4(unsigned int mask) static inline int _xtensa_handle_one_int4(unsigned int set, unsigned int mask)
{ {
return 0; return 0;
} }

16
soc/intel/intel_adsp/cavs/_soc_inthandlers.h
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@ -82,7 +82,7 @@
#error core-isa.h interrupt level does not match dispatcher! #error core-isa.h interrupt level does not match dispatcher!
#endif #endif
static inline int _xtensa_handle_one_int1(unsigned int mask) static inline int _xtensa_handle_one_int1(unsigned int set, unsigned int mask)
{ {
int irq; int irq;
@ -115,7 +115,7 @@ handle_irq:
return mask; return mask;
} }
static inline int _xtensa_handle_one_int2(unsigned int mask) static inline int _xtensa_handle_one_int2(unsigned int set, unsigned int mask)
{ {
int irq; int irq;
@ -148,7 +148,7 @@ handle_irq:
return mask; return mask;
} }
static inline int _xtensa_handle_one_int3(unsigned int mask) static inline int _xtensa_handle_one_int3(unsigned int set, unsigned int mask)
{ {
int irq; int irq;
@ -181,7 +181,7 @@ handle_irq:
return mask; return mask;
} }
static inline int _xtensa_handle_one_int4(unsigned int mask) static inline int _xtensa_handle_one_int4(unsigned int set, unsigned int mask)
{ {
int irq; int irq;
@ -206,7 +206,7 @@ handle_irq:
return mask; return mask;
} }
static inline int _xtensa_handle_one_int5(unsigned int mask) static inline int _xtensa_handle_one_int5(unsigned int set, unsigned int mask)
{ {
int irq; int irq;
@ -244,7 +244,7 @@ handle_irq:
return mask; return mask;
} }
static inline int _xtensa_handle_one_int7(unsigned int mask) static inline int _xtensa_handle_one_int7(unsigned int set, unsigned int mask)
{ {
int irq; int irq;
@ -259,11 +259,11 @@ handle_irq:
return mask; return mask;
} }
static inline int _xtensa_handle_one_int0(unsigned int mask) static inline int _xtensa_handle_one_int0(unsigned int set, unsigned int mask)
{ {
return 0; return 0;
} }
static inline int _xtensa_handle_one_int6(unsigned int mask) static inline int _xtensa_handle_one_int6(unsigned int set, unsigned int mask)
{ {
return 0; return 0;
} }

16
soc/nxp/imx/imx8/adsp/_soc_inthandlers.h
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@ -83,7 +83,7 @@
#error core-isa.h interrupt level does not match dispatcher! #error core-isa.h interrupt level does not match dispatcher!
#endif #endif
static inline int _xtensa_handle_one_int1(unsigned int mask) static inline int _xtensa_handle_one_int1(unsigned int set, unsigned int mask)
{ {
int irq; int irq;
@ -98,7 +98,7 @@ handle_irq:
return mask; return mask;
} }
static inline int _xtensa_handle_one_int2(unsigned int mask) static inline int _xtensa_handle_one_int2(unsigned int set, unsigned int mask)
{ {
int irq; int irq;
int i = 0; int i = 0;
@ -117,7 +117,7 @@ handle_irq:
return mask; return mask;
} }
static inline int _xtensa_handle_one_int3(unsigned int mask) static inline int _xtensa_handle_one_int3(unsigned int set, unsigned int mask)
{ {
int irq; int irq;
@ -142,7 +142,7 @@ handle_irq:
return mask; return mask;
} }
static inline int _xtensa_handle_one_int5(unsigned int mask) static inline int _xtensa_handle_one_int5(unsigned int set, unsigned int mask)
{ {
int irq; int irq;
@ -157,22 +157,22 @@ handle_irq:
return mask; return mask;
} }
static inline int _xtensa_handle_one_int0(unsigned int mask) static inline int _xtensa_handle_one_int0(unsigned int set, unsigned int mask)
{ {
return 0; return 0;
} }
static inline int _xtensa_handle_one_int4(unsigned int mask) static inline int _xtensa_handle_one_int4(unsigned int set, unsigned int mask)
{ {
return 0; return 0;
} }
static inline int _xtensa_handle_one_int6(unsigned int mask) static inline int _xtensa_handle_one_int6(unsigned int set, unsigned int mask)
{ {
return 0; return 0;
} }
static inline int _xtensa_handle_one_int7(unsigned int mask) static inline int _xtensa_handle_one_int7(unsigned int set, unsigned int mask)
{ {
return 0; return 0;
} }

16
soc/nxp/imx/imx8m/adsp/_soc_inthandlers.h
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@ -83,7 +83,7 @@
#error core-isa.h interrupt level does not match dispatcher! #error core-isa.h interrupt level does not match dispatcher!
#endif #endif
static inline int _xtensa_handle_one_int1(unsigned int mask) static inline int _xtensa_handle_one_int1(unsigned int set, unsigned int mask)
{ {
int irq; int irq;
@ -98,7 +98,7 @@ handle_irq:
return mask; return mask;
} }
static inline int _xtensa_handle_one_int2(unsigned int mask) static inline int _xtensa_handle_one_int2(unsigned int set, unsigned int mask)
{ {
int irq; int irq;
int i = 0; int i = 0;
@ -117,7 +117,7 @@ handle_irq:
return mask; return mask;
} }
static inline int _xtensa_handle_one_int3(unsigned int mask) static inline int _xtensa_handle_one_int3(unsigned int set, unsigned int mask)
{ {
int irq; int irq;
@ -142,7 +142,7 @@ handle_irq:
return mask; return mask;
} }
static inline int _xtensa_handle_one_int5(unsigned int mask) static inline int _xtensa_handle_one_int5(unsigned int set, unsigned int mask)
{ {
int irq; int irq;
@ -157,22 +157,22 @@ handle_irq:
return mask; return mask;
} }
static inline int _xtensa_handle_one_int0(unsigned int mask) static inline int _xtensa_handle_one_int0(unsigned int set, unsigned int mask)
{ {
return 0; return 0;
} }
static inline int _xtensa_handle_one_int4(unsigned int mask) static inline int _xtensa_handle_one_int4(unsigned int set, unsigned int mask)
{ {
return 0; return 0;
} }
static inline int _xtensa_handle_one_int6(unsigned int mask) static inline int _xtensa_handle_one_int6(unsigned int set, unsigned int mask)
{ {
return 0; return 0;
} }
static inline int _xtensa_handle_one_int7(unsigned int mask) static inline int _xtensa_handle_one_int7(unsigned int set, unsigned int mask)
{ {
return 0; return 0;
} }

32
soc/nxp/imx/imx8ulp/adsp/_soc_inthandlers.h
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@ -116,7 +116,7 @@
#error core-isa.h interrupt level does not match dispatcher! #error core-isa.h interrupt level does not match dispatcher!
#endif #endif
static inline int _xtensa_handle_one_int5(unsigned int mask) static inline int _xtensa_handle_one_int5(unsigned int set, unsigned int mask)
{ {
int irq; int irq;
@ -131,7 +131,7 @@ handle_irq:
return mask; return mask;
} }
static inline int _xtensa_handle_one_int2(unsigned int mask) static inline int _xtensa_handle_one_int2(unsigned int set, unsigned int mask)
{ {
int irq; int irq;
@ -200,7 +200,7 @@ handle_irq:
return mask; return mask;
} }
static inline int _xtensa_handle_one_int3(unsigned int mask) static inline int _xtensa_handle_one_int3(unsigned int set, unsigned int mask)
{ {
int irq; int irq;
@ -274,7 +274,7 @@ handle_irq:
return mask; return mask;
} }
static inline int _xtensa_handle_one_int1(unsigned int mask) static inline int _xtensa_handle_one_int1(unsigned int set, unsigned int mask)
{ {
int irq; int irq;
@ -343,51 +343,51 @@ handle_irq:
return mask; return mask;
} }
static inline int _xtensa_handle_one_int0(unsigned int mask) static inline int _xtensa_handle_one_int0(unsigned int set, unsigned int mask)
{ {
return 0; return 0;
} }
static inline int _xtensa_handle_one_int4(unsigned int mask) static inline int _xtensa_handle_one_int4(unsigned int set, unsigned int mask)
{ {
return 0; return 0;
} }
static inline int _xtensa_handle_one_int6(unsigned int mask) static inline int _xtensa_handle_one_int6(unsigned int set, unsigned int mask)
{ {
return 0; return 0;
} }
static inline int _xtensa_handle_one_int7(unsigned int mask) static inline int _xtensa_handle_one_int7(unsigned int set, unsigned int mask)
{ {
return 0; return 0;
} }
static inline int _xtensa_handle_one_int8(unsigned int mask) static inline int _xtensa_handle_one_int8(unsigned int set, unsigned int mask)
{ {
return 0; return 0;
} }
static inline int _xtensa_handle_one_int9(unsigned int mask) static inline int _xtensa_handle_one_int9(unsigned int set, unsigned int mask)
{ {
return 0; return 0;
} }
static inline int _xtensa_handle_one_int10(unsigned int mask) static inline int _xtensa_handle_one_int10(unsigned int set, unsigned int mask)
{ {
return 0; return 0;
} }
static inline int _xtensa_handle_one_int11(unsigned int mask) static inline int _xtensa_handle_one_int11(unsigned int set, unsigned int mask)
{ {
return 0; return 0;
} }
static inline int _xtensa_handle_one_int12(unsigned int mask) static inline int _xtensa_handle_one_int12(unsigned int set, unsigned int mask)
{ {
return 0; return 0;
} }
static inline int _xtensa_handle_one_int13(unsigned int mask) static inline int _xtensa_handle_one_int13(unsigned int set, unsigned int mask)
{ {
return 0; return 0;
} }
static inline int _xtensa_handle_one_int14(unsigned int mask) static inline int _xtensa_handle_one_int14(unsigned int set, unsigned int mask)
{ {
return 0; return 0;
} }
static inline int _xtensa_handle_one_int15(unsigned int mask) static inline int _xtensa_handle_one_int15(unsigned int set, unsigned int mask)
{ {
return 0; return 0;
} }

16
soc/nxp/imx/imx8x/adsp/_soc_inthandlers.h
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@ -83,7 +83,7 @@
#error core-isa.h interrupt level does not match dispatcher! #error core-isa.h interrupt level does not match dispatcher!
#endif #endif
static inline int _xtensa_handle_one_int1(unsigned int mask) static inline int _xtensa_handle_one_int1(unsigned int set, unsigned int mask)
{ {
int irq; int irq;
@ -98,7 +98,7 @@ handle_irq:
return mask; return mask;
} }
static inline int _xtensa_handle_one_int2(unsigned int mask) static inline int _xtensa_handle_one_int2(unsigned int set, unsigned int mask)
{ {
int irq; int irq;
int i = 0; int i = 0;
@ -117,7 +117,7 @@ handle_irq:
return mask; return mask;
} }
static inline int _xtensa_handle_one_int3(unsigned int mask) static inline int _xtensa_handle_one_int3(unsigned int set, unsigned int mask)
{ {
int irq; int irq;
@ -142,7 +142,7 @@ handle_irq:
return mask; return mask;
} }
static inline int _xtensa_handle_one_int5(unsigned int mask) static inline int _xtensa_handle_one_int5(unsigned int set, unsigned int mask)
{ {
int irq; int irq;
@ -157,22 +157,22 @@ handle_irq:
return mask; return mask;
} }
static inline int _xtensa_handle_one_int0(unsigned int mask) static inline int _xtensa_handle_one_int0(unsigned int set, unsigned int mask)
{ {
return 0; return 0;
} }
static inline int _xtensa_handle_one_int4(unsigned int mask) static inline int _xtensa_handle_one_int4(unsigned int set, unsigned int mask)
{ {
return 0; return 0;
} }
static inline int _xtensa_handle_one_int6(unsigned int mask) static inline int _xtensa_handle_one_int6(unsigned int set, unsigned int mask)
{ {
return 0; return 0;
} }
static inline int _xtensa_handle_one_int7(unsigned int mask) static inline int _xtensa_handle_one_int7(unsigned int set, unsigned int mask)
{ {
return 0; return 0;
} }

10
soc/nxp/imxrt/imxrt5xx/f1/include/_soc_inthandlers.h
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@ -113,7 +113,7 @@
* XCHAL_INTLEVEL5_MASK: 0x00000001 * XCHAL_INTLEVEL5_MASK: 0x00000001
*/ */
static inline int _xtensa_handle_one_int1(unsigned int mask) static inline int _xtensa_handle_one_int1(unsigned int set, unsigned int mask)
{ {
int irq; int irq;
@ -131,7 +131,7 @@ handle_irq:
return mask; return mask;
} }
static inline int _xtensa_handle_one_int2(unsigned int mask) static inline int _xtensa_handle_one_int2(unsigned int set, unsigned int mask)
{ {
int irq; int irq;
@ -149,7 +149,7 @@ handle_irq:
return mask; return mask;
} }
static inline int _xtensa_handle_one_int3(unsigned int mask) static inline int _xtensa_handle_one_int3(unsigned int set, unsigned int mask)
{ {
int irq; int irq;
@ -167,12 +167,12 @@ handle_irq:
return mask; return mask;
} }
static inline int _xtensa_handle_one_int4(unsigned int mask) static inline int _xtensa_handle_one_int4(unsigned int set, unsigned int mask)
{ {
return 0; return 0;
} }
static inline int _xtensa_handle_one_int5(unsigned int mask) static inline int _xtensa_handle_one_int5(unsigned int set, unsigned int mask)
{ {
int irq; int irq;

12
soc/nxp/imxrt/imxrt6xx/hifi4/include/_soc_inthandlers.h
Unescape View File

@ -116,7 +116,7 @@
#error core-isa.h interrupt level does not match dispatcher! #error core-isa.h interrupt level does not match dispatcher!
#endif #endif
static inline int _xtensa_handle_one_int5(unsigned int mask) static inline int _xtensa_handle_one_int5(unsigned int set, unsigned int mask)
{ {
int irq; int irq;
@ -131,7 +131,7 @@ handle_irq:
return mask; return mask;
} }
static inline int _xtensa_handle_one_int2(unsigned int mask) static inline int _xtensa_handle_one_int2(unsigned int set, unsigned int mask)
{ {
int irq; int irq;
@ -200,7 +200,7 @@ handle_irq:
return mask; return mask;
} }
static inline int _xtensa_handle_one_int3(unsigned int mask) static inline int _xtensa_handle_one_int3(unsigned int set, unsigned int mask)
{ {
int irq; int irq;
@ -269,7 +269,7 @@ handle_irq:
return mask; return mask;
} }
static inline int _xtensa_handle_one_int1(unsigned int mask) static inline int _xtensa_handle_one_int1(unsigned int set, unsigned int mask)
{ {
int irq; int irq;
@ -343,11 +343,11 @@ handle_irq:
return mask; return mask;
} }
static inline int _xtensa_handle_one_int0(unsigned int mask) static inline int _xtensa_handle_one_int0(unsigned int set, unsigned int mask)
{ {
return 0; return 0;
} }
static inline int _xtensa_handle_one_int4(unsigned int mask) static inline int _xtensa_handle_one_int4(unsigned int set, unsigned int mask)
{ {
return 0; return 0;
} }

25
subsys/testsuite/include/zephyr/interrupt_util.h
Unescape View File

@ -180,7 +180,30 @@ static inline void trigger_irq(int irq)
#elif defined(CONFIG_XTENSA) #elif defined(CONFIG_XTENSA)
static inline void trigger_irq(int irq) static inline void trigger_irq(int irq)
{ {
z_xt_set_intset(BIT((unsigned int)irq)); #if XCHAL_NUM_INTERRUPTS > 32
switch (irq >> 5) {
case 0:
z_xt_set_intset(1 << irq);
break;
case 1:
z_xt_set_intset1(1 << irq);
break;
#if XCHAL_NUM_INTERRUPTS > 64
case 2:
z_xt_set_intset2(1 << irq);
break;
#endif
#if XCHAL_NUM_INTERRUPTS > 96
case 3:
z_xt_set_intset3(1 << irq);
break;
#endif
default:
break;
}
#else
z_xt_set_intset(1 << irq);
#endif
} }
#elif defined(CONFIG_SPARC) #elif defined(CONFIG_SPARC)

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