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soc: arm64: intel_socfpga: Move and convert to HWMv2

Move and convert soc/arm64/intel_socfpga SoC family
`intel_socfpga` configuration to HWMv2 with its SoC
series: `agilex` and `agilex5` and related SoCs:
`intel_socfpga_agilex` and `intel_socfpga_agilex5`.

Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>
pull/69687/head
Dmitrii Golovanov 1 year ago committed by Carles Cufi
parent
commit
ab883b8019
  1. 0
      soc/intel/intel_socfpga/CMakeLists.txt
  2. 8
      soc/intel/intel_socfpga/Kconfig
  3. 8
      soc/intel/intel_socfpga/Kconfig.defconfig
  4. 10
      soc/intel/intel_socfpga/Kconfig.soc
  5. 0
      soc/intel/intel_socfpga/agilex/CMakeLists.txt
  6. 6
      soc/intel/intel_socfpga/agilex/Kconfig
  7. 5
      soc/intel/intel_socfpga/agilex/Kconfig.defconfig.agilex
  8. 8
      soc/intel/intel_socfpga/agilex/Kconfig.defconfig.series
  9. 20
      soc/intel/intel_socfpga/agilex/Kconfig.soc
  10. 0
      soc/intel/intel_socfpga/agilex/mmu_regions.c
  11. 0
      soc/intel/intel_socfpga/agilex5/CMakeLists.txt
  12. 6
      soc/intel/intel_socfpga/agilex5/Kconfig
  13. 5
      soc/intel/intel_socfpga/agilex5/Kconfig.defconfig.agilex5
  14. 8
      soc/intel/intel_socfpga/agilex5/Kconfig.defconfig.series
  15. 20
      soc/intel/intel_socfpga/agilex5/Kconfig.soc
  16. 0
      soc/intel/intel_socfpga/agilex5/mmu_regions.c
  17. 0
      soc/intel/intel_socfpga/common/CMakeLists.txt
  18. 0
      soc/intel/intel_socfpga/common/socfpga_handoff.h
  19. 0
      soc/intel/intel_socfpga/common/socfpga_system_manager.h
  20. 9
      soc/intel/intel_socfpga/soc.yml
  21. 13
      soc/soc_legacy/arm64/intel_socfpga/Kconfig
  22. 4
      soc/soc_legacy/arm64/intel_socfpga/Kconfig.defconfig
  23. 4
      soc/soc_legacy/arm64/intel_socfpga/Kconfig.soc
  24. 11
      soc/soc_legacy/arm64/intel_socfpga/agilex/Kconfig.defconfig.series
  25. 10
      soc/soc_legacy/arm64/intel_socfpga/agilex/Kconfig.series
  26. 10
      soc/soc_legacy/arm64/intel_socfpga/agilex/Kconfig.soc
  27. 11
      soc/soc_legacy/arm64/intel_socfpga/agilex5/Kconfig.defconfig.series
  28. 10
      soc/soc_legacy/arm64/intel_socfpga/agilex5/Kconfig.series
  29. 10
      soc/soc_legacy/arm64/intel_socfpga/agilex5/Kconfig.soc

0
soc/soc_legacy/arm64/intel_socfpga/CMakeLists.txt → soc/intel/intel_socfpga/CMakeLists.txt

8
soc/intel/intel_socfpga/Kconfig

@ -0,0 +1,8 @@ @@ -0,0 +1,8 @@
# Copyright (c) 2021-2024 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
if SOC_FAMILY_INTEL_SOCFPGA
rsource "*/Kconfig"
endif # SOC_FAMILY_INTEL_SOCFPGA

8
soc/intel/intel_socfpga/Kconfig.defconfig

@ -0,0 +1,8 @@ @@ -0,0 +1,8 @@
# Copyright (c) 2021-2024 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
if SOC_FAMILY_INTEL_SOCFPGA
rsource "*/Kconfig.defconfig.series"
endif # SOC_FAMILY_INTEL_SOCFPGA

10
soc/intel/intel_socfpga/Kconfig.soc

@ -0,0 +1,10 @@ @@ -0,0 +1,10 @@
# Copyright (c) 2021-2024 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
config SOC_FAMILY_INTEL_SOCFPGA
bool
config SOC_FAMILY
default "intel_socfpga" if SOC_FAMILY_INTEL_SOCFPGA
rsource "*/Kconfig.soc"

0
soc/soc_legacy/arm64/intel_socfpga/agilex/CMakeLists.txt → soc/intel/intel_socfpga/agilex/CMakeLists.txt

6
soc/intel/intel_socfpga/agilex/Kconfig

@ -0,0 +1,6 @@ @@ -0,0 +1,6 @@
# Copyright (c) 2021-2024 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_AGILEX
select ARM64
select CPU_CORTEX_A53

5
soc/soc_legacy/arm64/intel_socfpga/agilex/Kconfig.defconfig.agilex → soc/intel/intel_socfpga/agilex/Kconfig.defconfig.agilex

@ -1,11 +1,8 @@ @@ -1,11 +1,8 @@
# Copyright (c) 2021 Intel Corporation
# Copyright (c) 2021-2024 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
if SOC_AGILEX
config SOC
default "intel_socfpga_agilex"
# must be >= the highest interrupt number used
# - include the UART interrupts 173 or 204
config NUM_IRQS

8
soc/intel/intel_socfpga/agilex/Kconfig.defconfig.series

@ -0,0 +1,8 @@ @@ -0,0 +1,8 @@
# Copyright (c) 2021-2024 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_AGILEX
rsource "Kconfig.defconfig.agilex*"
endif # SOC_SERIES_AGILEX

20
soc/intel/intel_socfpga/agilex/Kconfig.soc

@ -0,0 +1,20 @@ @@ -0,0 +1,20 @@
# Copyright (c) 2021-2024 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_AGILEX
bool
select SOC_FAMILY_INTEL_SOCFPGA
help
Intel SoC FPGA Agilex Series
config SOC_SERIES
default "agilex" if SOC_SERIES_AGILEX
config SOC_AGILEX
bool
select SOC_SERIES_AGILEX
help
Intel SoC FPGA Agilex
config SOC
default "intel_socfpga_agilex" if SOC_AGILEX

0
soc/soc_legacy/arm64/intel_socfpga/agilex/mmu_regions.c → soc/intel/intel_socfpga/agilex/mmu_regions.c

0
soc/soc_legacy/arm64/intel_socfpga/agilex5/CMakeLists.txt → soc/intel/intel_socfpga/agilex5/CMakeLists.txt

6
soc/intel/intel_socfpga/agilex5/Kconfig

@ -0,0 +1,6 @@ @@ -0,0 +1,6 @@
# Copyright (c) 2022-2024 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_AGILEX5
select ARM64
select CPU_CORTEX_A76_A55

5
soc/soc_legacy/arm64/intel_socfpga/agilex5/Kconfig.defconfig.agilex5 → soc/intel/intel_socfpga/agilex5/Kconfig.defconfig.agilex5

@ -1,11 +1,8 @@ @@ -1,11 +1,8 @@
# Copyright (c) 2022 Intel Corporation
# Copyright (c) 2022-2024 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
if SOC_AGILEX5
config SOC
default "intel_socfpga_agilex5"
# must be >= the highest interrupt number used
# - include the UART interrupts 173 or 204
config NUM_IRQS

8
soc/intel/intel_socfpga/agilex5/Kconfig.defconfig.series

@ -0,0 +1,8 @@ @@ -0,0 +1,8 @@
# Copyright (c) 2022-2024 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_AGILEX5
rsource "Kconfig.defconfig.agilex5*"
endif # SOC_SERIES_AGILEX5

20
soc/intel/intel_socfpga/agilex5/Kconfig.soc

@ -0,0 +1,20 @@ @@ -0,0 +1,20 @@
# Copyright (c) 2022-2024 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_AGILEX5
bool
select SOC_FAMILY_INTEL_SOCFPGA
help
Intel SoC FPGA Agilex5 Series
config SOC_SERIES
default "agilex5" if SOC_SERIES_AGILEX5
config SOC_AGILEX5
bool
select SOC_SERIES_AGILEX5
help
Intel SoC FPGA Agilex5
config SOC
default "intel_socfpga_agilex5" if SOC_AGILEX5

0
soc/soc_legacy/arm64/intel_socfpga/agilex5/mmu_regions.c → soc/intel/intel_socfpga/agilex5/mmu_regions.c

0
soc/soc_legacy/arm64/intel_socfpga/common/CMakeLists.txt → soc/intel/intel_socfpga/common/CMakeLists.txt

0
soc/soc_legacy/arm64/intel_socfpga/common/socfpga_handoff.h → soc/intel/intel_socfpga/common/socfpga_handoff.h

0
soc/soc_legacy/arm64/intel_socfpga/common/socfpga_system_manager.h → soc/intel/intel_socfpga/common/socfpga_system_manager.h

9
soc/intel/intel_socfpga/soc.yml

@ -0,0 +1,9 @@ @@ -0,0 +1,9 @@
family:
- name: intel_socfpga
series:
- name: agilex
socs:
- name: intel_socfpga_agilex
- name: agilex5
socs:
- name: intel_socfpga_agilex5

13
soc/soc_legacy/arm64/intel_socfpga/Kconfig

@ -1,13 +0,0 @@ @@ -1,13 +0,0 @@
# Copyright (c) 2021 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
config SOC_FAMILY_INTEL_SOCFPGA
bool
if SOC_FAMILY_INTEL_SOCFPGA
config SOC_FAMILY
string
default "intel_socfpga"
source "soc/soc_legacy/arm64/intel_socfpga/*/Kconfig.soc"
endif

4
soc/soc_legacy/arm64/intel_socfpga/Kconfig.defconfig

@ -1,4 +0,0 @@ @@ -1,4 +0,0 @@
# Copyright (c) 2021 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
source "soc/soc_legacy/arm64/intel_socfpga/*/Kconfig.defconfig.series"

4
soc/soc_legacy/arm64/intel_socfpga/Kconfig.soc

@ -1,4 +0,0 @@ @@ -1,4 +0,0 @@
# Copyright (c) 2021 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
source "soc/soc_legacy/arm64/intel_socfpga/*/Kconfig.series"

11
soc/soc_legacy/arm64/intel_socfpga/agilex/Kconfig.defconfig.series

@ -1,11 +0,0 @@ @@ -1,11 +0,0 @@
# Copyright (c) 2021 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_AGILEX
config SOC_SERIES
default "agilex"
source "soc/soc_legacy/arm64/intel_socfpga/agilex/Kconfig.defconfig.agilex*"
endif # SOC_SERIES_AGILEX

10
soc/soc_legacy/arm64/intel_socfpga/agilex/Kconfig.series

@ -1,10 +0,0 @@ @@ -1,10 +0,0 @@
# Copyright (c) 2021 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_AGILEX
bool "Intel SoC FPGA Agilex Series"
select ARM64
select CPU_CORTEX_A53
select SOC_FAMILY_INTEL_SOCFPGA
help
Enable support for Intel SoC FPGA Series

10
soc/soc_legacy/arm64/intel_socfpga/agilex/Kconfig.soc

@ -1,10 +0,0 @@ @@ -1,10 +0,0 @@
# Copyright (c) 2021 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
choice
prompt "Intel SoC FPGA Agilex"
depends on SOC_SERIES_AGILEX
config SOC_AGILEX
bool "Intel SoC FPGA Agilex"
endchoice

11
soc/soc_legacy/arm64/intel_socfpga/agilex5/Kconfig.defconfig.series

@ -1,11 +0,0 @@ @@ -1,11 +0,0 @@
# Copyright (c) 2022 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_AGILEX5
config SOC_SERIES
default "agilex5"
source "soc/soc_legacy/arm64/intel_socfpga/agilex5/Kconfig.defconfig.agilex5*"
endif # SOC_SERIES_AGILEX5

10
soc/soc_legacy/arm64/intel_socfpga/agilex5/Kconfig.series

@ -1,10 +0,0 @@ @@ -1,10 +0,0 @@
# Copyright (c) 2022 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_AGILEX5
bool "Intel SoC FPGA Agilex5 Series"
select ARM64
select CPU_CORTEX_A76_A55
select SOC_FAMILY_INTEL_SOCFPGA
help
Enable support for Intel SoC FPGA Series

10
soc/soc_legacy/arm64/intel_socfpga/agilex5/Kconfig.soc

@ -1,10 +0,0 @@ @@ -1,10 +0,0 @@
# Copyright (c) 2022 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
choice
prompt "Intel SoC FPGA Agilex5"
depends on SOC_SERIES_AGILEX5
config SOC_AGILEX5
bool "Intel SoC FPGA Agilex5"
endchoice
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