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@ -21,8 +21,6 @@
@@ -21,8 +21,6 @@
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#define ADI_MAX32_I2C_INT_FL0_MASK 0x00FFFFFF |
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#define ADI_MAX32_I2C_INT_FL1_MASK 0x7 |
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#define ADI_MAX32_I2C_STATUS_MASTER_BUSY BIT(5) |
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#define I2C_RECOVER_MAX_RETRIES 3 |
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#ifdef CONFIG_I2C_MAX32_DMA |
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@ -540,8 +538,7 @@ static int i2c_max32_transfer(const struct device *dev, struct i2c_msg *msgs, ui
@@ -540,8 +538,7 @@ static int i2c_max32_transfer(const struct device *dev, struct i2c_msg *msgs, ui
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/* Wait for busy flag to be cleared for clock stetching
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* use-cases |
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*/ |
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while (i2c->status & ADI_MAX32_I2C_STATUS_MASTER_BUSY) { |
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} |
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Wrap_MXC_I2C_WaitForBusyClear(i2c); |
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MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK, |
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ADI_MAX32_I2C_INT_FL1_MASK); |
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} |
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@ -650,7 +647,7 @@ static void i2c_max32_isr_target(const struct device *dev, mxc_i2c_regs_t *i2c)
@@ -650,7 +647,7 @@ static void i2c_max32_isr_target(const struct device *dev, mxc_i2c_regs_t *i2c)
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uint32_t int_en0; |
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uint32_t int_en1; |
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ctrl = i2c->ctrl; |
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Wrap_MXC_I2C_GetCtrl(i2c, &ctrl); |
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Wrap_MXC_I2C_GetIntEn(i2c, &int_en0, &int_en1); |
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MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1); |
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MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK, ADI_MAX32_I2C_INT_FL1_MASK); |
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@ -710,7 +707,7 @@ static void i2c_max32_isr_target(const struct device *dev, mxc_i2c_regs_t *i2c)
@@ -710,7 +707,7 @@ static void i2c_max32_isr_target(const struct device *dev, mxc_i2c_regs_t *i2c)
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if (int_en0 & ADI_MAX32_I2C_INT_EN0_ADDR_MATCH) { |
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if (int_fl0 & ADI_MAX32_I2C_INT_FL0_ADDR_MATCH) { |
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/* Address match occurred, prepare for transaction */ |
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if (i2c->ctrl & MXC_F_I2C_CTRL_READ) { |
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if (Wrap_MXC_I2C_GetReadWriteBitStatus(i2c)) { |
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/* Read request received from the master */ |
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i2c_max32_target_callback(dev, i2c, MXC_I2C_EVT_MASTER_RD); |
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int_en0 = ADI_MAX32_I2C_INT_EN0_TX_THD | |
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