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80 lines
3.2 KiB
80 lines
3.2 KiB
.. _intel_socfpga_agilex5_socdk: |
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Intel® Agilex™ 5 SoC FPGA Development Kit |
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Overview |
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The Intel® Agilex™ 5 SoC FPGA Development Kit offers a complete design |
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environment that includes both hardware and software for developing |
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Intel® Agilex™ 5 E-Series based FPGA designs. This kit is recommended for |
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developing custom ARM* processor-based SoC designs and ideal for intelligent |
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applications at the edge, embedded and more. |
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Hardware |
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The Intel® Agilex™ 5 Development Kit supports the following physical features: |
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- Intel® Agilex™ 5 E-Series FPGA, 50K-656K LEs integrated with |
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multi-core ARM processors of Dual-core A55 and Dual-core A76 |
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- On-board 8 GB DDR5 memory |
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- On-board JTAG Intel FPGA Download Cable II |
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- QSPI flash daughtercard |
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Supported Features |
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================== |
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The Intel® Agilex™ 5 SoC Development Kit configuration supports the following |
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hardware features: |
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+-----------+------------+---------------------------------------------+ |
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| Interface | Controller | Hardware Subsystem Vendor | |
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+===========+============+=============================================+ |
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| GIC-600 | on-chip | ARM GICv3 interrupt controller | |
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+-----------+------------+---------------------------------------------+ |
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| UART | on-chip | Synopsys Designware,NS16550 compatible | |
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+-----------+------------+---------------------------------------------+ |
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| ARM TIMER | on-chip | ARM system timer | |
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+-----------+------------+---------------------------------------------+ |
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| Reset | on-chip | Intel Corporation, SoCFPGA Reset controller | |
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+-----------+------------+---------------------------------------------+ |
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| Clock | on-chip | Intel Corporation, SoCFPGA Clock controller | |
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+-----------+------------+---------------------------------------------+ |
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NOTE: TODO, more details on dev kit will be updated as and when available. |
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The default configuration can be found in the defconfig file: |
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`boards/intel/intel_socfpga_agilex5_socdk/intel_socfpga_agilex5_socdk_defconfig` |
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Programming and Debugging |
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************************* |
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Zephyr Boot Flow |
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Zephyr image will need to be loaded by Intel Arm Trusted Firmware (ATF). |
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ATF BL2 is the First Stage Boot Loader (FSBL) and ATF BL31 is the Run time resident firmware which |
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provides services like SMC (Secure monitor calls) and PSCI (Power state coordination interface). |
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Boot flow: |
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ATF BL2 (EL3) -> ATF BL31 (EL3) -> Zephyr (EL1) |
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Intel Arm Trusted Firmware (ATF) can be downloaded from github: |
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`altera-opensource/arm-trusted-firmware <https://github.com/altera-opensource/arm-trusted-firmware.git>`_ |
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Flashing |
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======== |
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Zephyr image can be loaded in DDR memory at address 0x80000000 from |
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SD Card or QSPI Flash or NAND in ATF BL2. |
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Debugging |
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========= |
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The Intel® Agilex™ 5 SoC Development Kit includes one JTAG connector on |
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board, connect it to Intel USB blaster download cables for debugging. |
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Zephyr applications running on the Cortex-A55/A76 core can be tested by |
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observing UART console output. |
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References |
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========== |
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`Intel® Agilex™ 5 FPGA and SoC FPGA <https://www.intel.in/content/www/in/en/products/details/fpga/agilex/5.html>`_
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