drivers: gpio: rz: improve gpio driver for Renesas RZ/A2M

- Adding support for GPIO_DISCONNECTED mode.
- Removing redundant interrupt configuration logic from the
.pin_configure API (already handled in pin_interrupt_configure).

Signed-off-by: Hoang Nguyen <hoang.nguyen.jx@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>

drivers/gpio/gpio_renesas_rza2m.c

@@ -320,13 +320,15 @@ static int gpio_rza2m_pin_configure(const struct device *port_dev, gpio_pin_t pi
 		return -ENOTSUP;
 	}
 
+	if (!flags) {
+		/* Disconnected mode */
+		gpio_rza2m_pin_configure_as_gpio(port_dev, pin, RZA2M_PDR_HIZ);
+	} else if (!(flags & GPIO_OPEN_DRAIN)) {
 		/* Configure pin direction */
 		if (flags & GPIO_OUTPUT) {
 			gpio_rza2m_pin_configure_as_gpio(port_dev, pin, RZA2M_PDR_OUTPUT);
 		} else if (flags & GPIO_INPUT) {
 			gpio_rza2m_pin_configure_as_gpio(port_dev, pin, RZA2M_PDR_INPUT);
-	} else {
-		return -ENOTSUP;
 		}
 
 		/* Configure pin drive strength */
@@ -342,21 +344,6 @@ static int gpio_rza2m_pin_configure(const struct device *port_dev, gpio_pin_t pi
 		} else if (flags & GPIO_OUTPUT_INIT_LOW) {
 			ret = gpio_rza2m_port_clear_bits_raw(port_dev, BIT(pin));
 		}
-
-	/* Configure pin interrupt */
-	if (flags & GPIO_INT_ENABLE) {
-		if (flags & GPIO_INT_LOW_0) {
-			return -ENOTSUP;
-		}
-
-		enum gpio_int_mode mode =
-			(flags & GPIO_INT_EDGE) ? GPIO_INT_MODE_EDGE : GPIO_INT_MODE_LEVEL;
-		enum gpio_int_trig trig = GPIO_INT_TRIG_HIGH;
-
-		ret = gpio_rza2m_pin_interrupt_configure(port_dev, pin, mode, trig);
-	} else if (flags & GPIO_INT_DISABLE) {
-		ret = gpio_rza2m_pin_interrupt_configure(port_dev, pin, GPIO_INT_MODE_DISABLED,
-							 GPIO_INT_TRIG_HIGH);
 	}
 
 	return ret;

drivers/gpio/gpio_renesas_rza2m.h

@@ -31,6 +31,7 @@
 #define RZA2M_GPIO_DRIVE_STRENGTH_NORMAL 0x01
 #define RZA2M_DSCR_MASK                  0x03
 #define RZA2M_PDR_MASK                   0x03
+#define RZA2M_PDR_HIZ                    0x00
 #define RZA2M_PDR_INPUT                  0x02
 #define RZA2M_PDR_OUTPUT                 0x03
 #define RZA2M_PWPR_PFSWE_MASK            0x40