soc: st: stm32: Add series stm32u3

Add STM32U3 familly support

Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>

soc/st/stm32/soc.yml

@@ -201,6 +201,9 @@ family:
     - name: stm32u031xx
     - name: stm32u073xx
     - name: stm32u083xx
+  - name: stm32u3x
+    socs:
+    - name: stm32u385xx
   - name: stm32u5x
     socs:
     - name: stm32u5a5xx

soc/st/stm32/stm32u3x/CMakeLists.txt

@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(${ZEPHYR_BASE}/drivers)
+zephyr_sources(
+  soc.c
+  )
+
+zephyr_include_directories(.)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

soc/st/stm32/stm32u3x/Kconfig

@@ -0,0 +1,15 @@
+# STMicroelectronics STM32U3 MCU series
+
+# Copyright (c) 2025 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_STM32U3X
+	select ARM
+	select CPU_CORTEX_M33
+	select CPU_HAS_ARM_SAU
+	select CPU_HAS_ARM_MPU
+	select CPU_HAS_FPU
+	select ARMV8_M_DSP
+	select CPU_CORTEX_M_HAS_DWT
+	select HAS_STM32CUBE
+	select SOC_EARLY_INIT_HOOK

soc/st/stm32/stm32u3x/Kconfig.defconfig

@@ -0,0 +1,11 @@
+# STMicroelectronics STM32U3 MCU series
+
+# Copyright (c) 2025 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_STM32U3X
+
+config NUM_IRQS
+	default 125
+
+endif # SOC_SERIES_STM32U3X

soc/st/stm32/stm32u3x/Kconfig.soc

@@ -0,0 +1,18 @@
+# STMicroelectronics STM32U3 MCU series
+
+# Copyright (c) 2025 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_STM32U3X
+	bool
+	select SOC_FAMILY_STM32
+
+config SOC_SERIES
+	default "stm32u3x" if SOC_SERIES_STM32U3X
+
+config SOC_STM32U385XX
+	bool
+	select SOC_SERIES_STM32U3X
+
+config SOC
+	default "stm32u385xx" if SOC_STM32U385XX

soc/st/stm32/stm32u3x/soc.c

@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for STM32U3 processor
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/cache.h>
+#include <zephyr/init.h>
+#include <stm32_ll_bus.h>
+#include <stm32_ll_system.h>
+#include <zephyr/logging/log.h>
+
+#include <cmsis_core.h>
+
+#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
+LOG_MODULE_REGISTER(soc);
+
+/**
+ * @brief Perform basic hardware initialization at boot.
+ *
+ * This needs to be run from the very beginning.
+ */
+void soc_early_init_hook(void)
+{
+	/* Enable ART Accelerator prefetch */
+	sys_cache_instr_enable();
+
+	/* Update CMSIS SystemCoreClock variable (HCLK) */
+	/* The MSIS is used as system clock source after startup from reset,configured at 12 MHz. */
+	SystemCoreClock = 12000000;
+
+	/* Enable power controller bus clock for other drivers */
+	LL_AHB1_GRP2_EnableClock(LL_AHB1_GRP2_PERIPH_PWR);
+}

soc/st/stm32/stm32u3x/soc.h

@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file SoC configuration macros for the STM32U3 family processors.
+ */
+
+#ifndef _STM32U3_SOC_H_
+#define _STM32U3_SOC_H_
+
+#ifndef _ASMLANGUAGE
+
+#include <stm32u3xx.h>
+
+#endif /* !_ASMLANGUAGE */
+
+#endif /* _STM32U3_SOC_H_ */