diff --git a/soc/st/stm32/soc.yml b/soc/st/stm32/soc.yml index 705097b3578..59d420ee09f 100644 --- a/soc/st/stm32/soc.yml +++ b/soc/st/stm32/soc.yml @@ -201,6 +201,9 @@ family: - name: stm32u031xx - name: stm32u073xx - name: stm32u083xx + - name: stm32u3x + socs: + - name: stm32u385xx - name: stm32u5x socs: - name: stm32u5a5xx diff --git a/soc/st/stm32/stm32u3x/CMakeLists.txt b/soc/st/stm32/stm32u3x/CMakeLists.txt new file mode 100644 index 00000000000..eebd281cd96 --- /dev/null +++ b/soc/st/stm32/stm32u3x/CMakeLists.txt @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources( + soc.c + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/st/stm32/stm32u3x/Kconfig b/soc/st/stm32/stm32u3x/Kconfig new file mode 100644 index 00000000000..f3684dec946 --- /dev/null +++ b/soc/st/stm32/stm32u3x/Kconfig @@ -0,0 +1,15 @@ +# STMicroelectronics STM32U3 MCU series + +# Copyright (c) 2025 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32U3X + select ARM + select CPU_CORTEX_M33 + select CPU_HAS_ARM_SAU + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select ARMV8_M_DSP + select CPU_CORTEX_M_HAS_DWT + select HAS_STM32CUBE + select SOC_EARLY_INIT_HOOK diff --git a/soc/st/stm32/stm32u3x/Kconfig.defconfig b/soc/st/stm32/stm32u3x/Kconfig.defconfig new file mode 100644 index 00000000000..bcc32a88ddb --- /dev/null +++ b/soc/st/stm32/stm32u3x/Kconfig.defconfig @@ -0,0 +1,11 @@ +# STMicroelectronics STM32U3 MCU series + +# Copyright (c) 2025 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_STM32U3X + +config NUM_IRQS + default 125 + +endif # SOC_SERIES_STM32U3X diff --git a/soc/st/stm32/stm32u3x/Kconfig.soc b/soc/st/stm32/stm32u3x/Kconfig.soc new file mode 100644 index 00000000000..42cc6963394 --- /dev/null +++ b/soc/st/stm32/stm32u3x/Kconfig.soc @@ -0,0 +1,18 @@ +# STMicroelectronics STM32U3 MCU series + +# Copyright (c) 2025 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32U3X + bool + select SOC_FAMILY_STM32 + +config SOC_SERIES + default "stm32u3x" if SOC_SERIES_STM32U3X + +config SOC_STM32U385XX + bool + select SOC_SERIES_STM32U3X + +config SOC + default "stm32u385xx" if SOC_STM32U385XX diff --git a/soc/st/stm32/stm32u3x/soc.c b/soc/st/stm32/stm32u3x/soc.c new file mode 100644 index 00000000000..0b134d8d558 --- /dev/null +++ b/soc/st/stm32/stm32u3x/soc.c @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2025 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief System/hardware module for STM32U3 processor + */ + +#include +#include +#include +#include +#include +#include + +#include + +#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL +LOG_MODULE_REGISTER(soc); + +/** + * @brief Perform basic hardware initialization at boot. + * + * This needs to be run from the very beginning. + */ +void soc_early_init_hook(void) +{ + /* Enable ART Accelerator prefetch */ + sys_cache_instr_enable(); + + /* Update CMSIS SystemCoreClock variable (HCLK) */ + /* The MSIS is used as system clock source after startup from reset,configured at 12 MHz. */ + SystemCoreClock = 12000000; + + /* Enable power controller bus clock for other drivers */ + LL_AHB1_GRP2_EnableClock(LL_AHB1_GRP2_PERIPH_PWR); +} diff --git a/soc/st/stm32/stm32u3x/soc.h b/soc/st/stm32/stm32u3x/soc.h new file mode 100644 index 00000000000..773e7370be4 --- /dev/null +++ b/soc/st/stm32/stm32u3x/soc.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2025 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file SoC configuration macros for the STM32U3 family processors. + */ + +#ifndef _STM32U3_SOC_H_ +#define _STM32U3_SOC_H_ + +#ifndef _ASMLANGUAGE + +#include + +#endif /* !_ASMLANGUAGE */ + +#endif /* _STM32U3_SOC_H_ */