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boards: max10/nios2: remove remaining boards/socs 

Remove remaining nios2 based boards and soc files.

Part of #89280

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
pull/86868/merge
Anas Nashif 2 months ago
parent
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53 changed files with 0 additions and 22596 deletions
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  1. 9
      MAINTAINERS.yml
  2. 10
      boards/altr/index.rst
  3. 5
      boards/altr/max10/Kconfig.altera_max10
  4. 13
      boards/altr/max10/Kconfig.defconfig
  5. 42
      boards/altr/max10/altera_max10.dts
  6. 7
      boards/altr/max10/altera_max10.yaml
  7. 7
      boards/altr/max10/altera_max10_defconfig
  8. 4
      boards/altr/max10/board.cmake
  9. 6
      boards/altr/max10/board.yml
  10. BIN
      boards/altr/max10/doc/img/Altera_MAX10_switches.jpg
  11. BIN
      boards/altr/max10/doc/img/altera_max10.jpg
  12. 324
      boards/altr/max10/doc/index.rst
  13. 9
      boards/common/nios2.board.cmake
  14. 1
      scripts/footprint/plan.txt
  15. 137
      scripts/support/quartus-flash.py
  16. 7
      soc/altr/zephyr_nios2f/CMakeLists.txt
  17. 7
      soc/altr/zephyr_nios2f/Kconfig
  18. 24
      soc/altr/zephyr_nios2f/Kconfig.defconfig
  19. 8
      soc/altr/zephyr_nios2f/Kconfig.soc
  20. 19
      soc/altr/zephyr_nios2f/cpu/README
  21. 31
      soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.qpf
  22. 412
      soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.qsf
  23. 1249
      soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.qsys
  24. BIN
      soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.sof
  25. 18989
      soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.sopcinfo
  26. 121
      soc/altr/zephyr_nios2f/cpu/ghrd_10m50da_top.v
  27. 28
      soc/altr/zephyr_nios2f/cpu/ghrd_timing.sdc
  28. 10
      soc/altr/zephyr_nios2f/include/layout.h
  29. 109
      soc/altr/zephyr_nios2f/include/linker.h
  30. 567
      soc/altr/zephyr_nios2f/include/system.h
  31. 20
      soc/altr/zephyr_nios2f/linker.ld
  32. 13
      soc/altr/zephyr_nios2f/soc.h
  33. 2
      soc/altr/zephyr_nios2f/soc.yml
  34. 8
      tests/boards/altera_max10/i2c_master/CMakeLists.txt
  35. 2
      tests/boards/altera_max10/i2c_master/README.txt
  36. 3
      tests/boards/altera_max10/i2c_master/prj.conf
  37. 129
      tests/boards/altera_max10/i2c_master/src/i2c_master.c
  38. 4
      tests/boards/altera_max10/i2c_master/testcase.yaml
  39. 13
      tests/boards/altera_max10/msgdma/CMakeLists.txt
  40. 2
      tests/boards/altera_max10/msgdma/README.txt
  41. 2
      tests/boards/altera_max10/msgdma/prj.conf
  42. 101
      tests/boards/altera_max10/msgdma/src/dma.c
  43. 4
      tests/boards/altera_max10/msgdma/testcase.yaml
  44. 8
      tests/boards/altera_max10/qspi/CMakeLists.txt
  45. 2
      tests/boards/altera_max10/qspi/README.txt
  46. 4
      tests/boards/altera_max10/qspi/prj.conf
  47. 74
      tests/boards/altera_max10/qspi/src/qspi_flash.c
  48. 6
      tests/boards/altera_max10/qspi/testcase.yaml
  49. 8
      tests/boards/altera_max10/sysid/CMakeLists.txt
  50. 2
      tests/boards/altera_max10/sysid/README.txt
  51. 1
      tests/boards/altera_max10/sysid/prj.conf
  52. 29
      tests/boards/altera_max10/sysid/src/sysid.c
  53. 4
      tests/boards/altera_max10/sysid/testcase.yaml

9
MAINTAINERS.yml
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@ -3163,18 +3163,9 @@ NIOS-2 arch: @@ -3163,18 +3163,9 @@ NIOS-2 arch:
- nashif
files:
- arch/nios2/
- dts/nios2/intel/
- boards/common/nios2.board.cmake
- soc/altr/*nios2*/
- include/zephyr/arch/nios2/
- tests/boards/altera_max10/
- boards/qemu/nios2/
- boards/altr/max10/
- scripts/support/quartus-flash.py
labels:
- "area: NIOS2"
tests:
- boards.altera_max10
nRF BSIM:
status: maintained

10
boards/altr/index.rst
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@ -1,10 +0,0 @@ @@ -1,10 +0,0 @@
.. _boards-altera:
Altera Corporation
##################
.. toctree::
:maxdepth: 1
:glob:
**/*

5
boards/altr/max10/Kconfig.altera_max10
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@ -1,5 +0,0 @@ @@ -1,5 +0,0 @@
# SPDX-License-Identifier: Apache-2.0
# Copyright (c) 2018 Intel
config BOARD_ALTERA_MAX10
select SOC_ZEPHYR_NIOS2F

13
boards/altr/max10/Kconfig.defconfig
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@ -1,13 +0,0 @@ @@ -1,13 +0,0 @@
# SPDX-License-Identifier: Apache-2.0
# Copyright (c) 2018 Intel
if BOARD_ALTERA_MAX10
if FLASH
config SOC_FLASH_NIOS2_QSPI
default y
endif # FLASH
endif # BOARD_ALTERA_MAX10

42
boards/altr/max10/altera_max10.dts
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@ -1,42 +0,0 @@ @@ -1,42 +0,0 @@
/* SPDX-License-Identifier: Apache-2.0 */
/* Copyright (c) 2018 Intel */
/dts-v1/;
#include <mem.h>
#include <intel/nios2f.dtsi>
/ {
model = "altera_max10";
compatible = "altr,nios2-max10";
aliases {
uart-0 = &uart0;
};
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
};
};
&uart0 {
status = "okay";
current-speed = <115200>;
};
&i2c0 {
status = "okay";
clock-frequency = <I2C_BITRATE_ULTRA>;
};
&qspi {
status = "okay";
n25q512ax3: n25q512ax3@0 {
compatible = "altr,nios2-qspi-nor";
size = <DT_SIZE_M(64*8)>; /* in bits */
reg = <0>;
};
};

7
boards/altr/max10/altera_max10.yaml
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@ -1,7 +0,0 @@ @@ -1,7 +0,0 @@
identifier: altera_max10
name: Altera MAX10
type: mcu
arch: nios2
toolchain:
- zephyr
vendor: altr

7
boards/altr/max10/altera_max10_defconfig
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@ -1,7 +0,0 @@ @@ -1,7 +0,0 @@
# SPDX-License-Identifier: Apache-2.0
# Copyright (c) 2018 Intel
CONFIG_HAS_ALTERA_HAL=y
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y

4
boards/altr/max10/board.cmake
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@ -1,4 +0,0 @@ @@ -1,4 +0,0 @@
# SPDX-License-Identifier: Apache-2.0
board_runner_args(nios2 "--cpu-sof=${ZEPHYR_BASE}/soc/nios2/nios2f-zephyr/cpu/ghrd_10m50da.sof")
include(${ZEPHYR_BASE}/boards/common/nios2.board.cmake)

6
boards/altr/max10/board.yml
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@ -1,6 +0,0 @@ @@ -1,6 +0,0 @@
board:
name: altera_max10
full_name: MAX10
vendor: altr
socs:
- name: zephyr_nios2f

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324
boards/altr/max10/doc/index.rst
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@ -1,324 +0,0 @@ @@ -1,324 +0,0 @@
.. zephyr:board:: altera_max10
Overview
********
The Zephyr kernel is supported on the Altera MAX10 Rev C development kit, using
the Nios II Gen 2 soft CPU.
Hardware
********
DIP Switch settings
===================
There are two sets of switches on the back of the board. Of particular
importance is SW2:
* Switch 2 (CONFIG_SEL) should be in the OFF (up) position so that the first
boot image is CFM0
* Switch 3 (VTAP_BYPASS) needs to be in the ON (down) position or the flashing
scripts won't work
* Switch 4 (HSMC_BYPASSN) should be OFF (up)
.. image:: img/Altera_MAX10_switches.jpg
:align: center
:alt: Altera's MAX* 10 Switches
Other switches are user switches, their position is application-specific.
Necessary Software
==================
You will need the Altera Quartus SDK in order to work with this device. The
`Altera Lite Distribution`_ of Quartus may be obtained without
charge.
For your convenience using the SDK tools (such as ``nios2-configure-sof``),
you should put the binaries provided by the SDK
in your path. Below is an example, adjust ALTERA_BASE to where you installed the
SDK:
.. code-block:: console
export ALTERA_BASE=/opt/altera_lite/16.0
export PATH=$PATH:$ALTERA_BASE/quartus/bin:$ALTERA_BASE/nios2eds/bin
You may need to adjust your udev rules so that you can talk to the USB Blaster
II peripheral, which is the built-in JTAG interface for this device.
The following works for Fedora 23:
.. code-block:: console
# For Altera USB-Blaster permissions.
SUBSYSTEM=="usb",\
ENV{DEVTYPE}=="usb_device",\
ATTR{idVendor}=="09fb",\
ATTR{idProduct}=="6010",\
MODE="0666",\
NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}",\
RUN+="/bin/chmod 0666 %c"
SUBSYSTEM=="usb",\
ENV{DEVTYPE}=="usb_device",\
ATTR{idVendor}=="09fb",\
ATTR{idProduct}=="6810",\
MODE="0666",\
NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}",\
RUN+="/bin/chmod 0666 %c"
You can test connectivity with the SDK jtagconfig tool, you should see something
like:
.. code-block:: console
$ jtagconfig
1) USB-BlasterII [1-1.2]
031050DD 10M50DA(.|ES)/10M50DC
020D10DD VTAP10
Reference CPU
=============
A reference CPU design of a Nios II/f core is included in the Zephyr tree
in the :zephyr_file:`soc/altr/zephyr_nios2f/cpu` directory.
Flash this CPU using the ``nios2-configure-sof`` SDK tool with the FPGA
configuration file
:zephyr_file:`soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.sof`:
.. code-block:: console
$ nios2-configure-sof ghrd_10m50da.sof
This CPU is a Nios II/F core with a 16550 UART, JTAG UART, and the Avalon Timer.
For any Nios II SOC definition, you can find out more details about the CPU
configuration by inspecting system.h in the SOC's include directory.
Console Output
==============
16550 UART
----------
By default, the kernel is configured to send console output to the 16550 UART.
You can monitor this on your workstation by connecting to the top right mini USB
port on the board (it will show up in /dev as a ttyUSB node), and then running
minicom with flow control disabled, 115200-8N1 settings.
JTAG UART
---------
You can also have it send its console output to the JTAG UART.
Enable ``jtag_uart`` node in :file:`altera_max10.dts` or overlay file:
.. code-block:: devicetree
&jtag_uart {
status = "okay";
current-speed = <115200>;
};
To view these messages on your local workstation, run the terminal application
in the SDK:
.. code-block:: console
$ nios2-terminal
Programming and Debugging
*************************
.. zephyr:board-supported-runners::
Flashing
========
Flashing Kernel into UFM
------------------------
The usual ``flash`` target will work with the ``altera_max10`` board
configuration. Here is an example for the :zephyr:code-sample:`hello_world`
application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: altera_max10
:goals: flash
Refer to :ref:`build_an_application` and :ref:`application_run` for
more details.
This provisions the Zephyr kernel and the CPU configuration onto the board,
using the scripts/support/quartus-flash.py script. After it completes the kernel
will immediately boot.
Flashing Kernel directly into RAM over JTAG
-------------------------------------------
The SDK included the nios2-download tool which will let you flash a kernel
directly into RAM and then boot it from the __start symbol.
In order for this to work, your entire kernel must be located in RAM. Make sure
the following config options are disabled:
.. code-block:: cfg
CONFIG_XIP=n
CONFIG_INCLUDE_RESET_VECTOR=n
Then, after building your kernel, push it into device's RAM by running
this from the build directory:
.. code-block:: console
$ nios2-download --go zephyr/zephyr.elf
If you have a console session running (either minicom or nios2-terminal) you
should see the application's output. There are additional arguments you can pass
to nios2-download so that it spawns a GDB server that you can connect to,
although it's typically simpler to just use nios2-gdb-server as described below.
Debugging
=========
The Altera SDK includes a GDB server which can be used to debug a MAX10 board.
You can either debug a running image that was flashed onto the device in User
Flash Memory (UFM), or load an image over the JTAG using GDB.
Debugging With UFM Flashed Image
--------------------------------
You can debug an application in the usual way. Here is an example.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: altera_max10
:goals: debug
You will see output similar to the following:
.. code-block:: console
Nios II GDB server running on port 3335
Ignoring --stop option because --tcpport also specified
GNU gdb (GDB) 7.11.0.20160511-git
Copyright (C) 2016 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law. Type "show copying"
and "show warranty" for details.
This GDB was configured as "--host=x86_64-pokysdk-linux --target=nios2-zephyr-elf".
Type "show configuration" for configuration details.
For bug reporting instructions, please see:
<http://www.gnu.org/software/gdb/bugs/>.
Find the GDB manual and other documentation resources online at:
<http://www.gnu.org/software/gdb/documentation/>.
For help, type "help".
Type "apropos word" to search for commands related to "word"...
Reading symbols from /projects/zephyr/samples/hello_world/build/zephyr/zephyr.elf...done.
Remote debugging using :3335
Using cable "USB-BlasterII [3-1.3]", device 1, instance 0x00
Resetting and pausing target processor: OK
Listening on port 3335 for connection from GDB: accepted
isr_tables_syms () at /projects/zephyr/arch/common/isr_tables.c:63
63 GEN_ABSOLUTE_SYM(__ISR_LIST_SIZEOF, sizeof(struct _isr_list));
(gdb) b z_prep_c
Breakpoint 1 at 0xdf0: file /projects/zephyr/arch/nios2/core/prep_c.c, line 36.
(gdb) b z_cstart
Breakpoint 2 at 0x1254: file /projects/zephyr/kernel/init.c, line 348.
(gdb) c
Continuing.
Breakpoint 2, z_cstart () at /projects/zephyr/kernel/init.c:348
348 {
(gdb)
To start debugging manually:
.. code-block:: console
nios2-gdb-server --tcpport 1234 --stop --reset-target
And then connect with GDB from the build directory:
.. code-block:: console
nios2-poky-elf-gdb zephyr/zephyr.elf -ex "target remote :1234"
Debugging With JTAG Flashed Image
---------------------------------
In order for this to work, execute-in-place must be disabled, since the GDB
'load' command can only put text and data in RAM. Ensure this is in your
configuration:
.. code-block:: cfg
CONFIG_XIP=n
It is OK for this procedure to leave the reset vector enabled, unlike
nios2-download (which errors out if it finds sections outside of SRAM) it will
be ignored.
In a terminal, launch the nios2 GDB server. It doesn't matter what kernel (if
any) is on the device, but you should have at least flashed a CPU using
nios2-configure-sof. You can leave this process running.
.. code-block:: console
$ nios2-gdb-server --tcpport 1234 --tcppersist --init-cache --reset-target
Build your Zephyr kernel, and load it into a GDB built for Nios II (included in
the Zephyr SDK) from the build directory:
.. code-block:: console
$ nios2-poky-elf-gdb zephyr/zephyr.elf
Then connect to the GDB server:
.. code-block:: console
(gdb) target remote :1234
And then load the kernel image over the wire. The CPU will not start from the
reset vector, instead it will boot from the __start symbol:
.. code-block:: console
(gdb) load
Loading section reset, size 0xc lma 0x0
Loading section exceptions, size 0x1b0 lma 0x400020
Loading section text, size 0x8df0 lma 0x4001d0
Loading section devconfig, size 0x30 lma 0x408fc0
Loading section rodata, size 0x3f4 lma 0x408ff0
Loading section datas, size 0x888 lma 0x4093e4
Loading section initlevel, size 0x30 lma 0x409c6c
Loading section _k_task_list, size 0x58 lma 0x409c9c
Loading section _k_task_ptr, size 0x8 lma 0x409cf4
Loading section _k_event_list, size 0x10 lma 0x409cfc
Start address 0x408f54, load size 40184
Transfer rate: 417 KB/sec, 368 bytes/write.
After this is done you may set breakpoints and continue execution. If you ever want to reset the CPU, issue the 'load' command again.
References
**********
* `CPU Documentation <https://www.altera.com/en_US/pdfs/literature/hb/nios2/n2cpu-nii5v1gen2.pdf>`_
* `Nios II Processor Booting Methods in MAX 10 FPGA Devices <https://www.altera.com/en_US/pdfs/literature/an/an730.pdf>`_
* `Embedded Peripherals IP User Guide <https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_embedded_ip.pdf>`_
* `MAX 10 FPGA Configuration User Guide <https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/max-10/ug_m10_config.pdf>`_
* `MAX 10 FPGA Development Kit User Guide <https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug-max10m50-fpga-dev-kit.pdf>`_
* `Nios II Command-Line Tools <https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/nios2/edh_ed51004.pdf>`_
* `Quartus II Scripting Reference Manual <https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/manual/tclscriptrefmnl.pdf>`_
.. _Altera Lite Distribution: https://www.intel.com/content/www/us/en/collections/products/fpga/software/downloads.html

9
boards/common/nios2.board.cmake
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@ -1,9 +0,0 @@ @@ -1,9 +0,0 @@
# SPDX-License-Identifier: Apache-2.0
board_set_flasher_ifnset(nios2)
board_set_debugger_ifnset(nios2)
board_finalize_runner_args(nios2
# TODO: merge this script into nios2.py
"--quartus-flash=${ZEPHYR_BASE}/scripts/support/quartus-flash.py"
)

1
scripts/footprint/plan.txt
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@ -4,7 +4,6 @@ footprints,default,disco_l475_iot1,tests/benchmarks/footprints,,benchmark.kernel @@ -4,7 +4,6 @@ footprints,default,disco_l475_iot1,tests/benchmarks/footprints,,benchmark.kernel
footprints,userspace,disco_l475_iot1,tests/benchmarks/footprints,-DCONF_FILE=prj_userspace.conf,benchmark.kernel.footprints.userspace
footprints,default,nrf5340dk/nrf5340/cpuapp,tests/benchmarks/footprints,,benchmark.kernel.footprints.default
footprints,default,nrf51dk/nrf51822,tests/benchmarks/footprints,,benchmark.kernel.footprints.default
footprints,default,altera_max10,tests/benchmarks/footprints,,benchmark.kernel.footprints.default
footprints,default,hifive1@B,tests/benchmarks/footprints,,benchmark.kernel.footprints.default
footprints,default,intel_ehl_crb,tests/benchmarks/footprints,,benchmark.kernel.footprints.default
footprints,userspace,intel_ehl_crb,tests/benchmarks/footprints,-DCONF_FILE=prj_userspace.conf,benchmark.kernel.footprints.userspace

137
scripts/support/quartus-flash.py
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@ -1,137 +0,0 @@ @@ -1,137 +0,0 @@
#!/usr/bin/env python3
# SPDX-License-Identifier: Apache-2.0
import subprocess
import tempfile
import argparse
import os
import string
import sys
quartus_cpf_template = """<?xml version="1.0" encoding="US-ASCII" standalone="yes"?>
<cof>
<output_filename>${OUTPUT_FILENAME}</output_filename>
<n_pages>1</n_pages>
<width>1</width>
<mode>14</mode>
<sof_data>
<user_name>Page_0</user_name>
<page_flags>1</page_flags>
<bit0>
<sof_filename>${SOF_FILENAME}<compress_bitstream>1</compress_bitstream></sof_filename>
</bit0>
</sof_data>
<version>10</version>
<create_cvp_file>0</create_cvp_file>
<create_hps_iocsr>0</create_hps_iocsr>
<auto_create_rpd>0</auto_create_rpd>
<rpd_little_endian>1</rpd_little_endian>
<options>
<map_file>1</map_file>
</options>
<MAX10_device_options>
<por>0</por>
<io_pullup>1</io_pullup>
<config_from_cfm0_only>0</config_from_cfm0_only>
<isp_source>0</isp_source>
<verify_protect>0</verify_protect>
<epof>0</epof>
<ufm_source>2</ufm_source>
<ufm_filepath>${KERNEL_FILENAME}</ufm_filepath>
</MAX10_device_options>
<advanced_options>
<ignore_epcs_id_check>2</ignore_epcs_id_check>
<ignore_condone_check>2</ignore_condone_check>
<plc_adjustment>0</plc_adjustment>
<post_chain_bitstream_pad_bytes>-1</post_chain_bitstream_pad_bytes>
<post_device_bitstream_pad_bytes>-1</post_device_bitstream_pad_bytes>
<bitslice_pre_padding>1</bitslice_pre_padding>
</advanced_options>
</cof>
"""
# XXX Do we care about FileRevision, DefaultMfr, PartName? Do they need
# to be parameters? So far seems to work across 2 different boards, leave
# this alone for now.
quartus_pgm_template = """/* Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition */
JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Cfg)
Device PartName(10M50DAF484ES) Path("${POF_DIR}/") File("${POF_FILE}") MfrSpec(OpMask(1));
ChainEnd;
AlteraBegin;
ChainType(JTAG);
AlteraEnd;"""
def create_pof(input_sof, kernel_hex):
"""given an input CPU .sof file and a kernel binary, return a file-like
object containing .pof data suitable for flashing onto the device"""
t = string.Template(quartus_cpf_template)
output_pof = tempfile.NamedTemporaryFile(suffix=".pof")
input_sof = os.path.abspath(input_sof)
kernel_hex = os.path.abspath(kernel_hex)
# These tools are very stupid and freak out if the desired filename
# extensions are used. The kernel image must have extension .hex
with tempfile.NamedTemporaryFile(suffix=".cof") as temp_xml:
xml = t.substitute(SOF_FILENAME=input_sof,
OUTPUT_FILENAME=output_pof.name,
KERNEL_FILENAME=kernel_hex)
temp_xml.write(bytes(xml, 'UTF-8'))
temp_xml.flush()
cmd = ["quartus_cpf", "-c", temp_xml.name]
try:
subprocess.check_output(cmd)
except subprocess.CalledProcessError as cpe:
sys.exit(cpe.output.decode("utf-8") +
"\nFailed to create POF file")
return output_pof
def flash_kernel(device_id, input_sof, kernel_hex):
pof_file = create_pof(input_sof, kernel_hex)
with tempfile.NamedTemporaryFile(suffix=".cdf") as temp_cdf:
dname, fname = os.path.split(pof_file.name)
t = string.Template(quartus_pgm_template)
cdf = t.substitute(POF_DIR=dname, POF_FILE=fname)
temp_cdf.write(bytes(cdf, 'UTF-8'))
temp_cdf.flush()
cmd = ["quartus_pgm", "-c", device_id, temp_cdf.name]
try:
subprocess.check_output(cmd)
except subprocess.CalledProcessError as cpe:
sys.exit(cpe.output.decode("utf-8") +
"\nFailed to flash image")
pof_file.close()
def main():
parser = argparse.ArgumentParser(description="Flash zephyr onto Altera boards", allow_abbrev=False)
parser.add_argument("-s", "--sof",
help=".sof file with Nios II CPU configuration")
parser.add_argument("-k", "--kernel",
help="Zephyr kernel image to place into UFM in Intel HEX format")
parser.add_argument("-d", "--device",
help="Remote device identifier / cable name. Default is "
"USB-BlasterII. Run jtagconfig -n if unsure.",
default="USB-BlasterII")
args = parser.parse_args()
flash_kernel(args.device, args.sof, args.kernel)
if __name__ == "__main__":
main()

7
soc/altr/zephyr_nios2f/CMakeLists.txt
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# Copyright (c) 2016 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
zephyr_include_directories(include)
zephyr_include_directories(.)
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")

7
soc/altr/zephyr_nios2f/Kconfig
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# Copyright (c) 2016 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
config SOC_ZEPHYR_NIOS2F
select NIOS2
select HAS_MUL_INSTRUCTION
select HAS_DIV_INSTRUCTION

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soc/altr/zephyr_nios2f/Kconfig.defconfig
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# Copyright (c) 2016 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
if SOC_ZEPHYR_NIOS2F
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 50000000
config ALTERA_AVALON_SYSID
def_bool y
config ALTERA_AVALON_QSPI
def_bool y
depends on SOC_FLASH_NIOS2_QSPI
config ALTERA_AVALON_I2C
def_bool y
depends on I2C_NIOS2
config ALTERA_AVALON_MSGDMA
def_bool y
depends on DMA_NIOS2_MSGDMA
endif # SOC_ZEPHYR_NIOS2F

8
soc/altr/zephyr_nios2f/Kconfig.soc
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# Copyright (c) 2016 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
config SOC_ZEPHYR_NIOS2F
bool
config SOC
default "zephyr_nios2f" if SOC_ZEPHYR_NIOS2F

19
soc/altr/zephyr_nios2f/cpu/README
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These files are a Nios II/F CPU design provided by Altera for evaluating
Zephyr on Nios II. This design is intended for the Altera MAX10 10M50 Rec C
development board. You can find more information about this board here:
https://www.altera.com/products/boards_and_kits/dev-kits/altera/max-10-fpga-development-kit.html
You will need the Quartus SDK in order to modify this CPU or flash it onto
a supported device. The Lite version of Quartus may be obtained without charge
from the following link:
http://dl.altera.com/?edition=lite
To flash this CPU, use the nios2-configure-sof tool:
$ nios2-configure-sof ghrd_10m50da.sof
The 'make flash' target will also package up the kernel and CPU into a single
.pof file which will then put the image onto the device using quartus_pgm tool.

31
soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.qpf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, the Altera Quartus Prime License Agreement,
# the Altera MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Altera and sold by Altera or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 16.0.0 Build 208 04/06/2016 SJ Standard Edition
# Date created = 16:01:48 April 27, 2016
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "16.0"
DATE = "16:01:48 April 27, 2016"
# Revisions
PROJECT_REVISION = "ghrd_10m50da"

412
soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.qsf
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@ -1,412 +0,0 @@ @@ -1,412 +0,0 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, the Altera Quartus Prime License Agreement,
# the Altera MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Altera and sold by Altera or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 16.0.0 Build 208 04/06/2016 SJ Standard Edition
# Date created = 16:01:48 April 27, 2016
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# ghrd_10m50da_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "MAX 10"
set_global_assignment -name DEVICE 10M50DAF484C6GES
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:01:48 APRIL 27, 2016"
set_global_assignment -name LAST_QUARTUS_VERSION "17.0.0 Standard Edition"
set_global_assignment -name TOP_LEVEL_ENTITY ghrd_10m50da_top
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE ON
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name UNIPHY_TEMP_VER_CODE 1590306432
set_global_assignment -name ECO_REGENERATE_REPORT ON
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name ENABLE_SIGNALTAP ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
set_global_assignment -name QII_AUTO_PACKED_REGISTERS NORMAL
set_global_assignment -name MUX_RESTRUCTURE OFF
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE COMP IMAGE"
set_global_assignment -name ENABLE_OCT_DONE OFF
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name SEED 16
set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
set_global_assignment -name ROUTER_REGISTER_DUPLICATION ON
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
set_location_assignment PIN_N14 -to clk_ddr3_100_p
set_location_assignment PIN_M8 -to clk_25_max10
set_location_assignment PIN_N5 -to clk_10_adc
set_location_assignment PIN_P11 -to clk_lvds_125_p
set_location_assignment PIN_T20 -to user_led[0]
set_location_assignment PIN_U22 -to user_led[1]
set_location_assignment PIN_U21 -to user_led[2]
set_location_assignment PIN_AA21 -to user_led[3]
set_location_assignment PIN_AA22 -to user_led[4]
set_location_assignment PIN_L22 -to user_pb[0]
set_location_assignment PIN_M21 -to user_pb[1]
set_location_assignment PIN_M22 -to user_pb[2]
set_location_assignment PIN_N21 -to user_pb[3]
set_location_assignment PIN_H21 -to user_dipsw[0]
set_location_assignment PIN_H22 -to user_dipsw[1]
set_location_assignment PIN_J21 -to user_dipsw[2]
set_location_assignment PIN_J22 -to user_dipsw[3]
set_location_assignment PIN_G19 -to user_dipsw[4]
set_location_assignment PIN_Y19 -to uart_rx
set_location_assignment PIN_W18 -to uart_tx
set_location_assignment PIN_Y6 -to enet_mdc
set_location_assignment PIN_Y5 -to enet_mdio
set_location_assignment PIN_T5 -to enet_gtx_clk
set_location_assignment PIN_V7 -to enet_intn
set_location_assignment PIN_V8 -to enet_resetn
set_location_assignment PIN_P3 -to enet_rx_clk
set_location_assignment PIN_P1 -to enet_rx_col
set_location_assignment PIN_N8 -to enet_rx_crs
set_location_assignment PIN_N9 -to enet_rx_d[0]
set_location_assignment PIN_T1 -to enet_rx_d[1]
set_location_assignment PIN_N1 -to enet_rx_d[2]
set_location_assignment PIN_T3 -to enet_rx_d[3]
set_location_assignment PIN_T2 -to enet_rx_dv
set_location_assignment PIN_U2 -to enet_rx_er
set_location_assignment PIN_E10 -to enet_tx_clk
set_location_assignment PIN_R5 -to enet_tx_d[0]
set_location_assignment PIN_P5 -to enet_tx_d[1]
set_location_assignment PIN_W1 -to enet_tx_d[2]
set_location_assignment PIN_W2 -to enet_tx_d[3]
set_location_assignment PIN_R4 -to enet_tx_en
set_location_assignment PIN_P4 -to enet_tx_er
set_location_assignment PIN_R9 -to enet_led_link100
set_location_assignment PIN_B2 -to qspi_clk
set_location_assignment PIN_C6 -to qspi_io[0]
set_location_assignment PIN_C3 -to qspi_io[1]
set_location_assignment PIN_C5 -to qspi_io[2]
set_location_assignment PIN_B1 -to qspi_io[3]
set_location_assignment PIN_C2 -to qspi_csn
set_location_assignment PIN_C22 -to mem_a[13]
set_location_assignment PIN_J14 -to mem_a[12]
set_location_assignment PIN_E20 -to mem_a[11]
set_location_assignment PIN_Y20 -to mem_a[10]
set_location_assignment PIN_E22 -to mem_a[9]
set_location_assignment PIN_D22 -to mem_a[8]
set_location_assignment PIN_B20 -to mem_a[7]
set_location_assignment PIN_C20 -to mem_a[4]
set_location_assignment PIN_A21 -to mem_a[2]
set_location_assignment PIN_D19 -to mem_a[1]
set_location_assignment PIN_E21 -to mem_a[6]
set_location_assignment PIN_F19 -to mem_a[5]
set_location_assignment PIN_U20 -to mem_a[3]
set_location_assignment PIN_V20 -to mem_a[0]
set_location_assignment PIN_W22 -to mem_ba[2]
set_location_assignment PIN_N18 -to mem_ba[1]
set_location_assignment PIN_V22 -to mem_ba[0]
set_location_assignment PIN_U19 -to mem_cas_n[0]
set_location_assignment PIN_D18 -to mem_ck[0]
set_location_assignment PIN_E18 -to mem_ck_n[0]
set_location_assignment PIN_W20 -to mem_cke[0]
set_location_assignment PIN_Y22 -to mem_cs_n[0]
set_location_assignment PIN_J15 -to mem_dm[0]
set_location_assignment PIN_K19 -to mem_dq[7]
set_location_assignment PIN_H20 -to mem_dq[6]
set_location_assignment PIN_J20 -to mem_dq[5]
set_location_assignment PIN_H19 -to mem_dq[4]
set_location_assignment PIN_K18 -to mem_dq[3]
set_location_assignment PIN_H18 -to mem_dq[2]
set_location_assignment PIN_K20 -to mem_dq[1]
set_location_assignment PIN_J18 -to mem_dq[0]
set_location_assignment PIN_K14 -to mem_dqs[0]
set_location_assignment PIN_W19 -to mem_odt[0]
set_location_assignment PIN_V18 -to mem_ras_n[0]
set_location_assignment PIN_B22 -to mem_reset_n
set_location_assignment PIN_Y21 -to mem_we_n[0]
set_location_assignment PIN_L20 -to mem_dq[8]
set_location_assignment PIN_M18 -to mem_dq[9]
set_location_assignment PIN_M20 -to mem_dq[10]
set_location_assignment PIN_M14 -to mem_dq[11]
set_location_assignment PIN_L18 -to mem_dq[12]
set_location_assignment PIN_M15 -to mem_dq[13]
set_location_assignment PIN_L19 -to mem_dq[14]
set_location_assignment PIN_N20 -to mem_dq[15]
set_location_assignment PIN_L14 -to mem_dqs[1]
set_location_assignment PIN_N19 -to mem_dm[1]
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL" -to clk_ddr3_100_p
set_instance_assignment -name IO_STANDARD "2.5 V" -to clk_50_max10
set_instance_assignment -name IO_STANDARD "2.5 V" -to clk_25_max10
set_instance_assignment -name IO_STANDARD LVDS -to clk_lvds_125_p
set_instance_assignment -name IO_STANDARD "2.5 V" -to clk_10_adc
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to fpga_resetn
set_instance_assignment -name IO_STANDARD "1.5 V" -to user_led[0]
set_instance_assignment -name IO_STANDARD "1.5 V" -to user_led[1]
set_instance_assignment -name IO_STANDARD "1.5 V" -to user_led[2]
set_instance_assignment -name IO_STANDARD "1.5 V" -to user_led[3]
set_instance_assignment -name IO_STANDARD "1.5 V" -to user_led[4]
set_instance_assignment -name IO_STANDARD "1.5 V" -to user_pb[0]
set_instance_assignment -name IO_STANDARD "1.5 V" -to user_pb[1]
set_instance_assignment -name IO_STANDARD "1.5 V" -to user_pb[2]
set_instance_assignment -name IO_STANDARD "1.5 V" -to user_pb[3]
set_instance_assignment -name IO_STANDARD "1.5 V" -to user_dipsw[0]
set_instance_assignment -name IO_STANDARD "1.5 V" -to user_dipsw[1]
set_instance_assignment -name IO_STANDARD "1.5 V" -to user_dipsw[2]
set_instance_assignment -name IO_STANDARD "1.5 V" -to user_dipsw[3]
set_instance_assignment -name IO_STANDARD "1.5 V" -to user_dipsw[4]
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to user_led[0]
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to user_led[2]
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to user_pb[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_gtx_clk
set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_intn
set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_resetn
set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_rx_clk
set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_rx_col
set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_rx_crs
set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_rx_d[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_rx_d[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_rx_d[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_rx_d[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_rx_dv
set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_rx_er
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to enet_tx_clk
set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_tx_d[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_tx_d[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_tx_d[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_tx_d[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_tx_en
set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_tx_er
set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_led_link100
set_instance_assignment -name GLOBAL_SIGNAL_CLKCTRL_LOCATION CLKCTRL_G2 -to enet_rx_clk
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_clk
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_csn
set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[2] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[2] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[3] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[3] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[4] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[4] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[5] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[5] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[6] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[6] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[7] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[7] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL" -to mem_dqs[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dqs[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL" -to mem_dqs_n[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dqs_n[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL" -to mem_ck[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_ck[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL" -to mem_ck_n[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_ck_n[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_a[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_a[10] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_a[11] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_a[12] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_a[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_a[2] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_a[3] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_a[4] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_a[5] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_a[6] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_a[7] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_a[8] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_a[9] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_ba[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_ba[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_ba[2] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_cs_n[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_we_n[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_ras_n[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_cas_n[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_cke[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_odt[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD 1.5V -to mem_reset_n -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dm[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dm[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name CKN_CK_PAIR ON -from mem_ck_n[0] -to mem_ck[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[2] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[3] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[4] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[5] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[6] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[7] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dm[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name DM_PIN ON -to mem_dm[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[2] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[3] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[4] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[5] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[6] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[7] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dm[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dqs[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dqs_n[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[10] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[11] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[12] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[2] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[3] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[4] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[5] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[6] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[7] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[8] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[9] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ba[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ba[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ba[2] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_cs_n[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_we_n[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ras_n[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_cas_n[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_cke[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_odt[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_reset_n -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ck[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ck_n[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to q_sys_inst|mem_if_ddr3_emif_0|p0|umemphy|ureset|phy_reset_n -tag __q_sys_mem_if_ddr3_emif_0_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to q_sys_inst|mem_if_ddr3_emif_0|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[0] -tag __q_sys_mem_if_ddr3_emif_0_p0
set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to q_sys_inst|mem_if_ddr3_emif_0 -tag __q_sys_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[13] -tag __q_sys_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[13] -tag __q_sys_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to mem_a[4]
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to mem_a[1]
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to mem_a[7]
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to mem_a[2]
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "ghrd_system:ghrd_system_inst|ghrd_system_mem_if_ddr3_emif_0:mem_if_ddr3_emif_0|ghrd_system_mem_if_ddr3_emif_0_p0:p0|ghrd_system_mem_if_ddr3_emif_0_p0_memphy_m10:umemphy|ghrd_system_mem_if_ddr3_emif_0_p0_reset_m10:ureset|phy_reset_n"
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "ghrd_system:ghrd_system_inst|ghrd_system_mem_if_ddr3_emif_0:mem_if_ddr3_emif_0|ghrd_system_mem_if_ddr3_emif_0_p0:p0|ghrd_system_mem_if_ddr3_emif_0_p0_memphy_m10:umemphy|ghrd_system_mem_if_ddr3_emif_0_p0_read_datapath_m10:uread_datapath|rdata_per_dq_group[0].reset_n_fifo_wraddress[0]"
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL" -to mem_dqs[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dqs[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL" -to mem_dqs_n[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dqs_n[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dqs[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dqs_n[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[9] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[10] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[11] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[12] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[13] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[14] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[15] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[8] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[9] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[10] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[11] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[12] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[13] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[14] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[15] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[8] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[8] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[9] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[10] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[11] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[12] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[13] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[14] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[15] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[1] -to mem_dq[9] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[1] -to mem_dq[10] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[1] -to mem_dq[11] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[1] -to mem_dq[12] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[1] -to mem_dq[13] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[1] -to mem_dq[14] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[1] -to mem_dq[15] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[1] -to mem_dq[8] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[1] -to mem_dm[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dm[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dm[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name DM_PIN ON -to mem_dm[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dm[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to ghrd_system_inst|mem_if_ddr3_emif_0|p0|umemphy|ureset|phy_reset_n -tag __ghrd_system_mem_if_ddr3_emif_0_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to ghrd_system_inst|mem_if_ddr3_emif_0|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[0] -tag __ghrd_system_mem_if_ddr3_emif_0_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to ghrd_system_inst|mem_if_ddr3_emif_0|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[1] -tag __ghrd_system_mem_if_ddr3_emif_0_p0
set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to ghrd_system_inst|mem_if_ddr3_emif_0 -tag __ghrd_system_mem_if_ddr3_emif_0_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "dut_example_if0:if0|dut_example_if0_p0:p0|dut_example_if0_p0_ghrd_system_mem_if_ddr3_emif_0_p0_m10:umemphy|dut_example_if0_p0_dqdqs_pads_m10:dq_ddio[*].ubidir_dq_dqs|altera_gpio_lite:dq_ddio_io|altgpio_one_bit:gpio_one_bit.i_loop[*].altgpio_bit_i|fr_clock"
set_instance_assignment -name GLOBAL_SIGNAL OFF -to ghrd_10m50daf484c6ges_inst|mem_if_ddr3_emif_0|p0|umemphy|ureset|phy_reset_n -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to ghrd_10m50daf484c6ges_inst|mem_if_ddr3_emif_0|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to ghrd_10m50daf484c6ges_inst|mem_if_ddr3_emif_0|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to ghrd_10m50daf484c6ges_inst|mem_if_ddr3_emif_0 -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to "dut_example_if0:if0|dut_example_if0_p0:p0|dut_example_if0_p0_ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0_m10:umemphy|dut_example_if0_p0_dqdqs_pads_m10:dq_ddio[*].ubidir_dq_dqs|altera_gpio_lite:dq_ddio_io|altgpio_one_bit:gpio_one_bit.i_loop[*].altgpio_bit_i|fr_clock"
set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_location_assignment PIN_M9 -to clk_50
set_location_assignment PIN_D9 -to fpga_reset_n
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
set_global_assignment -name VERILOG_FILE ghrd_10m50da_top.v
set_global_assignment -name QIP_FILE ghrd_10m50da/synthesis/ghrd_10m50da.qip
set_global_assignment -name SDC_FILE ghrd_timing.sdc
set_location_assignment PIN_A10 -to i2c_scl
set_location_assignment PIN_B15 -to i2c_sda
set_location_assignment PIN_B7 -to spi_sclk
set_location_assignment PIN_A6 -to spi_miso
set_location_assignment PIN_C8 -to spi_mosi
set_location_assignment PIN_C7 -to spi_ssn
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to spi_miso
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to spi_mosi
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to spi_sclk
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to spi_ssn
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to fpga_reset_n
set_global_assignment -name USE_SIGNALTAP_FILE output_files/uart.stp
set_global_assignment -name SIGNALTAP_FILE output_files/uart.stp
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.qsys
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soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.sof
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soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.sopcinfo
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121
soc/altr/zephyr_nios2f/cpu/ghrd_10m50da_top.v
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module ghrd_10m50da_top (
//Clock and Reset
input wire clk_50,
//input wire clk_ddr3_100_p,
input wire fpga_reset_n,
//QSPI
output wire qspi_clk,
inout wire[3:0] qspi_io,
output wire qspi_csn,
//ddr3
//output wire [13:0] mem_a,
//output wire [2:0] mem_ba,
//inout wire [0:0] mem_ck,
//inout wire [0:0] mem_ck_n,
//output wire [0:0] mem_cke,
//output wire [0:0] mem_cs_n,
//output wire [0:0] mem_dm,
//output wire [0:0] mem_ras_n,
//output wire [0:0] mem_cas_n,
//output wire [0:0] mem_we_n,
//output wire mem_reset_n,
///inout wire [7:0] mem_dq,
//inout wire [0:0] mem_dqs,
//inout wire [0:0] mem_dqs_n,
//output wire [0:0] mem_odt,
//i2c
inout wire i2c_sda,
inout wire i2c_scl,
//spi
input wire spi_miso,
output wire spi_mosi,
output wire spi_sclk,
output wire spi_ssn,
//16550 UART
input wire uart_rx,
output wire uart_tx,
output wire [4:0] user_led
);
//Heart-beat counter
reg [25:0] heart_beat_cnt;
//DDR3 interface assignments
//wire local_init_done;
//wire local_cal_success;
//wire local_cal_fail;
//i2c interface
wire i2c_serial_sda_in ;
wire i2c_serial_scl_in ;
wire i2c_serial_sda_oe ;
wire i2c_serial_scl_oe ;
assign i2c_serial_scl_in = i2c_scl;
assign i2c_scl = i2c_serial_scl_oe ? 1'b0 : 1'bz;
assign i2c_serial_sda_in = i2c_sda;
assign i2c_sda = i2c_serial_sda_oe ? 1'b0 : 1'bz;
//assign system_resetn = fpga_reset_n & local_init_done;
// SoC sub-system module
ghrd_10m50da ghrd_10m50da_inst (
.clk_clk (clk_50),
//.ref_clock_bridge_in_clk_clk (clk_ddr3_100_p),
.reset_reset_n (fpga_reset_n),
//.mem_resetn_in_reset_reset_n (fpga_reset_n ), // mem_resetn_in_reset.reset_n
.ext_flash_qspi_pins_data (qspi_io),
.ext_flash_qspi_pins_dclk (qspi_clk),
.ext_flash_qspi_pins_ncs (qspi_csn),
//.memory_mem_a (mem_a[12:0] ), // memory.mem_a
//.memory_mem_ba (mem_ba ), // .mem_ba
//.memory_mem_ck (mem_ck ), // .mem_ck
//.memory_mem_ck_n (mem_ck_n ), // .mem_ck_n
//.memory_mem_cke (mem_cke ), // .mem_cke
//.memory_mem_cs_n (mem_cs_n ), // .mem_cs_n
//.memory_mem_dm (mem_dm ), // .mem_dm
//.memory_mem_ras_n (mem_ras_n ), // .mem_ras_n
//.memory_mem_cas_n (mem_cas_n ), // .mem_cas_n
//.memory_mem_we_n (mem_we_n ), // .mem_we_n
//.memory_mem_reset_n (mem_reset_n ), // .mem_reset_n
//.memory_mem_dq (mem_dq ), // .mem_dq
//.memory_mem_dqs (mem_dqs ), // .mem_dqs
//.memory_mem_dqs_n (mem_dqs_n ), // .mem_dqs_n
//.memory_mem_odt (mem_odt ), // .mem_odt
//.mem_if_ddr3_emif_0_status_local_init_done (local_init_done ), // mem_if_ddr3_emif_0_status.local_init_done
//.mem_if_ddr3_emif_0_status_local_cal_success (local_cal_success ), // .local_cal_success
//.mem_if_ddr3_emif_0_status_local_cal_fail (local_cal_fail ), // .local_cal_fail
//i2c
.i2c_0_i2c_serial_sda_in (i2c_serial_sda_in),
.i2c_0_i2c_serial_scl_in (i2c_serial_scl_in),
.i2c_0_i2c_serial_sda_oe (i2c_serial_sda_oe),
.i2c_0_i2c_serial_scl_oe (i2c_serial_scl_oe),
//spi
.spi_0_external_MISO (spi_miso), // spi_0_external.MISO
.spi_0_external_MOSI (spi_mosi), // .MOSI
.spi_0_external_SCLK (spi_sclk), // .SCLK
.spi_0_external_SS_n (spi_ssn), // .SS_n
//pio
.led_external_connection_export (user_led[3:0]),
//16550 UART
.a_16550_uart_0_rs_232_serial_sin (uart_rx), // a_16550_uart_0_rs_232_serial.sin
.a_16550_uart_0_rs_232_serial_sout (uart_tx), // .sout
.a_16550_uart_0_rs_232_serial_sout_oe () // .sout_oe
);
//DDR3 Address Bit #13 is not available for DDR3 SDRAM A (64Mx16)
//assign mem_a[13] = 1'b0;
//Heart beat by 50MHz clock
always @(posedge clk_50 or negedge fpga_reset_n)
if (!fpga_reset_n)
heart_beat_cnt <= 26'h0; //0x3FFFFFF
else
heart_beat_cnt <= heart_beat_cnt + 1'b1;
assign user_led[4] = heart_beat_cnt[25];
endmodule

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soc/altr/zephyr_nios2f/cpu/ghrd_timing.sdc
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#**************************************************************
# Create Clock
#**************************************************************
derive_pll_clocks
# JTAG Signal Constraints constrain the TCK port, assuming a 10MHz JTAG clock and 3ns delays
create_clock -name {altera_reserved_tck} -period 41.667 [get_ports { altera_reserved_tck }]
set_input_delay -clock altera_reserved_tck -clock_fall -max 5 [get_ports altera_reserved_tdi]
set_input_delay -clock altera_reserved_tck -clock_fall -max 5 [get_ports altera_reserved_tms]
set_output_delay -clock altera_reserved_tck 5 [get_ports altera_reserved_tdo]
create_clock -name {clk_50} -period 20.000 {clk_50}
set_false_path -to [get_ports {user_led[*]}]
set_false_path -to [get_ports {fpga_reset_n}]
set_false_path -from [get_ports {fpga_reset_n}]
derive_clock_uncertainty
# QSPI interface
set_output_delay -clock {clk_50 } -rise -min 11 [get_ports {qspi_io[*]}]
set_output_delay -clock {clk_50 } -rise -min 11 [get_ports {qspi_clk}]
set_output_delay -clock {clk_50 } -rise -min 11 [get_ports {qspi_csn}]
set_input_delay -clock {clk_50 } -rise -min 10 [get_ports {qspi_io[*]}]
# UART
set_false_path -from * -to [get_ports {uart_tx}]

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soc/altr/zephyr_nios2f/include/layout.h
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/*
* Copyright (c) 2016 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <system.h>
#define _RESET_VECTOR ALT_CPU_RESET_ADDR
#define _EXC_VECTOR ALT_CPU_EXCEPTION_ADDR

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soc/altr/zephyr_nios2f/include/linker.h
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/*
* linker.h - Linker script mapping information
*
* Machine generated for CPU 'nios2_gen2_0' in SOPC Builder design 'ghrd_10m50da'
* SOPC Builder design path: ../../ghrd_10m50da.sopcinfo
*
* Generated: Tue Dec 05 14:42:02 SGT 2017
*/
/*
* DO NOT MODIFY THIS FILE
*
* Changing this file will have subtle consequences
* which will almost certainly lead to a nonfunctioning
* system. If you do modify this file, be aware that your
* changes will be overwritten and lost when this file
* is generated again.
*
* DO NOT MODIFY THIS FILE
*/
/*
* License Agreement
*
* Copyright (c) 2008
* Altera Corporation, San Jose, California, USA.
* All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* This agreement shall be governed in all respects by the laws of the State
* of California and by the laws of the United States of America.
*/
#ifndef __LINKER_H_
#define __LINKER_H_
/*
* BSP controls alt_load() behavior in crt0.
*
*/
#define ALT_LOAD_EXPLICITLY_CONTROLLED
/*
* Base address and span (size in bytes) of each linker region
*
*/
#define EXT_FLASH_AVL_MEM_REGION_BASE 0x8000000
#define EXT_FLASH_AVL_MEM_REGION_SPAN 67108864
#define ONCHIP_FLASH_0_DATA_REGION_BASE 0x20
#define ONCHIP_FLASH_0_DATA_REGION_SPAN 753632
#define ONCHIP_MEMORY2_0_BEFORE_EXCEPTION_REGION_BASE 0x400000
#define ONCHIP_MEMORY2_0_BEFORE_EXCEPTION_REGION_SPAN 32
#define ONCHIP_MEMORY2_0_REGION_BASE 0x400020
#define ONCHIP_MEMORY2_0_REGION_SPAN 131040
#define RESET_REGION_BASE 0x0
#define RESET_REGION_SPAN 32
/*
* Devices associated with code sections
*
*/
#define ALT_EXCEPTIONS_DEVICE ONCHIP_MEMORY2_0
#define ALT_RESET_DEVICE ONCHIP_FLASH_0_DATA
#define ALT_RODATA_DEVICE ONCHIP_MEMORY2_0
#define ALT_RWDATA_DEVICE ONCHIP_MEMORY2_0
#define ALT_TEXT_DEVICE ONCHIP_FLASH_0_DATA
/*
* Initialization code at the reset address is allowed (e.g. no external bootloader).
*
*/
#define ALT_ALLOW_CODE_AT_RESET
/*
* The alt_load() facility is called from crt0 to copy sections into RAM.
*
*/
#define ALT_LOAD_COPY_EXCEPTIONS
#define ALT_LOAD_COPY_RODATA
#define ALT_LOAD_COPY_RWDATA
#endif /* __LINKER_H_ */

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soc/altr/zephyr_nios2f/include/system.h
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@ -1,567 +0,0 @@ @@ -1,567 +0,0 @@
/*
* system.h - SOPC Builder system and BSP software package information
*
* Machine generated for CPU 'nios2_gen2_0' in SOPC Builder design 'ghrd_10m50da'
* SOPC Builder design path: ../../ghrd_10m50da.sopcinfo
*
* Generated: Tue Dec 05 14:41:17 SGT 2017
*/
/*
* DO NOT MODIFY THIS FILE
*
* Changing this file will have subtle consequences
* which will almost certainly lead to a nonfunctioning
* system. If you do modify this file, be aware that your
* changes will be overwritten and lost when this file
* is generated again.
*
* DO NOT MODIFY THIS FILE
*/
/*
* License Agreement
*
* Copyright (c) 2008
* Altera Corporation, San Jose, California, USA.
* All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* This agreement shall be governed in all respects by the laws of the State
* of California and by the laws of the United States of America.
*/
#ifndef __SYSTEM_H_
#define __SYSTEM_H_
/* Include definitions from linker script generator */
#include "linker.h"
/*
* CPU configuration
*
*/
#define ALT_CPU_ARCHITECTURE "altera_nios2_gen2"
#define ALT_CPU_BIG_ENDIAN 0
#define ALT_CPU_BREAK_ADDR 0x00200820
#define ALT_CPU_CPU_ARCH_NIOS2_R1
#define ALT_CPU_CPU_FREQ 50000000u
#define ALT_CPU_CPU_ID_SIZE 1
#define ALT_CPU_CPU_ID_VALUE 0x00000000
#define ALT_CPU_CPU_IMPLEMENTATION "fast"
#define ALT_CPU_DATA_ADDR_WIDTH 0x1c
#define ALT_CPU_DCACHE_BYPASS_MASK 0x80000000
#define ALT_CPU_DCACHE_LINE_SIZE 32
#define ALT_CPU_DCACHE_LINE_SIZE_LOG2 5
#define ALT_CPU_DCACHE_SIZE 2048
#define ALT_CPU_EXCEPTION_ADDR 0x00400020
#define ALT_CPU_FLASH_ACCELERATOR_LINES 0
#define ALT_CPU_FLASH_ACCELERATOR_LINE_SIZE 0
#define ALT_CPU_FLUSHDA_SUPPORTED
#define ALT_CPU_FREQ 50000000
#define ALT_CPU_HARDWARE_DIVIDE_PRESENT 1
#define ALT_CPU_HARDWARE_MULTIPLY_PRESENT 1
#define ALT_CPU_HARDWARE_MULX_PRESENT 0
#define ALT_CPU_HAS_DEBUG_CORE 1
#define ALT_CPU_HAS_DEBUG_STUB
#define ALT_CPU_HAS_DIVISION_ERROR_EXCEPTION
#define ALT_CPU_HAS_EXTRA_EXCEPTION_INFO
#define ALT_CPU_HAS_ILLEGAL_INSTRUCTION_EXCEPTION
#define ALT_CPU_HAS_JMPI_INSTRUCTION
#define ALT_CPU_ICACHE_LINE_SIZE 32
#define ALT_CPU_ICACHE_LINE_SIZE_LOG2 5
#define ALT_CPU_ICACHE_SIZE 4096
#define ALT_CPU_INITDA_SUPPORTED
#define ALT_CPU_INST_ADDR_WIDTH 0x1c
#define ALT_CPU_NAME "nios2_gen2_0"
#define ALT_CPU_NUM_OF_SHADOW_REG_SETS 0
#define ALT_CPU_OCI_VERSION 1
#define ALT_CPU_RESET_ADDR 0x00000000
/*
* CPU configuration (with legacy prefix - don't use these anymore)
*
*/
#define NIOS2_BIG_ENDIAN 0
#define NIOS2_BREAK_ADDR 0x00200820
#define NIOS2_CPU_ARCH_NIOS2_R1
#define NIOS2_CPU_FREQ 50000000u
#define NIOS2_CPU_ID_SIZE 1
#define NIOS2_CPU_ID_VALUE 0x00000000
#define NIOS2_CPU_IMPLEMENTATION "fast"
#define NIOS2_DATA_ADDR_WIDTH 0x1c
#define NIOS2_DCACHE_BYPASS_MASK 0x80000000
#define NIOS2_DCACHE_LINE_SIZE 32
#define NIOS2_DCACHE_LINE_SIZE_LOG2 5
#define NIOS2_DCACHE_SIZE 2048
#define NIOS2_EXCEPTION_ADDR 0x00400020
#define NIOS2_FLASH_ACCELERATOR_LINES 0
#define NIOS2_FLASH_ACCELERATOR_LINE_SIZE 0
#define NIOS2_FLUSHDA_SUPPORTED
#define NIOS2_HARDWARE_DIVIDE_PRESENT 1
#define NIOS2_HARDWARE_MULTIPLY_PRESENT 1
#define NIOS2_HARDWARE_MULX_PRESENT 0
#define NIOS2_HAS_DEBUG_CORE 1
#define NIOS2_HAS_DEBUG_STUB
#define NIOS2_HAS_DIVISION_ERROR_EXCEPTION
#define NIOS2_HAS_EXTRA_EXCEPTION_INFO
#define NIOS2_HAS_ILLEGAL_INSTRUCTION_EXCEPTION
#define NIOS2_HAS_JMPI_INSTRUCTION
#define NIOS2_ICACHE_LINE_SIZE 32
#define NIOS2_ICACHE_LINE_SIZE_LOG2 5
#define NIOS2_ICACHE_SIZE 4096
#define NIOS2_INITDA_SUPPORTED
#define NIOS2_INST_ADDR_WIDTH 0x1c
#define NIOS2_NUM_OF_SHADOW_REG_SETS 0
#define NIOS2_OCI_VERSION 1
#define NIOS2_RESET_ADDR 0x00000000
/*
* Define for each module class mastered by the CPU
*
*/
#define __ALTERA_16550_UART
#define __ALTERA_AVALON_I2C
#define __ALTERA_AVALON_JTAG_UART
#define __ALTERA_AVALON_ONCHIP_MEMORY2
#define __ALTERA_AVALON_PIO
#define __ALTERA_AVALON_SPI
#define __ALTERA_AVALON_SYSID_QSYS
#define __ALTERA_AVALON_TIMER
#define __ALTERA_GENERIC_QUAD_SPI_CONTROLLER2
#define __ALTERA_MSGDMA
#define __ALTERA_NIOS2_GEN2
#define __ALTERA_ONCHIP_FLASH
/*
* System configuration
*
*/
#define ALT_DEVICE_FAMILY "MAX 10"
#define ALT_ENHANCED_INTERRUPT_API_PRESENT
#define ALT_IRQ_BASE NULL
#define ALT_LOG_PORT "/dev/null"
#define ALT_LOG_PORT_BASE 0x0
#define ALT_LOG_PORT_DEV null
#define ALT_LOG_PORT_TYPE ""
#define ALT_NUM_EXTERNAL_INTERRUPT_CONTROLLERS 0
#define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1
#define ALT_NUM_INTERRUPT_CONTROLLERS 1
#define ALT_STDERR "/dev/jtag_uart_0"
#define ALT_STDERR_BASE 0x201000
#define ALT_STDERR_DEV jtag_uart_0
#define ALT_STDERR_IS_JTAG_UART
#define ALT_STDERR_PRESENT
#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
#define ALT_STDIN "/dev/jtag_uart_0"
#define ALT_STDIN_BASE 0x201000
#define ALT_STDIN_DEV jtag_uart_0
#define ALT_STDIN_IS_JTAG_UART
#define ALT_STDIN_PRESENT
#define ALT_STDIN_TYPE "altera_avalon_jtag_uart"
#define ALT_STDOUT "/dev/jtag_uart_0"
#define ALT_STDOUT_BASE 0x201000
#define ALT_STDOUT_DEV jtag_uart_0
#define ALT_STDOUT_IS_JTAG_UART
#define ALT_STDOUT_PRESENT
#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart"
#define ALT_SYSTEM_NAME "ghrd_10m50da"
/*
* a_16550_uart_0 configuration
*
*/
#define ALT_MODULE_CLASS_a_16550_uart_0 altera_16550_uart
#define A_16550_UART_0_BASE 0x100000
#define A_16550_UART_0_FIFO_DEPTH 64
#define A_16550_UART_0_FIFO_MODE 1
#define A_16550_UART_0_FIO_HWFC 0
#define A_16550_UART_0_FIO_SWFC 0
#define A_16550_UART_0_FREQ 50000000
#define A_16550_UART_0_IRQ 1
#define A_16550_UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0
#define A_16550_UART_0_NAME "/dev/a_16550_uart_0"
#define A_16550_UART_0_SPAN 512
#define A_16550_UART_0_TYPE "altera_16550_uart"
/*
* ext_flash_avl_csr configuration
*
*/
#define ALT_MODULE_CLASS_ext_flash_avl_csr altera_generic_quad_spi_controller2
#define EXT_FLASH_AVL_CSR_BASE 0x100240
#define EXT_FLASH_AVL_CSR_FLASH_TYPE "Micron512"
#define EXT_FLASH_AVL_CSR_IRQ 6
#define EXT_FLASH_AVL_CSR_IRQ_INTERRUPT_CONTROLLER_ID 0
#define EXT_FLASH_AVL_CSR_IS_EPCS 0
#define EXT_FLASH_AVL_CSR_NAME "/dev/ext_flash_avl_csr"
#define EXT_FLASH_AVL_CSR_NUMBER_OF_SECTORS 1024
#define EXT_FLASH_AVL_CSR_PAGE_SIZE 256
#define EXT_FLASH_AVL_CSR_SECTOR_SIZE 65536
#define EXT_FLASH_AVL_CSR_SPAN 64
#define EXT_FLASH_AVL_CSR_SUBSECTOR_SIZE 4096
#define EXT_FLASH_AVL_CSR_TYPE "altera_generic_quad_spi_controller2"
/*
* ext_flash_avl_mem configuration
*
*/
#define ALT_MODULE_CLASS_ext_flash_avl_mem altera_generic_quad_spi_controller2
#define EXT_FLASH_AVL_MEM_BASE 0x8000000
#define EXT_FLASH_AVL_MEM_FLASH_TYPE "Micron512"
#define EXT_FLASH_AVL_MEM_IRQ -1
#define EXT_FLASH_AVL_MEM_IRQ_INTERRUPT_CONTROLLER_ID -1
#define EXT_FLASH_AVL_MEM_IS_EPCS 0
#define EXT_FLASH_AVL_MEM_NAME "/dev/ext_flash_avl_mem"
#define EXT_FLASH_AVL_MEM_NUMBER_OF_SECTORS 1024
#define EXT_FLASH_AVL_MEM_PAGE_SIZE 256
#define EXT_FLASH_AVL_MEM_SECTOR_SIZE 65536
#define EXT_FLASH_AVL_MEM_SPAN 67108864
#define EXT_FLASH_AVL_MEM_SUBSECTOR_SIZE 4096
#define EXT_FLASH_AVL_MEM_TYPE "altera_generic_quad_spi_controller2"
/*
* hal configuration
*
*/
#define ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API
#define ALT_MAX_FD 32
#define ALT_SYS_CLK TIMER_0
#define ALT_TIMESTAMP_CLK none
/*
* i2c_0 configuration
*
*/
#define ALT_MODULE_CLASS_i2c_0 altera_avalon_i2c
#define I2C_0_BASE 0x100200
#define I2C_0_FIFO_DEPTH 16
#define I2C_0_FREQ 50000000
#define I2C_0_IRQ 4
#define I2C_0_IRQ_INTERRUPT_CONTROLLER_ID 0
#define I2C_0_NAME "/dev/i2c_0"
#define I2C_0_SPAN 64
#define I2C_0_TYPE "altera_avalon_i2c"
#define I2C_0_USE_AV_ST 0
/*
* jtag_uart_0 configuration
*
*/
#define ALT_MODULE_CLASS_jtag_uart_0 altera_avalon_jtag_uart
#define JTAG_UART_0_BASE 0x201000
#define JTAG_UART_0_IRQ 0
#define JTAG_UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0
#define JTAG_UART_0_NAME "/dev/jtag_uart_0"
#define JTAG_UART_0_READ_DEPTH 64
#define JTAG_UART_0_READ_THRESHOLD 8
#define JTAG_UART_0_SPAN 8
#define JTAG_UART_0_TYPE "altera_avalon_jtag_uart"
#define JTAG_UART_0_WRITE_DEPTH 64
#define JTAG_UART_0_WRITE_THRESHOLD 8
/*
* led configuration
*
*/
#define ALT_MODULE_CLASS_led altera_avalon_pio
#define LED_BASE 0x1002e0
#define LED_BIT_CLEARING_EDGE_REGISTER 0
#define LED_BIT_MODIFYING_OUTPUT_REGISTER 0
#define LED_CAPTURE 0
#define LED_DATA_WIDTH 4
#define LED_DO_TEST_BENCH_WIRING 0
#define LED_DRIVEN_SIM_VALUE 0
#define LED_EDGE_TYPE "NONE"
#define LED_FREQ 50000000
#define LED_HAS_IN 0
#define LED_HAS_OUT 1
#define LED_HAS_TRI 0
#define LED_IRQ -1
#define LED_IRQ_INTERRUPT_CONTROLLER_ID -1
#define LED_IRQ_TYPE "NONE"
#define LED_NAME "/dev/led"
#define LED_RESET_VALUE 0
#define LED_SPAN 16
#define LED_TYPE "altera_avalon_pio"
/*
* msgdma_0_csr configuration
*
*/
#define ALT_MODULE_CLASS_msgdma_0_csr altera_msgdma
#define MSGDMA_0_CSR_BASE 0x1002c0
#define MSGDMA_0_CSR_BURST_ENABLE 1
#define MSGDMA_0_CSR_BURST_WRAPPING_SUPPORT 1
#define MSGDMA_0_CSR_CHANNEL_ENABLE 0
#define MSGDMA_0_CSR_CHANNEL_ENABLE_DERIVED 0
#define MSGDMA_0_CSR_CHANNEL_WIDTH 8
#define MSGDMA_0_CSR_DATA_FIFO_DEPTH 32
#define MSGDMA_0_CSR_DATA_WIDTH 32
#define MSGDMA_0_CSR_DESCRIPTOR_FIFO_DEPTH 128
#define MSGDMA_0_CSR_DMA_MODE 0
#define MSGDMA_0_CSR_ENHANCED_FEATURES 0
#define MSGDMA_0_CSR_ERROR_ENABLE 0
#define MSGDMA_0_CSR_ERROR_ENABLE_DERIVED 0
#define MSGDMA_0_CSR_ERROR_WIDTH 8
#define MSGDMA_0_CSR_IRQ 3
#define MSGDMA_0_CSR_IRQ_INTERRUPT_CONTROLLER_ID 0
#define MSGDMA_0_CSR_MAX_BURST_COUNT 2
#define MSGDMA_0_CSR_MAX_BYTE 1024
#define MSGDMA_0_CSR_MAX_STRIDE 1
#define MSGDMA_0_CSR_NAME "/dev/msgdma_0_csr"
#define MSGDMA_0_CSR_PACKET_ENABLE 0
#define MSGDMA_0_CSR_PACKET_ENABLE_DERIVED 0
#define MSGDMA_0_CSR_PREFETCHER_ENABLE 0
#define MSGDMA_0_CSR_PROGRAMMABLE_BURST_ENABLE 0
#define MSGDMA_0_CSR_RESPONSE_PORT 2
#define MSGDMA_0_CSR_SPAN 32
#define MSGDMA_0_CSR_STRIDE_ENABLE 0
#define MSGDMA_0_CSR_STRIDE_ENABLE_DERIVED 0
#define MSGDMA_0_CSR_TRANSFER_TYPE "Aligned Accesses"
#define MSGDMA_0_CSR_TYPE "altera_msgdma"
/*
* msgdma_0_descriptor_slave configuration
*
*/
#define ALT_MODULE_CLASS_msgdma_0_descriptor_slave altera_msgdma
#define MSGDMA_0_DESCRIPTOR_SLAVE_BASE 0x1002f0
#define MSGDMA_0_DESCRIPTOR_SLAVE_BURST_ENABLE 1
#define MSGDMA_0_DESCRIPTOR_SLAVE_BURST_WRAPPING_SUPPORT 1
#define MSGDMA_0_DESCRIPTOR_SLAVE_CHANNEL_ENABLE 0
#define MSGDMA_0_DESCRIPTOR_SLAVE_CHANNEL_ENABLE_DERIVED 0
#define MSGDMA_0_DESCRIPTOR_SLAVE_CHANNEL_WIDTH 8
#define MSGDMA_0_DESCRIPTOR_SLAVE_DATA_FIFO_DEPTH 32
#define MSGDMA_0_DESCRIPTOR_SLAVE_DATA_WIDTH 32
#define MSGDMA_0_DESCRIPTOR_SLAVE_DESCRIPTOR_FIFO_DEPTH 128
#define MSGDMA_0_DESCRIPTOR_SLAVE_DMA_MODE 0
#define MSGDMA_0_DESCRIPTOR_SLAVE_ENHANCED_FEATURES 0
#define MSGDMA_0_DESCRIPTOR_SLAVE_ERROR_ENABLE 0
#define MSGDMA_0_DESCRIPTOR_SLAVE_ERROR_ENABLE_DERIVED 0
#define MSGDMA_0_DESCRIPTOR_SLAVE_ERROR_WIDTH 8
#define MSGDMA_0_DESCRIPTOR_SLAVE_IRQ -1
#define MSGDMA_0_DESCRIPTOR_SLAVE_IRQ_INTERRUPT_CONTROLLER_ID -1
#define MSGDMA_0_DESCRIPTOR_SLAVE_MAX_BURST_COUNT 2
#define MSGDMA_0_DESCRIPTOR_SLAVE_MAX_BYTE 1024
#define MSGDMA_0_DESCRIPTOR_SLAVE_MAX_STRIDE 1
#define MSGDMA_0_DESCRIPTOR_SLAVE_NAME "/dev/msgdma_0_descriptor_slave"
#define MSGDMA_0_DESCRIPTOR_SLAVE_PACKET_ENABLE 0
#define MSGDMA_0_DESCRIPTOR_SLAVE_PACKET_ENABLE_DERIVED 0
#define MSGDMA_0_DESCRIPTOR_SLAVE_PREFETCHER_ENABLE 0
#define MSGDMA_0_DESCRIPTOR_SLAVE_PROGRAMMABLE_BURST_ENABLE 0
#define MSGDMA_0_DESCRIPTOR_SLAVE_RESPONSE_PORT 2
#define MSGDMA_0_DESCRIPTOR_SLAVE_SPAN 16
#define MSGDMA_0_DESCRIPTOR_SLAVE_STRIDE_ENABLE 0
#define MSGDMA_0_DESCRIPTOR_SLAVE_STRIDE_ENABLE_DERIVED 0
#define MSGDMA_0_DESCRIPTOR_SLAVE_TRANSFER_TYPE "Aligned Accesses"
#define MSGDMA_0_DESCRIPTOR_SLAVE_TYPE "altera_msgdma"
/*
* onchip_flash_0_csr configuration
*
*/
#define ALT_MODULE_CLASS_onchip_flash_0_csr altera_onchip_flash
#define ONCHIP_FLASH_0_CSR_BASE 0x200000
#define ONCHIP_FLASH_0_CSR_BYTES_PER_PAGE 8192
#define ONCHIP_FLASH_0_CSR_IRQ -1
#define ONCHIP_FLASH_0_CSR_IRQ_INTERRUPT_CONTROLLER_ID -1
#define ONCHIP_FLASH_0_CSR_NAME "/dev/onchip_flash_0_csr"
#define ONCHIP_FLASH_0_CSR_READ_ONLY_MODE 0
#define ONCHIP_FLASH_0_CSR_SECTOR1_ENABLED 1
#define ONCHIP_FLASH_0_CSR_SECTOR1_END_ADDR 0x7fff
#define ONCHIP_FLASH_0_CSR_SECTOR1_START_ADDR 0
#define ONCHIP_FLASH_0_CSR_SECTOR2_ENABLED 1
#define ONCHIP_FLASH_0_CSR_SECTOR2_END_ADDR 0xffff
#define ONCHIP_FLASH_0_CSR_SECTOR2_START_ADDR 0x8000
#define ONCHIP_FLASH_0_CSR_SECTOR3_ENABLED 1
#define ONCHIP_FLASH_0_CSR_SECTOR3_END_ADDR 0x6ffff
#define ONCHIP_FLASH_0_CSR_SECTOR3_START_ADDR 0x10000
#define ONCHIP_FLASH_0_CSR_SECTOR4_ENABLED 1
#define ONCHIP_FLASH_0_CSR_SECTOR4_END_ADDR 0xb7fff
#define ONCHIP_FLASH_0_CSR_SECTOR4_START_ADDR 0x70000
#define ONCHIP_FLASH_0_CSR_SECTOR5_ENABLED 0
#define ONCHIP_FLASH_0_CSR_SECTOR5_END_ADDR 0xffffffff
#define ONCHIP_FLASH_0_CSR_SECTOR5_START_ADDR 0xffffffff
#define ONCHIP_FLASH_0_CSR_SPAN 8
#define ONCHIP_FLASH_0_CSR_TYPE "altera_onchip_flash"
/*
* onchip_flash_0_data configuration
*
*/
#define ALT_MODULE_CLASS_onchip_flash_0_data altera_onchip_flash
#define ONCHIP_FLASH_0_DATA_BASE 0x0
#define ONCHIP_FLASH_0_DATA_BYTES_PER_PAGE 8192
#define ONCHIP_FLASH_0_DATA_IRQ -1
#define ONCHIP_FLASH_0_DATA_IRQ_INTERRUPT_CONTROLLER_ID -1
#define ONCHIP_FLASH_0_DATA_NAME "/dev/onchip_flash_0_data"
#define ONCHIP_FLASH_0_DATA_READ_ONLY_MODE 0
#define ONCHIP_FLASH_0_DATA_SECTOR1_ENABLED 1
#define ONCHIP_FLASH_0_DATA_SECTOR1_END_ADDR 0x7fff
#define ONCHIP_FLASH_0_DATA_SECTOR1_START_ADDR 0
#define ONCHIP_FLASH_0_DATA_SECTOR2_ENABLED 1
#define ONCHIP_FLASH_0_DATA_SECTOR2_END_ADDR 0xffff
#define ONCHIP_FLASH_0_DATA_SECTOR2_START_ADDR 0x8000
#define ONCHIP_FLASH_0_DATA_SECTOR3_ENABLED 1
#define ONCHIP_FLASH_0_DATA_SECTOR3_END_ADDR 0x6ffff
#define ONCHIP_FLASH_0_DATA_SECTOR3_START_ADDR 0x10000
#define ONCHIP_FLASH_0_DATA_SECTOR4_ENABLED 1
#define ONCHIP_FLASH_0_DATA_SECTOR4_END_ADDR 0xb7fff
#define ONCHIP_FLASH_0_DATA_SECTOR4_START_ADDR 0x70000
#define ONCHIP_FLASH_0_DATA_SECTOR5_ENABLED 0
#define ONCHIP_FLASH_0_DATA_SECTOR5_END_ADDR 0xffffffff
#define ONCHIP_FLASH_0_DATA_SECTOR5_START_ADDR 0xffffffff
#define ONCHIP_FLASH_0_DATA_SPAN 753664
#define ONCHIP_FLASH_0_DATA_TYPE "altera_onchip_flash"
/*
* onchip_memory2_0 configuration
*
*/
#define ALT_MODULE_CLASS_onchip_memory2_0 altera_avalon_onchip_memory2
#define ONCHIP_MEMORY2_0_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define ONCHIP_MEMORY2_0_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define ONCHIP_MEMORY2_0_BASE 0x400000
#define ONCHIP_MEMORY2_0_CONTENTS_INFO ""
#define ONCHIP_MEMORY2_0_DUAL_PORT 0
#define ONCHIP_MEMORY2_0_GUI_RAM_BLOCK_TYPE "AUTO"
#define ONCHIP_MEMORY2_0_INIT_CONTENTS_FILE "ghrd_10m50da_onchip_memory2_0"
#define ONCHIP_MEMORY2_0_INIT_MEM_CONTENT 0
#define ONCHIP_MEMORY2_0_INSTANCE_ID "NONE"
#define ONCHIP_MEMORY2_0_IRQ -1
#define ONCHIP_MEMORY2_0_IRQ_INTERRUPT_CONTROLLER_ID -1
#define ONCHIP_MEMORY2_0_NAME "/dev/onchip_memory2_0"
#define ONCHIP_MEMORY2_0_NON_DEFAULT_INIT_FILE_ENABLED 0
#define ONCHIP_MEMORY2_0_RAM_BLOCK_TYPE "AUTO"
#define ONCHIP_MEMORY2_0_READ_DURING_WRITE_MODE "DONT_CARE"
#define ONCHIP_MEMORY2_0_SINGLE_CLOCK_OP 0
#define ONCHIP_MEMORY2_0_SIZE_MULTIPLE 1
#define ONCHIP_MEMORY2_0_SIZE_VALUE 131072
#define ONCHIP_MEMORY2_0_SPAN 131072
#define ONCHIP_MEMORY2_0_TYPE "altera_avalon_onchip_memory2"
#define ONCHIP_MEMORY2_0_WRITABLE 1
/*
* spi_0 configuration
*
*/
#define ALT_MODULE_CLASS_spi_0 altera_avalon_spi
#define SPI_0_BASE 0x100280
#define SPI_0_CLOCKMULT 1
#define SPI_0_CLOCKPHASE 1
#define SPI_0_CLOCKPOLARITY 0
#define SPI_0_CLOCKUNITS "Hz"
#define SPI_0_DATABITS 8
#define SPI_0_DATAWIDTH 16
#define SPI_0_DELAYMULT "1.0E-9"
#define SPI_0_DELAYUNITS "ns"
#define SPI_0_EXTRADELAY 0
#define SPI_0_INSERT_SYNC 0
#define SPI_0_IRQ 5
#define SPI_0_IRQ_INTERRUPT_CONTROLLER_ID 0
#define SPI_0_ISMASTER 1
#define SPI_0_LSBFIRST 0
#define SPI_0_NAME "/dev/spi_0"
#define SPI_0_NUMSLAVES 1
#define SPI_0_PREFIX "spi_"
#define SPI_0_SPAN 32
#define SPI_0_SYNC_REG_DEPTH 2
#define SPI_0_TARGETCLOCK 128000u
#define SPI_0_TARGETSSDELAY "0.0"
#define SPI_0_TYPE "altera_avalon_spi"
/*
* sysid configuration
*
*/
#define ALT_MODULE_CLASS_sysid altera_avalon_sysid_qsys
#define SYSID_BASE 0x100300
#define SYSID_ID 0
#define SYSID_IRQ -1
#define SYSID_IRQ_INTERRUPT_CONTROLLER_ID -1
#define SYSID_NAME "/dev/sysid"
#define SYSID_SPAN 8
#define SYSID_TIMESTAMP 1512455752
#define SYSID_TYPE "altera_avalon_sysid_qsys"
/*
* timer_0 configuration
*
*/
#define ALT_MODULE_CLASS_timer_0 altera_avalon_timer
#define TIMER_0_ALWAYS_RUN 0
#define TIMER_0_BASE 0x1002a0
#define TIMER_0_COUNTER_SIZE 32
#define TIMER_0_FIXED_PERIOD 0
#define TIMER_0_FREQ 50000000
#define TIMER_0_IRQ 2
#define TIMER_0_IRQ_INTERRUPT_CONTROLLER_ID 0
#define TIMER_0_LOAD_VALUE 49999
#define TIMER_0_MULT 0.001
#define TIMER_0_NAME "/dev/timer_0"
#define TIMER_0_PERIOD 1
#define TIMER_0_PERIOD_UNITS "ms"
#define TIMER_0_RESET_OUTPUT 0
#define TIMER_0_SNAPSHOT 1
#define TIMER_0_SPAN 32
#define TIMER_0_TICKS_PER_SEC 1000
#define TIMER_0_TIMEOUT_PULSE_OUTPUT 0
#define TIMER_0_TYPE "altera_avalon_timer"
#endif /* __SYSTEM_H_ */

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soc/altr/zephyr_nios2f/linker.ld
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/*
* Copyright (c) 2016 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief Linker script for the Nios II/e CPU with timer and 16550 UART
*/
#include <layout.h>
#include <zephyr/devicetree.h>
#define _RAM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
#define _RAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
#define _ROM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_flash))
#define _ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))
#include <zephyr/arch/nios2/linker.ld>

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soc/altr/zephyr_nios2f/soc.h
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/*
* Copyright (c) 2016 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __SOC_H_
#define __SOC_H_
#include <system.h>
#endif

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soc/altr/zephyr_nios2f/soc.yml
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socs:
- name: zephyr_nios2f

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tests/boards/altera_max10/i2c_master/CMakeLists.txt
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# SPDX-License-Identifier: Apache-2.0
cmake_minimum_required(VERSION 3.20.0)
find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
project(i2c_master)
FILE(GLOB app_sources src/*.c)
target_sources(app PRIVATE ${app_sources})

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tests/boards/altera_max10/i2c_master/README.txt
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Build test for:
Altera Nios-II I2C master soft IP core.

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tests/boards/altera_max10/i2c_master/prj.conf
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CONFIG_I2C=y
CONFIG_I2C_INIT_PRIORITY=60
CONFIG_ZTEST=y

129
tests/boards/altera_max10/i2c_master/src/i2c_master.c
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/*
* Copyright (c) 2018 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/i2c.h>
#include <zephyr/kernel.h>
#include <zephyr/ztest.h>
/*
* For ADV7513 Programming details, please
* refer to the following link.
* https://ez.analog.com/docs/DOC-1986
*/
#define ADV7513_HDMI_I2C_SLAVE_ADDR 0x39
#define ADV7513_CHIP_REVISION_REG 0x0
#define CHIP_REVISION_VAL 0x13
#define ADV7513_MAIN_POWER_REG 0x41
#define POWER_ON_VAL 0x10
#define ADV7513_HPD_CTRL_REG 0xD6
#define HPD_CTRL_VAL 0xC0
#define ADV7513_WRITE_TEST_REG 0x2
#define WRITE_TEST_VAL 0x66
static int powerup_adv7513(const struct device *i2c_dev)
{
uint8_t data;
TC_PRINT("Powering up ADV7513\n");
/* write to HPD control registers */
if (i2c_reg_write_byte(i2c_dev, ADV7513_HDMI_I2C_SLAVE_ADDR,
ADV7513_HPD_CTRL_REG, HPD_CTRL_VAL)) {
TC_PRINT("i2c write fail\n");
return TC_FAIL;
}
if (i2c_reg_read_byte(i2c_dev, ADV7513_HDMI_I2C_SLAVE_ADDR,
0xD6, &data)) {
TC_PRINT("failed to read HPD control\n");
return TC_FAIL;
}
TC_PRINT("HPD control 0x%x\n", data);
/* write to power control registers */
if (i2c_reg_write_byte(i2c_dev, ADV7513_HDMI_I2C_SLAVE_ADDR,
ADV7513_MAIN_POWER_REG, POWER_ON_VAL)) {
TC_PRINT("i2c write fail\n");
return TC_FAIL;
}
if (i2c_reg_read_byte(i2c_dev, ADV7513_HDMI_I2C_SLAVE_ADDR,
0x41, &data)) {
TC_PRINT("failed to read Power state\n");
return TC_FAIL;
}
TC_PRINT("Power state 0x%x\n", data);
return TC_PASS;
}
static int test_i2c_adv7513(void)
{
const struct device *const i2c_dev = DEVICE_DT_GET_ONE(altr_nios2_i2c);
uint32_t i2c_cfg = I2C_SPEED_SET(I2C_SPEED_STANDARD) | I2C_MODE_CONTROLLER;
uint8_t data;
if (!device_is_ready(i2c_dev)) {
TC_PRINT("i2c device is not ready\n");
return TC_FAIL;
}
/* Test i2c_configure() */
if (i2c_configure(i2c_dev, i2c_cfg)) {
TC_PRINT("i2c config failed\n");
return TC_FAIL;
}
/* Power up ADV7513 */
zassert_true(powerup_adv7513(i2c_dev) == TC_PASS,
"ADV7513 power up failed");
TC_PRINT("*** Running i2c read/write tests ***\n");
/* Test i2c byte read */
data = 0x0;
if (i2c_reg_read_byte(i2c_dev, ADV7513_HDMI_I2C_SLAVE_ADDR,
ADV7513_CHIP_REVISION_REG, &data)) {
TC_PRINT("failed to read chip revision\n");
return TC_FAIL;
}
if (data != CHIP_REVISION_VAL) {
TC_PRINT("chip revision does not match 0x%x\n", data);
return TC_FAIL;
}
TC_PRINT("i2c read test passed\n");
/* Test i2c byte write */
data = WRITE_TEST_VAL;
if (i2c_reg_write_byte(i2c_dev, ADV7513_HDMI_I2C_SLAVE_ADDR,
ADV7513_WRITE_TEST_REG, data)) {
TC_PRINT("i2c write fail\n");
return TC_FAIL;
}
data = 0x0;
if (i2c_reg_read_byte(i2c_dev, ADV7513_HDMI_I2C_SLAVE_ADDR,
ADV7513_WRITE_TEST_REG, &data)) {
TC_PRINT("i2c read fail\n");
return TC_FAIL;
}
if (data != WRITE_TEST_VAL) {
TC_PRINT("i2c write test failed 0x%x\n", data);
return TC_FAIL;
}
TC_PRINT("i2c write & verify test passed\n");
return TC_PASS;
}
ZTEST(nios2_i2c_master, test_i2c_master)
{
zassert_true(test_i2c_adv7513() == TC_PASS);
}
ZTEST_SUITE(nios2_i2c_master, NULL, NULL, NULL, NULL, NULL);

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tests/boards/altera_max10/i2c_master/testcase.yaml
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tests:
boards.altera_max10.i2c_master:
platform_allow: altera_max10
tags: i2c

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tests/boards/altera_max10/msgdma/CMakeLists.txt
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# SPDX-License-Identifier: Apache-2.0
cmake_minimum_required(VERSION 3.20.0)
find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
project(msgdma)
FILE(GLOB app_sources src/*.c)
target_sources(app PRIVATE ${app_sources})
target_include_directories(app PRIVATE
${ZEPHYR_BASE}/kernel/include
${ZEPHYR_BASE}/arch/${ARCH}/include
)

2
tests/boards/altera_max10/msgdma/README.txt
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Build test for:
Altera Nios-II Modular Scatter Gather DMA (MSGDMA) soft IP core.

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tests/boards/altera_max10/msgdma/prj.conf
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CONFIG_DMA=y
CONFIG_ZTEST=y

101
tests/boards/altera_max10/msgdma/src/dma.c
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/*
* Copyright (c) 2018 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/ztest.h>
#include <soc.h>
#include <kernel_arch_func.h>
#include <zephyr/device.h>
#include <zephyr/drivers/dma.h>
#define DMA_BUFF_SIZE 1024
enum dma_op_status {
DMA_OP_STAT_NONE = 0,
DMA_OP_STAT_ERR,
DMA_OP_STAT_SUCCESS,
};
static enum dma_op_status dma_stat;
static char tx_data[DMA_BUFF_SIZE];
static char rx_data[DMA_BUFF_SIZE];
static struct dma_config dma_cfg = {0};
static struct dma_block_config dma_block_cfg = {0};
static void dma_user_callback(const struct device *dma_dev, void *arg,
uint32_t id, int status)
{
if (status >= 0) {
TC_PRINT("DMA completed successfully\n");
dma_stat = DMA_OP_STAT_SUCCESS;
} else {
TC_PRINT("DMA error occurred!! (%d)\n", status);
dma_stat = DMA_OP_STAT_ERR;
}
}
ZTEST(nios2_msgdma, test_msgdma)
{
const struct device *dma;
static uint32_t chan_id;
int i;
dma = DEVICE_DT_GET(DT_NODELABEL(dma));
__ASSERT_NO_MSG(device_is_ready(dma));
/* Init tx buffer */
for (i = 0; i < DMA_BUFF_SIZE; i++) {
tx_data[i] = i;
}
/* Init DMA config info */
dma_cfg.channel_direction = MEMORY_TO_MEMORY;
dma_cfg.source_data_size = 1U;
dma_cfg.dest_data_size = 1U;
dma_cfg.source_burst_length = 1U;
dma_cfg.dest_burst_length = 1U;
dma_cfg.dma_callback = dma_user_callback;
dma_cfg.block_count = 1U;
dma_cfg.head_block = &dma_block_cfg;
/*
* Set channel id to 0 as Nios-II
* MSGDMA only supports one channel
*/
chan_id = 0U;
/* Init DMA descriptor info */
dma_block_cfg.block_size = DMA_BUFF_SIZE;
dma_block_cfg.source_address = (uint32_t)tx_data;
dma_block_cfg.dest_address = (uint32_t)rx_data;
/* Configure DMA */
zassert_true(dma_config(dma, chan_id, &dma_cfg) == 0,
"DMA config error");
/* Make sure all the data is written out to memory */
z_nios2_dcache_flush_all();
/* Start DMA operation */
zassert_true(dma_start(dma, chan_id) == 0, "DMA start error");
while (dma_stat == DMA_OP_STAT_NONE) {
k_busy_wait(10);
}
/* Invalidate the data cache */
z_nios2_dcache_flush_no_writeback(rx_data, DMA_BUFF_SIZE);
zassert_true(dma_stat == DMA_OP_STAT_SUCCESS,
"Nios-II DMA operation failed!!");
zassert_true(!memcmp(&tx_data, &rx_data, DMA_BUFF_SIZE),
"Nios-II DMA Test failed!!");
}
ZTEST_SUITE(nios2_msgdma, NULL, NULL, NULL, NULL, NULL);

4
tests/boards/altera_max10/msgdma/testcase.yaml
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tests:
boards.altera_max10.dma:
platform_allow: altera_max10
tags: dma

8
tests/boards/altera_max10/qspi/CMakeLists.txt
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# SPDX-License-Identifier: Apache-2.0
cmake_minimum_required(VERSION 3.20.0)
find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
project(qspi)
FILE(GLOB app_sources src/*.c)
target_sources(app PRIVATE ${app_sources})

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tests/boards/altera_max10/qspi/README.txt
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Build test for:
Altera Nios-II QSPI flash soft IP core.

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tests/boards/altera_max10/qspi/prj.conf
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CONFIG_STDOUT_CONSOLE=y
CONFIG_FLASH=y
CONFIG_SOC_FLASH_NIOS2_QSPI=y
CONFIG_ZTEST=y

74
tests/boards/altera_max10/qspi/src/qspi_flash.c
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/*
* Copyright (c) 2018 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/drivers/flash.h>
#include <zephyr/device.h>
#include <zephyr/ztest.h>
#define MAX_NUM_OF_SECTORS 1024
#define NUM_OF_SECTORS_TO_TEST 4
#define FLASH_SECTOR_SIZE 65536
#define TEST_DATA_LEN 4
ZTEST(nios2_qspi, test_qspi_flash)
{
const struct device *flash_dev;
uint32_t i, offset, rd_val, wr_val;
uint8_t wr_buf[4] = {0xAA, 0xBB, 0xCC, 0xDD};
uint8_t rd_buf[2];
flash_dev = DEVICE_DT_GET(DT_NODELABEL(n25q512ax3));
zassert_true(!device_is_ready(flash_dev), TC_PASS, "Flash device is not ready!");
for (i = 0U; i < NUM_OF_SECTORS_TO_TEST; i++) {
TC_PRINT("\nTesting: Flash Sector-%d\n", i);
offset = FLASH_SECTOR_SIZE * i;
/* Flash Erase Test */
TC_PRINT(" Flash Erase Test...");
zassert_equal(flash_erase(flash_dev,
offset, FLASH_SECTOR_SIZE),
TC_PASS, "Flash erase call failed!");
zassert_equal(flash_read(flash_dev, offset,
&rd_val, TEST_DATA_LEN),
TC_PASS, "Flash read call failed!");
/* In case of erase all bits will be set to 1 */
wr_val = 0xffffffff;
zassert_equal(rd_val != wr_val, TC_PASS,
"Flash Erase Test failed!!");
TC_PRINT("PASS\n");
/* Flash Write & Read Test */
TC_PRINT(" Flash Write & Read Test...");
wr_val = 0xAABBCCDD;
zassert_equal(flash_write(flash_dev, offset,
&wr_val, TEST_DATA_LEN),
TC_PASS, "Flash write call failed!");
zassert_equal(flash_read(flash_dev, offset,
&rd_val, TEST_DATA_LEN),
TC_PASS, "Flash read call failed!");
zassert_equal(rd_val != wr_val, TC_PASS,
"Flash Write & Read Test failed!!");
TC_PRINT("PASS\n");
/* Flash Unaligned Read Test */
TC_PRINT(" Flash Unaligned Read Test...");
zassert_equal(flash_write(flash_dev, offset + sizeof(wr_val),
&wr_buf, sizeof(wr_buf)),
TC_PASS, "Flash write call failed!");
zassert_equal(flash_read(flash_dev, offset + sizeof(wr_val) + 1,
&rd_buf, sizeof(rd_buf)),
TC_PASS, "Flash read call failed!");
zassert_equal(memcmp(wr_buf + 1, rd_buf, sizeof(rd_buf)),
TC_PASS, "Flash Write & Read Test failed!!");
TC_PRINT("PASS\n");
}
}
ZTEST_SUITE(nios2_qspi, NULL, NULL, NULL, NULL, NULL);

6
tests/boards/altera_max10/qspi/testcase.yaml
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tests:
boards.altera_max10.qspi:
platform_allow: altera_max10
tags:
- qspi
- flash

8
tests/boards/altera_max10/sysid/CMakeLists.txt
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# SPDX-License-Identifier: Apache-2.0
cmake_minimum_required(VERSION 3.20.0)
find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
project(sysid)
FILE(GLOB app_sources src/*.c)
target_sources(app PRIVATE ${app_sources})

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tests/boards/altera_max10/sysid/README.txt
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Build test for:
Altera Nios-II System ID soft IP core.

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tests/boards/altera_max10/sysid/prj.conf
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CONFIG_ZTEST=y

29
tests/boards/altera_max10/sysid/src/sysid.c
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/*
* Copyright (c) 2017 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/ztest.h>
#include "altera_avalon_sysid.h"
ZTEST(nios2_sysid, test_sysid)
{
int32_t sysid, status = TC_FAIL;
sysid = alt_avalon_sysid_test();
if (!sysid) {
status = TC_PASS;
TC_PRINT("[SysID] hardware and software appear to be in sync\n");
} else if (sysid > 0) {
TC_PRINT("[SysID] software appears to be older than hardware\n");
} else {
TC_PRINT("[SysID] hardware appears to be older than software\n");
}
zassert_equal(status, TC_PASS, "SysID test failed");
}
ZTEST_SUITE(nios2_sysid, NULL, NULL, NULL, NULL, NULL);

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tests/boards/altera_max10/sysid/testcase.yaml
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tests:
boards.altera_max10.sysid:
platform_allow: altera_max10
tags: sysid
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