diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index c77180172d2..dec2d0a2f25 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -3163,18 +3163,9 @@ NIOS-2 arch: - nashif files: - arch/nios2/ - - dts/nios2/intel/ - - boards/common/nios2.board.cmake - - soc/altr/*nios2*/ - include/zephyr/arch/nios2/ - - tests/boards/altera_max10/ - - boards/qemu/nios2/ - - boards/altr/max10/ - - scripts/support/quartus-flash.py labels: - "area: NIOS2" - tests: - - boards.altera_max10 nRF BSIM: status: maintained diff --git a/boards/altr/index.rst b/boards/altr/index.rst deleted file mode 100644 index 83220f8c905..00000000000 --- a/boards/altr/index.rst +++ /dev/null @@ -1,10 +0,0 @@ -.. _boards-altera: - -Altera Corporation -################## - -.. toctree:: - :maxdepth: 1 - :glob: - - **/* diff --git a/boards/altr/max10/Kconfig.altera_max10 b/boards/altr/max10/Kconfig.altera_max10 deleted file mode 100644 index b0b39da8448..00000000000 --- a/boards/altr/max10/Kconfig.altera_max10 +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# Copyright (c) 2018 Intel - -config BOARD_ALTERA_MAX10 - select SOC_ZEPHYR_NIOS2F diff --git a/boards/altr/max10/Kconfig.defconfig b/boards/altr/max10/Kconfig.defconfig deleted file mode 100644 index d0617d44c33..00000000000 --- a/boards/altr/max10/Kconfig.defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# Copyright (c) 2018 Intel - -if BOARD_ALTERA_MAX10 - -if FLASH - -config SOC_FLASH_NIOS2_QSPI - default y - -endif # FLASH - -endif # BOARD_ALTERA_MAX10 diff --git a/boards/altr/max10/altera_max10.dts b/boards/altr/max10/altera_max10.dts deleted file mode 100644 index 30c7e442505..00000000000 --- a/boards/altr/max10/altera_max10.dts +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 */ -/* Copyright (c) 2018 Intel */ - -/dts-v1/; - -#include -#include - -/ { - model = "altera_max10"; - compatible = "altr,nios2-max10"; - - aliases { - uart-0 = &uart0; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - }; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; -}; - -&i2c0 { - status = "okay"; - clock-frequency = ; -}; - -&qspi { - status = "okay"; - n25q512ax3: n25q512ax3@0 { - compatible = "altr,nios2-qspi-nor"; - size = ; /* in bits */ - reg = <0>; - }; -}; diff --git a/boards/altr/max10/altera_max10.yaml b/boards/altr/max10/altera_max10.yaml deleted file mode 100644 index eb068f21f47..00000000000 --- a/boards/altr/max10/altera_max10.yaml +++ /dev/null @@ -1,7 +0,0 @@ -identifier: altera_max10 -name: Altera MAX10 -type: mcu -arch: nios2 -toolchain: - - zephyr -vendor: altr diff --git a/boards/altr/max10/altera_max10_defconfig b/boards/altr/max10/altera_max10_defconfig deleted file mode 100644 index ac9a2e96e4d..00000000000 --- a/boards/altr/max10/altera_max10_defconfig +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# Copyright (c) 2018 Intel - -CONFIG_HAS_ALTERA_HAL=y -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y diff --git a/boards/altr/max10/board.cmake b/boards/altr/max10/board.cmake deleted file mode 100644 index 9e7a8dd873d..00000000000 --- a/boards/altr/max10/board.cmake +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(nios2 "--cpu-sof=${ZEPHYR_BASE}/soc/nios2/nios2f-zephyr/cpu/ghrd_10m50da.sof") -include(${ZEPHYR_BASE}/boards/common/nios2.board.cmake) diff --git a/boards/altr/max10/board.yml b/boards/altr/max10/board.yml deleted file mode 100644 index 9106b7e15ec..00000000000 --- a/boards/altr/max10/board.yml +++ /dev/null @@ -1,6 +0,0 @@ -board: - name: altera_max10 - full_name: MAX10 - vendor: altr - socs: - - name: zephyr_nios2f diff --git a/boards/altr/max10/doc/img/Altera_MAX10_switches.jpg b/boards/altr/max10/doc/img/Altera_MAX10_switches.jpg deleted file mode 100644 index 5c71d7bf80d..00000000000 Binary files a/boards/altr/max10/doc/img/Altera_MAX10_switches.jpg and /dev/null differ diff --git a/boards/altr/max10/doc/img/altera_max10.jpg b/boards/altr/max10/doc/img/altera_max10.jpg deleted file mode 100644 index 51d5424c2f8..00000000000 Binary files a/boards/altr/max10/doc/img/altera_max10.jpg and /dev/null differ diff --git a/boards/altr/max10/doc/index.rst b/boards/altr/max10/doc/index.rst deleted file mode 100644 index 1e5064b0f0d..00000000000 --- a/boards/altr/max10/doc/index.rst +++ /dev/null @@ -1,324 +0,0 @@ -.. zephyr:board:: altera_max10 - -Overview -******** - -The Zephyr kernel is supported on the Altera MAX10 Rev C development kit, using -the Nios II Gen 2 soft CPU. - -Hardware -******** - -DIP Switch settings -=================== - -There are two sets of switches on the back of the board. Of particular -importance is SW2: - -* Switch 2 (CONFIG_SEL) should be in the OFF (up) position so that the first - boot image is CFM0 -* Switch 3 (VTAP_BYPASS) needs to be in the ON (down) position or the flashing - scripts won't work -* Switch 4 (HSMC_BYPASSN) should be OFF (up) - -.. image:: img/Altera_MAX10_switches.jpg - :align: center - :alt: Altera's MAX* 10 Switches - -Other switches are user switches, their position is application-specific. - -Necessary Software -================== - -You will need the Altera Quartus SDK in order to work with this device. The -`Altera Lite Distribution`_ of Quartus may be obtained without -charge. - -For your convenience using the SDK tools (such as ``nios2-configure-sof``), -you should put the binaries provided by the SDK -in your path. Below is an example, adjust ALTERA_BASE to where you installed the -SDK: - -.. code-block:: console - - export ALTERA_BASE=/opt/altera_lite/16.0 - export PATH=$PATH:$ALTERA_BASE/quartus/bin:$ALTERA_BASE/nios2eds/bin - -You may need to adjust your udev rules so that you can talk to the USB Blaster -II peripheral, which is the built-in JTAG interface for this device. - -The following works for Fedora 23: - -.. code-block:: console - - # For Altera USB-Blaster permissions. - SUBSYSTEM=="usb",\ - ENV{DEVTYPE}=="usb_device",\ - ATTR{idVendor}=="09fb",\ - ATTR{idProduct}=="6010",\ - MODE="0666",\ - NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}",\ - RUN+="/bin/chmod 0666 %c" - SUBSYSTEM=="usb",\ - ENV{DEVTYPE}=="usb_device",\ - ATTR{idVendor}=="09fb",\ - ATTR{idProduct}=="6810",\ - MODE="0666",\ - NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}",\ - RUN+="/bin/chmod 0666 %c" - -You can test connectivity with the SDK jtagconfig tool, you should see something -like: - -.. code-block:: console - - $ jtagconfig - 1) USB-BlasterII [1-1.2] - 031050DD 10M50DA(.|ES)/10M50DC - 020D10DD VTAP10 - - -Reference CPU -============= - -A reference CPU design of a Nios II/f core is included in the Zephyr tree -in the :zephyr_file:`soc/altr/zephyr_nios2f/cpu` directory. - -Flash this CPU using the ``nios2-configure-sof`` SDK tool with the FPGA -configuration file -:zephyr_file:`soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.sof`: - -.. code-block:: console - - $ nios2-configure-sof ghrd_10m50da.sof - -This CPU is a Nios II/F core with a 16550 UART, JTAG UART, and the Avalon Timer. -For any Nios II SOC definition, you can find out more details about the CPU -configuration by inspecting system.h in the SOC's include directory. - -Console Output -============== - -16550 UART ----------- - -By default, the kernel is configured to send console output to the 16550 UART. -You can monitor this on your workstation by connecting to the top right mini USB -port on the board (it will show up in /dev as a ttyUSB node), and then running -minicom with flow control disabled, 115200-8N1 settings. - -JTAG UART ---------- - -You can also have it send its console output to the JTAG UART. -Enable ``jtag_uart`` node in :file:`altera_max10.dts` or overlay file: - -.. code-block:: devicetree - - &jtag_uart { - status = "okay"; - current-speed = <115200>; - }; - -To view these messages on your local workstation, run the terminal application -in the SDK: - -.. code-block:: console - - $ nios2-terminal - -Programming and Debugging -************************* - -.. zephyr:board-supported-runners:: - -Flashing -======== - -Flashing Kernel into UFM ------------------------- - -The usual ``flash`` target will work with the ``altera_max10`` board -configuration. Here is an example for the :zephyr:code-sample:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: altera_max10 - :goals: flash - -Refer to :ref:`build_an_application` and :ref:`application_run` for -more details. - -This provisions the Zephyr kernel and the CPU configuration onto the board, -using the scripts/support/quartus-flash.py script. After it completes the kernel -will immediately boot. - - -Flashing Kernel directly into RAM over JTAG -------------------------------------------- - -The SDK included the nios2-download tool which will let you flash a kernel -directly into RAM and then boot it from the __start symbol. - -In order for this to work, your entire kernel must be located in RAM. Make sure -the following config options are disabled: - -.. code-block:: cfg - - CONFIG_XIP=n - CONFIG_INCLUDE_RESET_VECTOR=n - -Then, after building your kernel, push it into device's RAM by running -this from the build directory: - -.. code-block:: console - - $ nios2-download --go zephyr/zephyr.elf - -If you have a console session running (either minicom or nios2-terminal) you -should see the application's output. There are additional arguments you can pass -to nios2-download so that it spawns a GDB server that you can connect to, -although it's typically simpler to just use nios2-gdb-server as described below. - -Debugging -========= - -The Altera SDK includes a GDB server which can be used to debug a MAX10 board. -You can either debug a running image that was flashed onto the device in User -Flash Memory (UFM), or load an image over the JTAG using GDB. - -Debugging With UFM Flashed Image --------------------------------- - -You can debug an application in the usual way. Here is an example. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: altera_max10 - :goals: debug - -You will see output similar to the following: - -.. code-block:: console - - Nios II GDB server running on port 3335 - Ignoring --stop option because --tcpport also specified - GNU gdb (GDB) 7.11.0.20160511-git - Copyright (C) 2016 Free Software Foundation, Inc. - License GPLv3+: GNU GPL version 3 or later - This is free software: you are free to change and redistribute it. - There is NO WARRANTY, to the extent permitted by law. Type "show copying" - and "show warranty" for details. - This GDB was configured as "--host=x86_64-pokysdk-linux --target=nios2-zephyr-elf". - Type "show configuration" for configuration details. - For bug reporting instructions, please see: - . - Find the GDB manual and other documentation resources online at: - . - For help, type "help". - Type "apropos word" to search for commands related to "word"... - Reading symbols from /projects/zephyr/samples/hello_world/build/zephyr/zephyr.elf...done. - Remote debugging using :3335 - Using cable "USB-BlasterII [3-1.3]", device 1, instance 0x00 - Resetting and pausing target processor: OK - Listening on port 3335 for connection from GDB: accepted - isr_tables_syms () at /projects/zephyr/arch/common/isr_tables.c:63 - 63 GEN_ABSOLUTE_SYM(__ISR_LIST_SIZEOF, sizeof(struct _isr_list)); - (gdb) b z_prep_c - Breakpoint 1 at 0xdf0: file /projects/zephyr/arch/nios2/core/prep_c.c, line 36. - (gdb) b z_cstart - Breakpoint 2 at 0x1254: file /projects/zephyr/kernel/init.c, line 348. - (gdb) c - Continuing. - - Breakpoint 2, z_cstart () at /projects/zephyr/kernel/init.c:348 - 348 { - (gdb) - -To start debugging manually: - - -.. code-block:: console - - nios2-gdb-server --tcpport 1234 --stop --reset-target - -And then connect with GDB from the build directory: - - -.. code-block:: console - - nios2-poky-elf-gdb zephyr/zephyr.elf -ex "target remote :1234" - -Debugging With JTAG Flashed Image ---------------------------------- - -In order for this to work, execute-in-place must be disabled, since the GDB -'load' command can only put text and data in RAM. Ensure this is in your -configuration: - -.. code-block:: cfg - - CONFIG_XIP=n - -It is OK for this procedure to leave the reset vector enabled, unlike -nios2-download (which errors out if it finds sections outside of SRAM) it will -be ignored. - -In a terminal, launch the nios2 GDB server. It doesn't matter what kernel (if -any) is on the device, but you should have at least flashed a CPU using -nios2-configure-sof. You can leave this process running. - -.. code-block:: console - - $ nios2-gdb-server --tcpport 1234 --tcppersist --init-cache --reset-target - -Build your Zephyr kernel, and load it into a GDB built for Nios II (included in -the Zephyr SDK) from the build directory: - -.. code-block:: console - - $ nios2-poky-elf-gdb zephyr/zephyr.elf - -Then connect to the GDB server: - -.. code-block:: console - - (gdb) target remote :1234 - -And then load the kernel image over the wire. The CPU will not start from the -reset vector, instead it will boot from the __start symbol: - - -.. code-block:: console - - (gdb) load - Loading section reset, size 0xc lma 0x0 - Loading section exceptions, size 0x1b0 lma 0x400020 - Loading section text, size 0x8df0 lma 0x4001d0 - Loading section devconfig, size 0x30 lma 0x408fc0 - Loading section rodata, size 0x3f4 lma 0x408ff0 - Loading section datas, size 0x888 lma 0x4093e4 - Loading section initlevel, size 0x30 lma 0x409c6c - Loading section _k_task_list, size 0x58 lma 0x409c9c - Loading section _k_task_ptr, size 0x8 lma 0x409cf4 - Loading section _k_event_list, size 0x10 lma 0x409cfc - Start address 0x408f54, load size 40184 - Transfer rate: 417 KB/sec, 368 bytes/write. - After this is done you may set breakpoints and continue execution. If you ever want to reset the CPU, issue the 'load' command again. - - - -References -********** - -* `CPU Documentation `_ -* `Nios II Processor Booting Methods in MAX 10 FPGA Devices `_ -* `Embedded Peripherals IP User Guide `_ -* `MAX 10 FPGA Configuration User Guide `_ -* `MAX 10 FPGA Development Kit User Guide `_ -* `Nios II Command-Line Tools `_ -* `Quartus II Scripting Reference Manual `_ - - -.. _Altera Lite Distribution: https://www.intel.com/content/www/us/en/collections/products/fpga/software/downloads.html diff --git a/boards/common/nios2.board.cmake b/boards/common/nios2.board.cmake deleted file mode 100644 index 4a59927171b..00000000000 --- a/boards/common/nios2.board.cmake +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_set_flasher_ifnset(nios2) -board_set_debugger_ifnset(nios2) - -board_finalize_runner_args(nios2 - # TODO: merge this script into nios2.py - "--quartus-flash=${ZEPHYR_BASE}/scripts/support/quartus-flash.py" - ) diff --git a/scripts/footprint/plan.txt b/scripts/footprint/plan.txt index a28cb93f142..7ad9a4fb788 100644 --- a/scripts/footprint/plan.txt +++ b/scripts/footprint/plan.txt @@ -4,7 +4,6 @@ footprints,default,disco_l475_iot1,tests/benchmarks/footprints,,benchmark.kernel footprints,userspace,disco_l475_iot1,tests/benchmarks/footprints,-DCONF_FILE=prj_userspace.conf,benchmark.kernel.footprints.userspace footprints,default,nrf5340dk/nrf5340/cpuapp,tests/benchmarks/footprints,,benchmark.kernel.footprints.default footprints,default,nrf51dk/nrf51822,tests/benchmarks/footprints,,benchmark.kernel.footprints.default -footprints,default,altera_max10,tests/benchmarks/footprints,,benchmark.kernel.footprints.default footprints,default,hifive1@B,tests/benchmarks/footprints,,benchmark.kernel.footprints.default footprints,default,intel_ehl_crb,tests/benchmarks/footprints,,benchmark.kernel.footprints.default footprints,userspace,intel_ehl_crb,tests/benchmarks/footprints,-DCONF_FILE=prj_userspace.conf,benchmark.kernel.footprints.userspace diff --git a/scripts/support/quartus-flash.py b/scripts/support/quartus-flash.py deleted file mode 100755 index fab6622c21c..00000000000 --- a/scripts/support/quartus-flash.py +++ /dev/null @@ -1,137 +0,0 @@ -#!/usr/bin/env python3 - -# SPDX-License-Identifier: Apache-2.0 -import subprocess -import tempfile -import argparse -import os -import string -import sys - -quartus_cpf_template = """ - - ${OUTPUT_FILENAME} - 1 - 1 - 14 - - Page_0 - 1 - - ${SOF_FILENAME}1 - - - 10 - 0 - 0 - 0 - 1 - - 1 - - - 0 - 1 - 0 - 0 - 0 - 0 - 2 - ${KERNEL_FILENAME} - - - 2 - 2 - 0 - -1 - -1 - 1 - - -""" - -# XXX Do we care about FileRevision, DefaultMfr, PartName? Do they need -# to be parameters? So far seems to work across 2 different boards, leave -# this alone for now. -quartus_pgm_template = """/* Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition */ -JedecChain; - FileRevision(JESD32A); - DefaultMfr(6E); - - P ActionCode(Cfg) - Device PartName(10M50DAF484ES) Path("${POF_DIR}/") File("${POF_FILE}") MfrSpec(OpMask(1)); - -ChainEnd; - -AlteraBegin; - ChainType(JTAG); -AlteraEnd;""" - - -def create_pof(input_sof, kernel_hex): - """given an input CPU .sof file and a kernel binary, return a file-like - object containing .pof data suitable for flashing onto the device""" - - t = string.Template(quartus_cpf_template) - output_pof = tempfile.NamedTemporaryFile(suffix=".pof") - - input_sof = os.path.abspath(input_sof) - kernel_hex = os.path.abspath(kernel_hex) - - # These tools are very stupid and freak out if the desired filename - # extensions are used. The kernel image must have extension .hex - - with tempfile.NamedTemporaryFile(suffix=".cof") as temp_xml: - - xml = t.substitute(SOF_FILENAME=input_sof, - OUTPUT_FILENAME=output_pof.name, - KERNEL_FILENAME=kernel_hex) - - temp_xml.write(bytes(xml, 'UTF-8')) - temp_xml.flush() - - cmd = ["quartus_cpf", "-c", temp_xml.name] - try: - subprocess.check_output(cmd) - except subprocess.CalledProcessError as cpe: - sys.exit(cpe.output.decode("utf-8") + - "\nFailed to create POF file") - - return output_pof - - -def flash_kernel(device_id, input_sof, kernel_hex): - pof_file = create_pof(input_sof, kernel_hex) - - with tempfile.NamedTemporaryFile(suffix=".cdf") as temp_cdf: - dname, fname = os.path.split(pof_file.name) - t = string.Template(quartus_pgm_template) - cdf = t.substitute(POF_DIR=dname, POF_FILE=fname) - temp_cdf.write(bytes(cdf, 'UTF-8')) - temp_cdf.flush() - cmd = ["quartus_pgm", "-c", device_id, temp_cdf.name] - try: - subprocess.check_output(cmd) - except subprocess.CalledProcessError as cpe: - sys.exit(cpe.output.decode("utf-8") + - "\nFailed to flash image") - pof_file.close() - -def main(): - parser = argparse.ArgumentParser(description="Flash zephyr onto Altera boards", allow_abbrev=False) - parser.add_argument("-s", "--sof", - help=".sof file with Nios II CPU configuration") - parser.add_argument("-k", "--kernel", - help="Zephyr kernel image to place into UFM in Intel HEX format") - parser.add_argument("-d", "--device", - help="Remote device identifier / cable name. Default is " - "USB-BlasterII. Run jtagconfig -n if unsure.", - default="USB-BlasterII") - - args = parser.parse_args() - - flash_kernel(args.device, args.sof, args.kernel) - - -if __name__ == "__main__": - main() diff --git a/soc/altr/zephyr_nios2f/CMakeLists.txt b/soc/altr/zephyr_nios2f/CMakeLists.txt deleted file mode 100644 index 3277239a967..00000000000 --- a/soc/altr/zephyr_nios2f/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2016 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(include) -zephyr_include_directories(.) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/altr/zephyr_nios2f/Kconfig b/soc/altr/zephyr_nios2f/Kconfig deleted file mode 100644 index 6aa5654f7b5..00000000000 --- a/soc/altr/zephyr_nios2f/Kconfig +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2016 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config SOC_ZEPHYR_NIOS2F - select NIOS2 - select HAS_MUL_INSTRUCTION - select HAS_DIV_INSTRUCTION diff --git a/soc/altr/zephyr_nios2f/Kconfig.defconfig b/soc/altr/zephyr_nios2f/Kconfig.defconfig deleted file mode 100644 index 5f021107cac..00000000000 --- a/soc/altr/zephyr_nios2f/Kconfig.defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# Copyright (c) 2016 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if SOC_ZEPHYR_NIOS2F - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 50000000 - -config ALTERA_AVALON_SYSID - def_bool y - -config ALTERA_AVALON_QSPI - def_bool y - depends on SOC_FLASH_NIOS2_QSPI - -config ALTERA_AVALON_I2C - def_bool y - depends on I2C_NIOS2 - -config ALTERA_AVALON_MSGDMA - def_bool y - depends on DMA_NIOS2_MSGDMA - -endif # SOC_ZEPHYR_NIOS2F diff --git a/soc/altr/zephyr_nios2f/Kconfig.soc b/soc/altr/zephyr_nios2f/Kconfig.soc deleted file mode 100644 index b976d0b4795..00000000000 --- a/soc/altr/zephyr_nios2f/Kconfig.soc +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2016 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config SOC_ZEPHYR_NIOS2F - bool - -config SOC - default "zephyr_nios2f" if SOC_ZEPHYR_NIOS2F diff --git a/soc/altr/zephyr_nios2f/cpu/README b/soc/altr/zephyr_nios2f/cpu/README deleted file mode 100644 index ec2b9451502..00000000000 --- a/soc/altr/zephyr_nios2f/cpu/README +++ /dev/null @@ -1,19 +0,0 @@ -These files are a Nios II/F CPU design provided by Altera for evaluating -Zephyr on Nios II. This design is intended for the Altera MAX10 10M50 Rec C -development board. You can find more information about this board here: - -https://www.altera.com/products/boards_and_kits/dev-kits/altera/max-10-fpga-development-kit.html - -You will need the Quartus SDK in order to modify this CPU or flash it onto -a supported device. The Lite version of Quartus may be obtained without charge -from the following link: - -http://dl.altera.com/?edition=lite - -To flash this CPU, use the nios2-configure-sof tool: - -$ nios2-configure-sof ghrd_10m50da.sof - -The 'make flash' target will also package up the kernel and CPU into a single -.pof file which will then put the image onto the device using quartus_pgm tool. - diff --git a/soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.qpf b/soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.qpf deleted file mode 100644 index 7cd0d501064..00000000000 --- a/soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.qpf +++ /dev/null @@ -1,31 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2016 Altera Corporation. All rights reserved. -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, the Altera Quartus Prime License Agreement, -# the Altera MegaCore Function License Agreement, or other -# applicable license agreement, including, without limitation, -# that your use is for the sole purpose of programming logic -# devices manufactured by Altera and sold by Altera or its -# authorized distributors. Please refer to the applicable -# agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus Prime -# Version 16.0.0 Build 208 04/06/2016 SJ Standard Edition -# Date created = 16:01:48 April 27, 2016 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "16.0" -DATE = "16:01:48 April 27, 2016" - -# Revisions - -PROJECT_REVISION = "ghrd_10m50da" diff --git a/soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.qsf b/soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.qsf deleted file mode 100644 index 069444ae537..00000000000 --- a/soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.qsf +++ /dev/null @@ -1,412 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2016 Altera Corporation. All rights reserved. -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, the Altera Quartus Prime License Agreement, -# the Altera MegaCore Function License Agreement, or other -# applicable license agreement, including, without limitation, -# that your use is for the sole purpose of programming logic -# devices manufactured by Altera and sold by Altera or its -# authorized distributors. Please refer to the applicable -# agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus Prime -# Version 16.0.0 Build 208 04/06/2016 SJ Standard Edition -# Date created = 16:01:48 April 27, 2016 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# ghrd_10m50da_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus Prime software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - -set_global_assignment -name FAMILY "MAX 10" -set_global_assignment -name DEVICE 10M50DAF484C6GES -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:01:48 APRIL 27, 2016" -set_global_assignment -name LAST_QUARTUS_VERSION "17.0.0 Standard Edition" -set_global_assignment -name TOP_LEVEL_ENTITY ghrd_10m50da_top -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE ON -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON -set_global_assignment -name UNIPHY_TEMP_VER_CODE 1590306432 -set_global_assignment -name ECO_REGENERATE_REPORT ON -set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON -set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" -set_global_assignment -name FITTER_EFFORT "STANDARD FIT" -set_global_assignment -name ENABLE_SIGNALTAP ON -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON -set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON -set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM -set_global_assignment -name QII_AUTO_PACKED_REGISTERS NORMAL -set_global_assignment -name MUX_RESTRUCTURE OFF -set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON -set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE COMP IMAGE" -set_global_assignment -name ENABLE_OCT_DONE OFF -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall -set_global_assignment -name SEED 16 -set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE" -set_global_assignment -name ROUTER_REGISTER_DUPLICATION ON -set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS -set_location_assignment PIN_N14 -to clk_ddr3_100_p -set_location_assignment PIN_M8 -to clk_25_max10 -set_location_assignment PIN_N5 -to clk_10_adc -set_location_assignment PIN_P11 -to clk_lvds_125_p -set_location_assignment PIN_T20 -to user_led[0] -set_location_assignment PIN_U22 -to user_led[1] -set_location_assignment PIN_U21 -to user_led[2] -set_location_assignment PIN_AA21 -to user_led[3] -set_location_assignment PIN_AA22 -to user_led[4] -set_location_assignment PIN_L22 -to user_pb[0] -set_location_assignment PIN_M21 -to user_pb[1] -set_location_assignment PIN_M22 -to user_pb[2] -set_location_assignment PIN_N21 -to user_pb[3] -set_location_assignment PIN_H21 -to user_dipsw[0] -set_location_assignment PIN_H22 -to user_dipsw[1] -set_location_assignment PIN_J21 -to user_dipsw[2] -set_location_assignment PIN_J22 -to user_dipsw[3] -set_location_assignment PIN_G19 -to user_dipsw[4] -set_location_assignment PIN_Y19 -to uart_rx -set_location_assignment PIN_W18 -to uart_tx -set_location_assignment PIN_Y6 -to enet_mdc -set_location_assignment PIN_Y5 -to enet_mdio -set_location_assignment PIN_T5 -to enet_gtx_clk -set_location_assignment PIN_V7 -to enet_intn -set_location_assignment PIN_V8 -to enet_resetn -set_location_assignment PIN_P3 -to enet_rx_clk -set_location_assignment PIN_P1 -to enet_rx_col -set_location_assignment PIN_N8 -to enet_rx_crs -set_location_assignment PIN_N9 -to enet_rx_d[0] -set_location_assignment PIN_T1 -to enet_rx_d[1] -set_location_assignment PIN_N1 -to enet_rx_d[2] -set_location_assignment PIN_T3 -to enet_rx_d[3] -set_location_assignment PIN_T2 -to enet_rx_dv -set_location_assignment PIN_U2 -to enet_rx_er -set_location_assignment PIN_E10 -to enet_tx_clk -set_location_assignment PIN_R5 -to enet_tx_d[0] -set_location_assignment PIN_P5 -to enet_tx_d[1] -set_location_assignment PIN_W1 -to enet_tx_d[2] -set_location_assignment PIN_W2 -to enet_tx_d[3] -set_location_assignment PIN_R4 -to enet_tx_en -set_location_assignment PIN_P4 -to enet_tx_er -set_location_assignment PIN_R9 -to enet_led_link100 -set_location_assignment PIN_B2 -to qspi_clk -set_location_assignment PIN_C6 -to qspi_io[0] -set_location_assignment PIN_C3 -to qspi_io[1] -set_location_assignment PIN_C5 -to qspi_io[2] -set_location_assignment PIN_B1 -to qspi_io[3] -set_location_assignment PIN_C2 -to qspi_csn -set_location_assignment PIN_C22 -to mem_a[13] -set_location_assignment PIN_J14 -to mem_a[12] -set_location_assignment PIN_E20 -to mem_a[11] -set_location_assignment PIN_Y20 -to mem_a[10] -set_location_assignment PIN_E22 -to mem_a[9] -set_location_assignment PIN_D22 -to mem_a[8] -set_location_assignment PIN_B20 -to mem_a[7] -set_location_assignment PIN_C20 -to mem_a[4] -set_location_assignment PIN_A21 -to mem_a[2] -set_location_assignment PIN_D19 -to mem_a[1] -set_location_assignment PIN_E21 -to mem_a[6] -set_location_assignment PIN_F19 -to mem_a[5] -set_location_assignment PIN_U20 -to mem_a[3] -set_location_assignment PIN_V20 -to mem_a[0] -set_location_assignment PIN_W22 -to mem_ba[2] -set_location_assignment PIN_N18 -to mem_ba[1] -set_location_assignment PIN_V22 -to mem_ba[0] -set_location_assignment PIN_U19 -to mem_cas_n[0] -set_location_assignment PIN_D18 -to mem_ck[0] -set_location_assignment PIN_E18 -to mem_ck_n[0] -set_location_assignment PIN_W20 -to mem_cke[0] -set_location_assignment PIN_Y22 -to mem_cs_n[0] -set_location_assignment PIN_J15 -to mem_dm[0] -set_location_assignment PIN_K19 -to mem_dq[7] -set_location_assignment PIN_H20 -to mem_dq[6] -set_location_assignment PIN_J20 -to mem_dq[5] -set_location_assignment PIN_H19 -to mem_dq[4] -set_location_assignment PIN_K18 -to mem_dq[3] -set_location_assignment PIN_H18 -to mem_dq[2] -set_location_assignment PIN_K20 -to mem_dq[1] -set_location_assignment PIN_J18 -to mem_dq[0] -set_location_assignment PIN_K14 -to mem_dqs[0] -set_location_assignment PIN_W19 -to mem_odt[0] -set_location_assignment PIN_V18 -to mem_ras_n[0] -set_location_assignment PIN_B22 -to mem_reset_n -set_location_assignment PIN_Y21 -to mem_we_n[0] -set_location_assignment PIN_L20 -to mem_dq[8] -set_location_assignment PIN_M18 -to mem_dq[9] -set_location_assignment PIN_M20 -to mem_dq[10] -set_location_assignment PIN_M14 -to mem_dq[11] -set_location_assignment PIN_L18 -to mem_dq[12] -set_location_assignment PIN_M15 -to mem_dq[13] -set_location_assignment PIN_L19 -to mem_dq[14] -set_location_assignment PIN_N20 -to mem_dq[15] -set_location_assignment PIN_L14 -to mem_dqs[1] -set_location_assignment PIN_N19 -to mem_dm[1] -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL" -to clk_ddr3_100_p -set_instance_assignment -name IO_STANDARD "2.5 V" -to clk_50_max10 -set_instance_assignment -name IO_STANDARD "2.5 V" -to clk_25_max10 -set_instance_assignment -name IO_STANDARD LVDS -to clk_lvds_125_p -set_instance_assignment -name IO_STANDARD "2.5 V" -to clk_10_adc -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to fpga_resetn -set_instance_assignment -name IO_STANDARD "1.5 V" -to user_led[0] -set_instance_assignment -name IO_STANDARD "1.5 V" -to user_led[1] -set_instance_assignment -name IO_STANDARD "1.5 V" -to user_led[2] -set_instance_assignment -name IO_STANDARD "1.5 V" -to user_led[3] -set_instance_assignment -name IO_STANDARD "1.5 V" -to user_led[4] -set_instance_assignment -name IO_STANDARD "1.5 V" -to user_pb[0] -set_instance_assignment -name IO_STANDARD "1.5 V" -to user_pb[1] -set_instance_assignment -name IO_STANDARD "1.5 V" -to user_pb[2] -set_instance_assignment -name IO_STANDARD "1.5 V" -to user_pb[3] -set_instance_assignment -name IO_STANDARD "1.5 V" -to user_dipsw[0] -set_instance_assignment -name IO_STANDARD "1.5 V" -to user_dipsw[1] -set_instance_assignment -name IO_STANDARD "1.5 V" -to user_dipsw[2] -set_instance_assignment -name IO_STANDARD "1.5 V" -to user_dipsw[3] -set_instance_assignment -name IO_STANDARD "1.5 V" -to user_dipsw[4] -set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to user_led[0] -set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to user_led[2] -set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to user_pb[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_gtx_clk -set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_intn -set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_resetn -set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_rx_clk -set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_rx_col -set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_rx_crs -set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_rx_d[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_rx_d[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_rx_d[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_rx_d[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_rx_dv -set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_rx_er -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to enet_tx_clk -set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_tx_d[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_tx_d[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_tx_d[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_tx_d[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_tx_en -set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_tx_er -set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_led_link100 -set_instance_assignment -name GLOBAL_SIGNAL_CLKCTRL_LOCATION CLKCTRL_G2 -to enet_rx_clk -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_clk -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_csn -set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[2] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[2] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[3] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[3] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[4] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[4] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[5] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[5] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[6] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[6] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[7] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[7] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL" -to mem_dqs[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dqs[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL" -to mem_dqs_n[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dqs_n[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL" -to mem_ck[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_ck[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL" -to mem_ck_n[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_ck_n[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_a[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_a[10] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_a[11] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_a[12] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_a[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_a[2] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_a[3] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_a[4] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_a[5] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_a[6] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_a[7] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_a[8] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_a[9] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_ba[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_ba[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_ba[2] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_cs_n[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_we_n[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_ras_n[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_cas_n[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_cke[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_odt[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD 1.5V -to mem_reset_n -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dm[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dm[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name CKN_CK_PAIR ON -from mem_ck_n[0] -to mem_ck[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[2] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[3] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[4] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[5] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[6] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[7] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dm[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name DM_PIN ON -to mem_dm[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[2] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[3] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[4] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[5] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[6] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[7] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dm[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dqs[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dqs_n[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[10] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[11] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[12] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[2] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[3] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[4] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[5] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[6] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[7] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[8] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[9] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ba[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ba[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ba[2] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_cs_n[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_we_n[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ras_n[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_cas_n[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_cke[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_odt[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_reset_n -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ck[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ck_n[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name GLOBAL_SIGNAL OFF -to q_sys_inst|mem_if_ddr3_emif_0|p0|umemphy|ureset|phy_reset_n -tag __q_sys_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name GLOBAL_SIGNAL OFF -to q_sys_inst|mem_if_ddr3_emif_0|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[0] -tag __q_sys_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to q_sys_inst|mem_if_ddr3_emif_0 -tag __q_sys_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[13] -tag __q_sys_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[13] -tag __q_sys_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to mem_a[4] -set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to mem_a[1] -set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to mem_a[7] -set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to mem_a[2] -set_instance_assignment -name GLOBAL_SIGNAL OFF -to "ghrd_system:ghrd_system_inst|ghrd_system_mem_if_ddr3_emif_0:mem_if_ddr3_emif_0|ghrd_system_mem_if_ddr3_emif_0_p0:p0|ghrd_system_mem_if_ddr3_emif_0_p0_memphy_m10:umemphy|ghrd_system_mem_if_ddr3_emif_0_p0_reset_m10:ureset|phy_reset_n" -set_instance_assignment -name GLOBAL_SIGNAL OFF -to "ghrd_system:ghrd_system_inst|ghrd_system_mem_if_ddr3_emif_0:mem_if_ddr3_emif_0|ghrd_system_mem_if_ddr3_emif_0_p0:p0|ghrd_system_mem_if_ddr3_emif_0_p0_memphy_m10:umemphy|ghrd_system_mem_if_ddr3_emif_0_p0_read_datapath_m10:uread_datapath|rdata_per_dq_group[0].reset_n_fifo_wraddress[0]" -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL" -to mem_dqs[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dqs[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL" -to mem_dqs_n[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dqs_n[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dqs[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dqs_n[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[9] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[10] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[11] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[12] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[13] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[14] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[15] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[8] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[9] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[10] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[11] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[12] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[13] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[14] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[15] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[8] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[8] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[9] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[10] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[11] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[12] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[13] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[14] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[15] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[1] -to mem_dq[9] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[1] -to mem_dq[10] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[1] -to mem_dq[11] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[1] -to mem_dq[12] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[1] -to mem_dq[13] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[1] -to mem_dq[14] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[1] -to mem_dq[15] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[1] -to mem_dq[8] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[1] -to mem_dm[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dm[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dm[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name DM_PIN ON -to mem_dm[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dm[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name GLOBAL_SIGNAL OFF -to ghrd_system_inst|mem_if_ddr3_emif_0|p0|umemphy|ureset|phy_reset_n -tag __ghrd_system_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name GLOBAL_SIGNAL OFF -to ghrd_system_inst|mem_if_ddr3_emif_0|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[0] -tag __ghrd_system_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name GLOBAL_SIGNAL OFF -to ghrd_system_inst|mem_if_ddr3_emif_0|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[1] -tag __ghrd_system_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to ghrd_system_inst|mem_if_ddr3_emif_0 -tag __ghrd_system_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name GLOBAL_SIGNAL OFF -to "dut_example_if0:if0|dut_example_if0_p0:p0|dut_example_if0_p0_ghrd_system_mem_if_ddr3_emif_0_p0_m10:umemphy|dut_example_if0_p0_dqdqs_pads_m10:dq_ddio[*].ubidir_dq_dqs|altera_gpio_lite:dq_ddio_io|altgpio_one_bit:gpio_one_bit.i_loop[*].altgpio_bit_i|fr_clock" -set_instance_assignment -name GLOBAL_SIGNAL OFF -to ghrd_10m50daf484c6ges_inst|mem_if_ddr3_emif_0|p0|umemphy|ureset|phy_reset_n -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name GLOBAL_SIGNAL OFF -to ghrd_10m50daf484c6ges_inst|mem_if_ddr3_emif_0|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name GLOBAL_SIGNAL OFF -to ghrd_10m50daf484c6ges_inst|mem_if_ddr3_emif_0|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to ghrd_10m50daf484c6ges_inst|mem_if_ddr3_emif_0 -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0 -set_instance_assignment -name GLOBAL_SIGNAL OFF -to "dut_example_if0:if0|dut_example_if0_p0:p0|dut_example_if0_p0_ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0_m10:umemphy|dut_example_if0_p0_dqdqs_pads_m10:dq_ddio[*].ubidir_dq_dqs|altera_gpio_lite:dq_ddio_io|altgpio_one_bit:gpio_one_bit.i_loop[*].altgpio_bit_i|fr_clock" -set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000 -set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_location_assignment PIN_M9 -to clk_50 -set_location_assignment PIN_D9 -to fpga_reset_n -set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF -set_global_assignment -name VERILOG_FILE ghrd_10m50da_top.v -set_global_assignment -name QIP_FILE ghrd_10m50da/synthesis/ghrd_10m50da.qip -set_global_assignment -name SDC_FILE ghrd_timing.sdc - -set_location_assignment PIN_A10 -to i2c_scl -set_location_assignment PIN_B15 -to i2c_sda -set_location_assignment PIN_B7 -to spi_sclk -set_location_assignment PIN_A6 -to spi_miso -set_location_assignment PIN_C8 -to spi_mosi -set_location_assignment PIN_C7 -to spi_ssn -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to spi_miso -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to spi_mosi -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to spi_sclk -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to spi_ssn -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to fpga_reset_n -set_global_assignment -name USE_SIGNALTAP_FILE output_files/uart.stp -set_global_assignment -name SIGNALTAP_FILE output_files/uart.stp -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.qsys b/soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.qsys deleted file mode 100644 index f816798222c..00000000000 --- a/soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.qsys +++ /dev/null @@ -1,1249 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_UNUSED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 1 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#PORT_ARESET PORT_UNUSED CT#BANDWIDTH_TYPE AUTO CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 2 CT#PORT_LOCKED PORT_UNUSED - altpll_avalon_elaboration - altpll_avalon_post_edit - IF#phasecounterselect {input 3} IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#phaseupdown {input 0} IF#scandone {output 0} IF#readdata {output 32} IF#write {input 0} IF#scanclk {input 0} IF#phasedone {output 0} IF#c4 {output 0} IF#c3 {output 0} IF#c2 {output 0} IF#address {input 2} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0} IF#scanclkena {input 0} IF#scandataout {output 0} IF#configupdate {input 0} IF#phasestep {input 0} IF#scandata {input 0} - - IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#PLL_ENHPLL_CHECK 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 - MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1 - PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ0 25.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 0 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE0 25.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK4 0 PT#STICKY_CLK3 0 PT#STICKY_CLK2 0 PT#STICKY_CLK1 0 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK0 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#CLKLOSS_CHECK 0 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE0 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1509345238202295.mif PT#ACTIVECLK_CHECK 0 - UP#locked used UP#c0 used UP#areset used UP#inclk0 used - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 - - - - - - - - - - - - - - - NO_INTERACTIVE_WINDOWS - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ]]> - - ]]> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ]]> - - - - - - - - - - - - - - - - - - - - - - ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 - - - - - - - - - - - - - - - - - ]]> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Single Compressed Image - Internal Configuration - - - - - - Read and write,Read and write,Read and write,Read and write,Hidden - $${FILENAME}_onchip_flash_0 - - altera_onchip_flash.hex - altera_onchip_flash.dat - - - - - $${FILENAME}_onchip_memory2_0 - - - - - - ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.sof b/soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.sof deleted file mode 100644 index 6c19755fa6f..00000000000 Binary files a/soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.sof and /dev/null differ diff --git a/soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.sopcinfo b/soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.sopcinfo deleted file mode 100644 index 91d6c0ac929..00000000000 --- a/soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.sopcinfo +++ /dev/null @@ -1,18989 +0,0 @@ - - - - - - - java.lang.Integer - 1512455752 - false - true - false - true - GENERATION_ID - - - java.lang.String - - false - true - false - true - UNIQUE_ID - - - java.lang.String - MAX10FPGA - false - true - false - true - DEVICE_FAMILY - - - java.lang.String - 10M50DAF484C6GES - false - true - false - true - DEVICE - - - java.lang.String - 6 - false - true - false - true - DEVICE_SPEEDGRADE - - - java.lang.Long - -1 - false - true - false - true - CLOCK_RATE - clk - - - java.lang.Integer - -1 - false - true - false - true - CLOCK_DOMAIN - clk - - - java.lang.Integer - -1 - false - true - false - true - RESET_DOMAIN - clk - - - java.lang.String - MAX 10 - false - true - false - true - DEVICE_FAMILY - - - boolean - false - false - true - true - true - - - - - embeddedsw.CMacro.FIFO_DEPTH - 64 - - - embeddedsw.CMacro.FIFO_MODE - 1 - - - embeddedsw.CMacro.FIO_HWFC - 0 - - - embeddedsw.CMacro.FIO_SWFC - 0 - - - embeddedsw.CMacro.FREQ - 50000000 - - - embeddedsw.dts.compatible - altr,16550-FIFO64 ns16550a - - - embeddedsw.dts.group - serial - - - embeddedsw.dts.params.clock-frequency - 50000000 - - - embeddedsw.dts.params.fifo-size - 64 - - - embeddedsw.dts.params.reg-io-width - 4 - - - embeddedsw.dts.params.reg-shift - 2 - - - embeddedsw.dts.vendor - altr - - - java.lang.String - MAX10FPGA - false - true - false - true - DEVICE_FAMILY - - - java.lang.String - AUTO - false - true - true - true - - - int - 1 - false - true - true - true - - - int - 64 - false - true - true - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 50000000 - false - true - false - true - CLOCK_RATE - clock - - - java.lang.String - ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 - false - true - false - true - DEVICE_FEATURES - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 0 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - DYNAMIC - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 512 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - SYMBOLS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clock - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - int - 8 - false - true - true - true - - - java.math.BigInteger - - false - true - false - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - true - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 1 - false - true - true - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - addr - Input - 9 - address - - - write - Input - 1 - write - - - writedata - Input - 32 - writedata - - - read - Input - 1 - read - - - readdata - Output - 32 - readdata - - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 50000000 - true - true - false - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - clock - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - rst_n - Input - 1 - reset_n - - - - - - com.altera.entityinterfaces.IConnectionPoint - a_16550_uart_0.avalon_slave - false - true - true - true - - - java.lang.String - clock - false - true - false - true - - - java.lang.String - reset_sink - false - true - false - true - - - java.lang.Integer - - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - NONE - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - false - - intr - Output - 1 - irq - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - sin - Input - 1 - sin - - - sout - Output - 1 - sout - - - sout_oe - Output - 1 - sout_oe - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - cts_n - Input - 1 - cts_n - - - rts_n - Output - 1 - rts_n - - - dsr_n - Input - 1 - dsr_n - - - dcd_n - Input - 1 - dcd_n - - - ri_n - Input - 1 - ri_n - - - dtr_n - Output - 1 - dtr_n - - - out1_n - Output - 1 - out1_n - - - out2_n - Output - 1 - out2_n - - - - - - - java.lang.String - altpll_avalon_elaboration - false - true - false - true - - - java.lang.String - altpll_avalon_post_edit - false - true - false - true - - - java.lang.String - MAX 10 - false - true - true - true - - - java.lang.String - 5 - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - 20000 - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - NORMAL - false - true - true - true - - - java.lang.String - AUTO - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - CLK0 - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - AUTO - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - 1 - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - 2 - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - 0 - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - 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- - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_USED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - NO - false - true - true - true - - - java.lang.String - CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_UNUSED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 1 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#PORT_ARESET PORT_UNUSED CT#BANDWIDTH_TYPE AUTO CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 2 CT#PORT_LOCKED PORT_UNUSED - false - true - false - true - - - java.lang.String - PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ0 25.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 0 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE0 25.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK4 0 PT#STICKY_CLK3 0 PT#STICKY_CLK2 0 PT#STICKY_CLK1 0 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK0 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#CLKLOSS_CHECK 0 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE0 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1509345238202295.mif PT#ACTIVECLK_CHECK 0 - false - true - false - true - - - java.lang.String - UP#locked used UP#c0 used UP#areset used UP#inclk0 used - false - true - false - true - - - java.lang.String - IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#PLL_ENHPLL_CHECK 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 - false - true - false - true - - - java.lang.String - MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1 - false - true - false - true - - - java.lang.String - IF#phasecounterselect {input 3} IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#phaseupdown {input 0} IF#scandone {output 0} IF#readdata {output 32} IF#write {input 0} IF#scanclk {input 0} IF#phasedone {output 0} IF#c4 {output 0} IF#c3 {output 0} IF#c2 {output 0} IF#address {input 2} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0} IF#scanclkena {input 0} IF#scandataout {output 0} IF#configupdate {input 0} IF#phasestep {input 0} IF#scandata {input 0} - false - true - false - true - - - java.lang.String - 0 - false - true - false - true - - - java.lang.String - MAX10FPGA - false - true - false - true - DEVICE_FAMILY - - - java.lang.Long - 50000000 - false - true - false - true - CLOCK_RATE - inclk_interface - - - java.lang.String - MAX 10 - false - true - false - true - DEVICE_FAMILY - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 50000000 - true - true - false - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - inclk_interface - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset - Input - 1 - reset - - - - - - embeddedsw.configuration.isMemoryDevice - false - - - embeddedsw.configuration.isNonVolatileStorage - false - - - embeddedsw.configuration.isPrintableDevice - false - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - DYNAMIC - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 16 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - inclk_interface - false - true - true - true - - - java.lang.String - inclk_interface_reset - false - true - true - true - - - int - 8 - false - true - true - true - - - java.math.BigInteger - - false - true - false - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - true - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - read - Input - 1 - read - - - write - Input - 1 - write - - - address - Input - 2 - address - - - readdata - Output - 32 - readdata - - - writedata - Input - 32 - writedata - - - - - - java.lang.String - - false - true - true - true - - - long - 25000000 - false - true - true - true - - - boolean - true - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - true - - c0 - Output - 1 - clk - - - false - ext_flash - clock_sink - ext_flash.clock_sink - - - - - - - long - 50000000 - false - true - true - true - - - boolean - true - false - true - true - true - - - long - 0 - false - true - false - true - CLOCK_RATE - clk_in - - - com.altera.sopcmodel.reset.Reset$Edges - NONE - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - qsys.ui.export_name - clk - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 50000000 - true - true - false - true - - clock - false - - in_clk - Input - 1 - clk - - - - - - qsys.ui.export_name - reset - - - java.lang.String - - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - NONE - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - java.lang.String - clk_in - false - true - true - true - - - long - 50000000 - false - true - true - true - - - boolean - true - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - true - - clk_out - Output - 1 - clk - - - false - nios2_gen2_0 - clk - nios2_gen2_0.clk - - - false - jtag_uart_0 - clk - jtag_uart_0.clk - - - false - timer_0 - clk - timer_0.clk - - - false - spi_0 - clk - spi_0.clk - - - false - led - clk - led.clk - - - false - sysid - clk - sysid.clk - - - false - onchip_flash_0 - clk - onchip_flash_0.clk - - - false - onchip_memory2_0 - clk1 - onchip_memory2_0.clk1 - - - false - a_16550_uart_0 - clock - a_16550_uart_0.clock - - - false - msgdma_0 - clock - msgdma_0.clock - - - false - i2c_0 - clock - i2c_0.clock - - - false - altpll_0 - inclk_interface - altpll_0.inclk_interface - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - clk_in_reset - false - true - true - true - - - [Ljava.lang.String; - clk_in_reset - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - NONE - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - true - - reset_n_out - Output - 1 - reset_n - - - - - - - embeddedsw.CMacro.FLASH_TYPE - Micron512 - - - embeddedsw.CMacro.IS_EPCS - 0 - - - embeddedsw.CMacro.NUMBER_OF_SECTORS - 1024 - - - embeddedsw.CMacro.PAGE_SIZE - 256 - - - embeddedsw.CMacro.SECTOR_SIZE - 65536 - - - embeddedsw.CMacro.SUBSECTOR_SIZE - 4096 - - - embeddedsw.dts.compatible - altr,quadspi-2.0 - - - embeddedsw.dts.group - quadspi - - - embeddedsw.dts.name - quadspi - - - embeddedsw.dts.vendor - altr - - - embeddedsw.memoryInfo.GENERATE_DAT_SYM - 0 - - - embeddedsw.memoryInfo.GENERATE_FLASH - 0 - - - embeddedsw.memoryInfo.GENERATE_HEX - 1 - - - embeddedsw.memoryInfo.HEX_INSTALL_DIR - QPF_DIR - - - embeddedsw.memoryInfo.IS_FLASH - 1 - - - embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH - 32 - - - embeddedsw.memoryInfo.USE_BYTE_ADDRESSING_FOR_HEX - 1 - - - java.lang.String - MAX10FPGA - false - true - false - true - DEVICE_FAMILY - - - long - 25000000 - false - true - false - true - CLOCK_RATE - clock_sink - - - int - 3 - true - true - false - true - - - int - 24 - true - true - false - true - - - int - 4 - true - true - false - true - - - int - 32 - true - true - false - true - - - int - 1 - true - true - false - true - - - int - 1 - true - true - false - true - - - java.lang.String - Micron512 - false - true - true - true - - - java.lang.String - QUAD - false - true - true - true - - - int - 1 - false - true - true - true - - - java.lang.String - ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 - false - true - false - true - DEVICE_FEATURES - - - java.lang.String - 10M50DAF484C6GES - false - true - false - true - DEVICE - - - java.lang.String - 6 - false - true - false - true - DEVICE_SPEEDGRADE - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - flash_dclk_out - Output - 1 - dclk - - - flash_ncs - Output - 1 - ncs - - - flash_dataout - Bidir - 4 - data - - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 0 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - DYNAMIC - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 64 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - java.math.BigInteger - 0 - false - true - false - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - false - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 1 - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - false - true - true - - - int - 0 - false - true - false - true - - - int - 0 - false - false - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - false - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - false - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - false - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - avl_csr_read - Input - 1 - read - - - avl_csr_waitrequest - Output - 1 - waitrequest - - - avl_csr_write - Input - 1 - write - - - avl_csr_addr - Input - 4 - address - - - avl_csr_wrdata - Input - 32 - writedata - - - avl_csr_rddata - Output - 32 - readdata - - - avl_csr_rddata_valid - Output - 1 - readdatavalid - - - - - - embeddedsw.configuration.isFlash - 1 - - - embeddedsw.configuration.isMemoryDevice - 1 - - - embeddedsw.configuration.isNonVolatileStorage - 1 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - DYNAMIC - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 67108864 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clock_sink - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - java.math.BigInteger - 0 - false - true - false - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - true - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - false - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - true - false - true - true - true - - - int - 1 - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - false - true - true - - - int - 0 - false - true - false - true - - - int - 0 - false - false - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - false - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - false - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - false - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - avl_mem_write - Input - 1 - write - - - avl_mem_burstcount - Input - 7 - burstcount - - - avl_mem_waitrequest - Output - 1 - waitrequest - - - avl_mem_read - Input - 1 - read - - - avl_mem_addr - Input - 24 - address - - - avl_mem_wrdata - Input - 32 - writedata - - - avl_mem_rddata - Output - 32 - readdata - - - avl_mem_rddata_valid - Output - 1 - readdatavalid - - - avl_mem_byteenable - Input - 4 - byteenable - - - - - - com.altera.entityinterfaces.IConnectionPoint - ext_flash.avl_csr - false - true - true - true - - - java.lang.String - clock_sink - false - true - false - true - - - java.lang.String - reset - false - true - false - true - - - java.lang.Integer - 0 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - NONE - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - false - - irq - Output - 1 - irq - - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 25000000 - true - true - false - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - clock_sink - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - - embeddedsw.CMacro.FIFO_DEPTH - 16 - - - embeddedsw.CMacro.FREQ - 50000000 - - - embeddedsw.CMacro.USE_AV_ST - 0 - - - int - 0 - false - true - true - true - - - int - 16 - false - true - true - true - - - int - 4 - true - true - false - true - - - int - 50000000 - false - true - false - true - CLOCK_RATE - clock - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 50000000 - true - true - false - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - clock - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - rst_n - Input - 1 - reset_n - - - - - - com.altera.entityinterfaces.IConnectionPoint - i2c_0.csr - false - true - true - true - - - java.lang.String - clock - false - true - false - true - - - java.lang.String - reset_sink - false - true - false - true - - - java.lang.Integer - - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - NONE - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - false - - intr - Output - 1 - irq - - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 0 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - DYNAMIC - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 64 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clock - false - true - true - true - - - java.lang.String - reset_sink - false - true - true - true - - - int - 8 - false - true - true - true - - - java.math.BigInteger - - false - true - false - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - true - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 2 - false - true - true - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - addr - Input - 4 - address - - - read - Input - 1 - read - - - write - Input - 1 - write - - - writedata - Input - 32 - writedata - - - readdata - Output - 32 - readdata - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - sda_in - Input - 1 - sda_in - - - scl_in - Input - 1 - scl_in - - - sda_oe - Output - 1 - sda_oe - - - scl_oe - Output - 1 - scl_oe - - - - - - - embeddedsw.CMacro.READ_DEPTH - 64 - - - embeddedsw.CMacro.READ_THRESHOLD - 8 - - - embeddedsw.CMacro.WRITE_DEPTH - 64 - - - embeddedsw.CMacro.WRITE_THRESHOLD - 8 - - - embeddedsw.dts.compatible - altr,juart-1.0 - - - embeddedsw.dts.group - serial - - - embeddedsw.dts.name - juart - - - embeddedsw.dts.vendor - altr - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 64 - false - true - true - true - - - int - 8 - false - true - true - true - - - java.lang.String - - false - false - false - true - - - java.lang.String - NO_INTERACTIVE_WINDOWS - false - true - false - true - - - boolean - true - false - true - true - true - - - boolean - true - false - true - true - true - - - boolean - false - false - true - false - true - - - int - 64 - false - true - true - true - - - int - 8 - false - true - true - true - - - long - 50000000 - false - true - false - true - CLOCK_RATE - clk - - - java.lang.String - 2.0 - false - true - false - true - AVALON_SPEC - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 50000000 - true - true - false - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - clk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - rst_n - Input - 1 - reset_n - - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 0 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 1 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - NATIVE - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 2 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - java.math.BigInteger - - false - true - false - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - false - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - true - true - - - int - 1 - false - true - false - true - - - boolean - true - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - false - true - - - int - 1 - false - false - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - false - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - false - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - false - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - av_chipselect - Input - 1 - chipselect - - - av_address - Input - 1 - address - - - av_read_n - Input - 1 - read_n - - - av_readdata - Output - 32 - readdata - - - av_write_n - Input - 1 - write_n - - - av_writedata - Input - 32 - writedata - - - av_waitrequest - Output - 1 - waitrequest - - - - - - com.altera.entityinterfaces.IConnectionPoint - jtag_uart_0.avalon_jtag_slave - false - true - true - true - - - java.lang.String - clk - false - true - false - true - - - java.lang.String - reset - false - true - false - true - - - java.lang.Integer - - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - NONE - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - false - - av_irq - Output - 1 - irq - - - - - - - embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER - 0 - - - embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER - 0 - - - embeddedsw.CMacro.CAPTURE - 0 - - - embeddedsw.CMacro.DATA_WIDTH - 4 - - - embeddedsw.CMacro.DO_TEST_BENCH_WIRING - 0 - - - embeddedsw.CMacro.DRIVEN_SIM_VALUE - 0 - - - embeddedsw.CMacro.EDGE_TYPE - NONE - - - embeddedsw.CMacro.FREQ - 50000000 - - - embeddedsw.CMacro.HAS_IN - 0 - - - embeddedsw.CMacro.HAS_OUT - 1 - - - embeddedsw.CMacro.HAS_TRI - 0 - - - embeddedsw.CMacro.IRQ_TYPE - NONE - - - embeddedsw.CMacro.RESET_VALUE - 0 - - - embeddedsw.dts.compatible - altr,pio-1.0 - - - embeddedsw.dts.group - gpio - - - embeddedsw.dts.name - pio - - - embeddedsw.dts.params.altr,gpio-bank-width - 4 - - - embeddedsw.dts.params.resetvalue - 0 - - - embeddedsw.dts.vendor - altr - - - boolean - false - false - false - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - false - true - true - - - java.lang.String - Output - false - true - true - true - - - java.lang.String - RISING - false - false - true - true - - - boolean - false - false - false - true - true - - - java.lang.String - LEVEL - false - false - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - false - true - true - - - long - 0 - false - false - true - true - - - int - 4 - false - true - true - true - - - long - 50000000 - false - true - false - true - CLOCK_RATE - clk - - - boolean - false - true - true - false - true - - - boolean - true - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 50000000 - true - true - false - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - clk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 0 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - NATIVE - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 4 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - java.math.BigInteger - - false - true - false - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - true - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - false - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - address - Input - 2 - address - - - write_n - Input - 1 - write_n - - - writedata - Input - 32 - writedata - - - chipselect - Input - 1 - chipselect - - - readdata - Output - 32 - readdata - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - out_port - Output - 4 - export - - - - - - - embeddedsw.CMacro.BURST_ENABLE - 1 - - - embeddedsw.CMacro.BURST_WRAPPING_SUPPORT - 1 - - - embeddedsw.CMacro.CHANNEL_ENABLE - 0 - - - embeddedsw.CMacro.CHANNEL_ENABLE_DERIVED - 0 - - - embeddedsw.CMacro.CHANNEL_WIDTH - 8 - - - embeddedsw.CMacro.DATA_FIFO_DEPTH - 32 - - - embeddedsw.CMacro.DATA_WIDTH - 32 - - - embeddedsw.CMacro.DESCRIPTOR_FIFO_DEPTH - 128 - - - embeddedsw.CMacro.DMA_MODE - 0 - - - embeddedsw.CMacro.ENHANCED_FEATURES - 0 - - - embeddedsw.CMacro.ERROR_ENABLE - 0 - - - embeddedsw.CMacro.ERROR_ENABLE_DERIVED - 0 - - - embeddedsw.CMacro.ERROR_WIDTH - 8 - - - embeddedsw.CMacro.MAX_BURST_COUNT - 2 - - - embeddedsw.CMacro.MAX_BYTE - 1024 - - - embeddedsw.CMacro.MAX_STRIDE - 1 - - - embeddedsw.CMacro.PACKET_ENABLE - 0 - - - embeddedsw.CMacro.PACKET_ENABLE_DERIVED - 0 - - - embeddedsw.CMacro.PREFETCHER_ENABLE - 0 - - - embeddedsw.CMacro.PROGRAMMABLE_BURST_ENABLE - 0 - - - embeddedsw.CMacro.RESPONSE_PORT - 2 - - - embeddedsw.CMacro.STRIDE_ENABLE - 0 - - - embeddedsw.CMacro.STRIDE_ENABLE_DERIVED - 0 - - - embeddedsw.CMacro.TRANSFER_TYPE - Aligned Accesses - - - embeddedsw.dts.compatible - altr,msgdma-1.0 - - - embeddedsw.dts.group - msgdma - - - embeddedsw.dts.name - msgdma - - - embeddedsw.dts.vendor - altr - - - int - 0 - false - true - true - true - - - int - 32 - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 32 - false - false - true - true - - - int - 0 - false - true - true - true - - - int - 32 - false - true - true - true - - - int - 128 - false - true - true - true - - - int - 2 - false - true - true - true - - - int - 1024 - false - true - true - true - - - java.lang.String - Aligned Accesses - false - true - true - true - - - int - 1 - false - true - true - true - - - int - 2 - false - true - true - true - - - int - 1 - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 1 - false - false - true - true - - - int - 0 - false - false - true - true - - - int - 0 - true - true - false - true - - - int - 0 - false - false - true - true - - - int - 0 - true - true - false - true - - - int - 0 - false - false - true - true - - - int - 0 - true - true - false - true - - - int - 8 - false - false - true - true - - - int - 0 - false - false - true - true - - - int - 0 - true - true - false - true - - - int - 8 - false - false - true - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 32 - false - true - true - true - - - int - 2 - false - false - true - true - - - java.lang.String - MAX10FPGA - false - true - false - true - DEVICE_FAMILY - - - java.lang.String - 10M50DAF484C6GES - false - true - false - true - DEVICE - - - java.lang.String - 6 - false - true - false - true - DEVICE_SPEEDGRADE - - - com.altera.entityinterfaces.moduleext.AddressMap - ]]> - false - true - false - true - ADDRESS_MAP - mm_read - - - com.altera.entityinterfaces.moduleext.AddressWidthType - AddressWidth = 23 - false - true - false - true - ADDRESS_WIDTH - mm_read - - - com.altera.entityinterfaces.moduleext.AddressMap - ]]> - false - true - false - true - ADDRESS_MAP - mm_write - - - com.altera.entityinterfaces.moduleext.AddressWidthType - AddressWidth = 23 - false - true - false - true - ADDRESS_WIDTH - mm_write - - - com.altera.entityinterfaces.moduleext.AddressMap - - false - true - false - true - ADDRESS_MAP - descriptor_read_master - - - com.altera.entityinterfaces.moduleext.AddressWidthType - AddressWidth = -1 - false - true - false - true - ADDRESS_WIDTH - descriptor_read_master - - - com.altera.entityinterfaces.moduleext.AddressMap - - false - true - false - true - ADDRESS_MAP - descriptor_write_master - - - com.altera.entityinterfaces.moduleext.AddressWidthType - AddressWidth = -1 - false - true - false - true - ADDRESS_WIDTH - descriptor_write_master - - - java.lang.String - MAX 10 - false - true - false - true - DEVICE_FAMILY - - - boolean - false - false - true - true - true - - - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - int - 0 - false - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - SYMBOLS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clock - false - true - true - true - - - java.lang.String - reset_n - false - true - true - true - - - int - 8 - false - true - true - true - - - boolean - true - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 32 - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - true - - mm_read_address - Output - 23 - address - - - mm_read_read - Output - 1 - read - - - mm_read_byteenable - Output - 4 - byteenable - - - mm_read_readdata - Input - 32 - readdata - - - mm_read_waitrequest - Input - 1 - waitrequest - - - mm_read_readdatavalid - Input - 1 - readdatavalid - - - mm_read_burstcount - Output - 2 - burstcount - - - false - onchip_memory2_0 - s1 - onchip_memory2_0.s1 - 4194304 - 131072 - - - - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - int - 0 - false - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - SYMBOLS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clock - false - true - true - true - - - java.lang.String - reset_n - false - true - true - true - - - int - 8 - false - true - true - true - - - boolean - true - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 32 - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - true - - mm_write_address - Output - 23 - address - - - mm_write_write - Output - 1 - write - - - mm_write_byteenable - Output - 4 - byteenable - - - mm_write_writedata - Output - 32 - writedata - - - mm_write_waitrequest - Input - 1 - waitrequest - - - mm_write_burstcount - Output - 2 - burstcount - - - false - onchip_memory2_0 - s1 - onchip_memory2_0.s1 - 4194304 - 131072 - - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clock_clk - Input - 1 - clk - - - - - - java.lang.String - clock - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n_reset_n - Input - 1 - reset_n - - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 0 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - DYNAMIC - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 32 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clock - false - true - true - true - - - java.lang.String - reset_n - false - true - true - true - - - int - 8 - false - true - true - true - - - java.math.BigInteger - 0 - false - true - false - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - true - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 1 - false - true - true - true - - - int - 1 - false - true - false - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - csr_writedata - Input - 32 - writedata - - - csr_write - Input - 1 - write - - - csr_byteenable - Input - 4 - byteenable - - - csr_readdata - Output - 32 - readdata - - - csr_read - Input - 1 - read - - - csr_address - Input - 3 - address - - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 0 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - DYNAMIC - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 16 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clock - false - true - true - true - - - java.lang.String - reset_n - false - true - true - true - - - int - 8 - false - true - true - true - - - java.math.BigInteger - 0 - false - true - false - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - false - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - true - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - false - true - - - int - 1 - false - false - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - false - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - false - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - false - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - descriptor_slave_write - Input - 1 - write - - - descriptor_slave_waitrequest - Output - 1 - waitrequest - - - descriptor_slave_writedata - Input - 128 - writedata - - - descriptor_slave_byteenable - Input - 16 - byteenable - - - - - - com.altera.entityinterfaces.IConnectionPoint - msgdma_0.csr - false - true - true - true - - - java.lang.String - clock - false - true - false - true - - - java.lang.String - reset_n - false - true - false - true - - - java.lang.Integer - 0 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - NONE - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - false - - csr_irq_irq - Output - 1 - irq - - - - - - - debug.hostConnection - type jtag id 70:34|110:135 - - - embeddedsw.CMacro.BIG_ENDIAN - 0 - - - embeddedsw.CMacro.BREAK_ADDR - 0x00200820 - - - embeddedsw.CMacro.CPU_ARCH_NIOS2_R1 - - - - embeddedsw.CMacro.CPU_FREQ - 50000000u - - - embeddedsw.CMacro.CPU_ID_SIZE - 1 - - - embeddedsw.CMacro.CPU_ID_VALUE - 0x00000000 - - - embeddedsw.CMacro.CPU_IMPLEMENTATION - "fast" - - - embeddedsw.CMacro.DATA_ADDR_WIDTH - 28 - - - embeddedsw.CMacro.DCACHE_BYPASS_MASK - 0x80000000 - - - embeddedsw.CMacro.DCACHE_LINE_SIZE - 32 - - - embeddedsw.CMacro.DCACHE_LINE_SIZE_LOG2 - 5 - - - embeddedsw.CMacro.DCACHE_SIZE - 2048 - - - embeddedsw.CMacro.EXCEPTION_ADDR - 0x00400020 - - - embeddedsw.CMacro.FLASH_ACCELERATOR_LINES - 0 - - - embeddedsw.CMacro.FLASH_ACCELERATOR_LINE_SIZE - 0 - - - embeddedsw.CMacro.FLUSHDA_SUPPORTED - - - - embeddedsw.CMacro.HARDWARE_DIVIDE_PRESENT - 1 - - - embeddedsw.CMacro.HARDWARE_MULTIPLY_PRESENT - 1 - - - embeddedsw.CMacro.HARDWARE_MULX_PRESENT - 0 - - - embeddedsw.CMacro.HAS_DEBUG_CORE - 1 - - - embeddedsw.CMacro.HAS_DEBUG_STUB - - - - embeddedsw.CMacro.HAS_DIVISION_ERROR_EXCEPTION - - - - embeddedsw.CMacro.HAS_EXTRA_EXCEPTION_INFO - - - - embeddedsw.CMacro.HAS_ILLEGAL_INSTRUCTION_EXCEPTION - - - - embeddedsw.CMacro.HAS_JMPI_INSTRUCTION - - - - embeddedsw.CMacro.ICACHE_LINE_SIZE - 32 - - - embeddedsw.CMacro.ICACHE_LINE_SIZE_LOG2 - 5 - - - embeddedsw.CMacro.ICACHE_SIZE - 4096 - - - embeddedsw.CMacro.INITDA_SUPPORTED - - - - embeddedsw.CMacro.INST_ADDR_WIDTH - 28 - - - embeddedsw.CMacro.NUM_OF_SHADOW_REG_SETS - 0 - - - embeddedsw.CMacro.OCI_VERSION - 1 - - - embeddedsw.CMacro.RESET_ADDR - 0x00000000 - - - embeddedsw.configuration.DataCacheVictimBufImpl - ram - - - embeddedsw.configuration.HDLSimCachesCleared - 1 - - - embeddedsw.configuration.breakOffset - 32 - - - embeddedsw.configuration.breakSlave - nios2_gen2_0.debug_mem_slave - - - embeddedsw.configuration.cpuArchitecture - Nios II - - - embeddedsw.configuration.exceptionOffset - 32 - - - embeddedsw.configuration.exceptionSlave - onchip_memory2_0.s1 - - - embeddedsw.configuration.resetOffset - 0 - - - embeddedsw.configuration.resetSlave - onchip_flash_0.data - - - embeddedsw.dts.compatible - altr,nios2-1.1 - - - embeddedsw.dts.group - cpu - - - embeddedsw.dts.name - nios2 - - - embeddedsw.dts.params.altr,exception-addr - 0x00400020 - - - embeddedsw.dts.params.altr,has-div - 1 - - - embeddedsw.dts.params.altr,has-initda - 1 - - - embeddedsw.dts.params.altr,has-mul - 1 - - - embeddedsw.dts.params.altr,implementation - "fast" - - - embeddedsw.dts.params.altr,reset-addr - 0x00000000 - - - embeddedsw.dts.params.clock-frequency - 50000000u - - - embeddedsw.dts.params.dcache-line-size - 32 - - - embeddedsw.dts.params.dcache-size - 2048 - - - embeddedsw.dts.params.icache-line-size - 32 - - - embeddedsw.dts.params.icache-size - 4096 - - - embeddedsw.dts.vendor - altr - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - true - false - true - false - true - - - int - 0 - false - false - true - true - - - int - 0 - false - true - true - true - - - boolean - true - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - false - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - true - false - false - true - true - - - boolean - false - false - true - true - true - - - boolean - true - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 8 - false - false - true - true - - - int - 8 - false - false - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - true - true - true - - - int - 32 - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 32 - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - onchip_flash_0.data - false - true - true - true - - - java.lang.String - None - false - false - true - true - - - java.lang.String - onchip_memory2_0.s1 - false - true - true - true - - - java.lang.String - None - false - true - false - true - - - java.lang.String - Internal - false - true - true - true - - - java.lang.String - Dynamic - false - true - true - true - - - int - 8 - false - true - true - true - - - int - 1 - false - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - fast_le_shift - true - true - false - true - - - java.lang.String - mul_fast32 - true - true - false - true - - - int - 0 - false - true - true - true - - - int - 2 - false - false - true - true - - - int - 1 - false - false - true - true - - - int - 1 - false - false - true - true - - - java.lang.String - srt2 - false - true - true - true - - - int - 12 - false - false - true - true - - - int - 12 - false - false - true - true - - - int - 4 - false - false - true - true - - - int - 6 - false - false - true - true - - - int - 7 - false - false - true - true - - - int - 16 - false - false - true - true - - - int - 8 - false - false - true - true - - - java.lang.String - Fast - false - true - true - true - - - int - 4096 - false - true - true - true - - - int - 2 - false - false - true - true - - - int - 0 - false - true - true - true - - - java.lang.String - Automatic - false - true - false - true - - - java.lang.String - Automatic - false - true - false - true - - - int - 0 - false - true - true - true - - - java.lang.String - None - false - true - true - true - - - java.lang.String - false - false - true - true - true - - - java.lang.String - ram - false - true - true - true - - - int - 2048 - false - true - true - true - - - java.lang.String - Automatic - false - true - false - true - - - java.lang.String - Automatic - false - true - false - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - boolean - true - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - true - false - true - false - true - - - java.lang.String - Automatic - false - true - false - true - - - java.lang.String - Automatic - false - true - false - true - - - boolean - false - false - true - false - true - - - java.lang.String - Automatic - false - true - false - true - - - java.lang.String - Automatic - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - true - false - true - true - true - - - boolean - true - false - true - false - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - java.lang.String - _128 - false - false - true - true - - - int - 4 - false - true - true - true - - - int - 4 - false - true - true - true - - - java.lang.String - none - false - true - true - true - - - java.lang.String - onchip_trace - false - false - true - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - long - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - long - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - long - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - long - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - long - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - long - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - long - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - long - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - long - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - long - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - long - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - long - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - long - 0 - false - true - false - true - - - int - 0 - true - true - true - true - - - int - 4194336 - true - true - true - true - - - int - 2099232 - true - true - false - true - - - int - 0 - true - true - true - true - - - java.lang.String - false - true - true - false - true - - - int - 2048 - true - true - false - true - - - java.lang.String - nios2_gen2_0.debug_mem_slave - true - true - false - true - - - int - 32 - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - true - true - true - false - true - - - java.lang.String - "synthesis translate_on" - true - true - false - true - - - java.lang.String - "synthesis translate_off" - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - int - 28 - false - true - false - true - ADDRESS_WIDTH - instruction_master - - - int - 1 - false - true - false - true - ADDRESS_WIDTH - flash_instruction_master - - - int - 28 - false - true - false - true - ADDRESS_WIDTH - data_master - - - int - 1 - false - true - false - true - ADDRESS_WIDTH - tightly_coupled_data_master_0 - - - int - 1 - false - true - false - true - ADDRESS_WIDTH - tightly_coupled_data_master_1 - - - int - 1 - false - true - false - true - ADDRESS_WIDTH - tightly_coupled_data_master_2 - - - int - 1 - false - true - false - true - ADDRESS_WIDTH - tightly_coupled_data_master_3 - - - int - 1 - false - true - false - true - ADDRESS_WIDTH - tightly_coupled_instruction_master_0 - - - int - 1 - false - true - false - true - ADDRESS_WIDTH - tightly_coupled_instruction_master_1 - - - int - 1 - false - true - false - true - ADDRESS_WIDTH - tightly_coupled_instruction_master_2 - - - int - 1 - false - true - false - true - ADDRESS_WIDTH - tightly_coupled_instruction_master_3 - - - int - 1 - false - true - false - true - ADDRESS_WIDTH - data_master_high_performance - - - int - 1 - false - true - false - true - ADDRESS_WIDTH - instruction_master_high_performance - - - java.lang.String - ]]> - false - true - false - true - ADDRESS_MAP - instruction_master - - - java.lang.String - - false - true - false - true - ADDRESS_MAP - flash_instruction_master - - - java.lang.String - ]]> - false - true - false - true - ADDRESS_MAP - data_master - - - java.lang.String - - false - true - false - true - ADDRESS_MAP - tightly_coupled_data_master_0 - - - java.lang.String - - false - true - false - true - ADDRESS_MAP - tightly_coupled_data_master_1 - - - java.lang.String - - false - true - false - true - ADDRESS_MAP - tightly_coupled_data_master_2 - - - java.lang.String - - false - true - false - true - ADDRESS_MAP - tightly_coupled_data_master_3 - - - java.lang.String - - false - true - false - true - ADDRESS_MAP - tightly_coupled_instruction_master_0 - - - java.lang.String - - false - true - false - true - ADDRESS_MAP - tightly_coupled_instruction_master_1 - - - java.lang.String - - false - true - false - true - ADDRESS_MAP - tightly_coupled_instruction_master_2 - - - java.lang.String - - false - true - false - true - ADDRESS_MAP - tightly_coupled_instruction_master_3 - - - java.lang.String - - false - true - false - true - ADDRESS_MAP - data_master_high_performance - - - java.lang.String - - false - true - false - true - ADDRESS_MAP - instruction_master_high_performance - - - long - 50000000 - false - true - false - true - CLOCK_RATE - clk - - - java.lang.String - MAX10FPGA - false - true - false - true - DEVICE_FAMILY - - - long - 127 - false - true - false - true - INTERRUPTS_USED - irq - - - java.lang.String - ]]> - false - true - false - true - CUSTOM_INSTRUCTION_SLAVES - custom_instruction_master - - - java.lang.String - ]]> - false - true - false - true - CUSTOM_INSTRUCTION_SLAVES - custom_instruction_master_a - - - java.lang.String - ]]> - false - true - false - true - CUSTOM_INSTRUCTION_SLAVES - custom_instruction_master_b - - - java.lang.String - ]]> - false - true - false - true - CUSTOM_INSTRUCTION_SLAVES - custom_instruction_master_c - - - java.lang.String - ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 - false - true - false - true - DEVICE_FEATURES - - - java.lang.String - 10M50DAF484C6GES - false - true - false - true - DEVICE - - - java.lang.String - 6 - false - true - false - true - DEVICE_SPEEDGRADE - - - java.lang.Integer - 2 - false - true - false - true - CLOCK_DOMAIN - clk - - - java.lang.Integer - 2 - false - true - false - true - RESET_DOMAIN - clk - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 50000000 - true - true - false - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - clk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - reset_req - Input - 1 - reset_req - - - - - - debug.providesServices - master - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - int - 1 - false - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - SYMBOLS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - boolean - true - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 32 - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - true - - d_address - Output - 28 - address - - - d_byteenable - Output - 4 - byteenable - - - d_read - Output - 1 - read - - - d_readdata - Input - 32 - readdata - - - d_waitrequest - Input - 1 - waitrequest - - - d_write - Output - 1 - write - - - d_writedata - Output - 32 - writedata - - - d_readdatavalid - Input - 1 - readdatavalid - - - debug_mem_slave_debugaccess_to_roms - Output - 1 - debugaccess - - - false - jtag_uart_0 - avalon_jtag_slave - jtag_uart_0.avalon_jtag_slave - 2101248 - 8 - - - false - a_16550_uart_0 - avalon_slave - a_16550_uart_0.avalon_slave - 1048576 - 512 - - - false - ext_flash - avl_csr - ext_flash.avl_csr - 1049152 - 64 - - - false - ext_flash - avl_mem - ext_flash.avl_mem - 134217728 - 67108864 - - - false - sysid - control_slave - sysid.control_slave - 1049344 - 8 - - - false - msgdma_0 - csr - msgdma_0.csr - 1049280 - 32 - - - false - i2c_0 - csr - i2c_0.csr - 1049088 - 64 - - - false - onchip_flash_0 - csr - onchip_flash_0.csr - 2097152 - 8 - - - false - onchip_flash_0 - data - onchip_flash_0.data - 0 - 753664 - - - false - nios2_gen2_0 - debug_mem_slave - nios2_gen2_0.debug_mem_slave - 2099200 - 2048 - - - false - msgdma_0 - descriptor_slave - msgdma_0.descriptor_slave - 1049328 - 16 - - - false - onchip_memory2_0 - s1 - onchip_memory2_0.s1 - 4194304 - 131072 - - - false - timer_0 - s1 - timer_0.s1 - 1049248 - 32 - - - false - led - s1 - led.s1 - 1049312 - 16 - - - false - spi_0 - spi_control_port - spi_0.spi_control_port - 1049216 - 32 - - - - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - int - 1 - false - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - SYMBOLS - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - true - false - true - true - true - - - int - 32 - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - true - - i_address - Output - 28 - address - - - i_read - Output - 1 - read - - - i_readdata - Input - 32 - readdata - - - i_waitrequest - Input - 1 - waitrequest - - - i_readdatavalid - Input - 1 - readdatavalid - - - false - ext_flash - avl_mem - ext_flash.avl_mem - 134217728 - 67108864 - - - false - onchip_flash_0 - data - onchip_flash_0.data - 0 - 753664 - - - false - nios2_gen2_0 - debug_mem_slave - nios2_gen2_0.debug_mem_slave - 2099200 - 2048 - - - false - onchip_memory2_0 - s1 - onchip_memory2_0.s1 - 4194304 - 131072 - - - - - - com.altera.entityinterfaces.IConnectionPoint - nios2_gen2_0.data_master - false - true - true - true - - - java.lang.String - clk - false - true - false - true - - - java.lang.String - reset - false - true - false - true - - - java.lang.String - - false - true - false - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - INDIVIDUAL_REQUESTS - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - true - - irq - Input - 32 - irq - - - false - msgdma_0 - csr_irq - msgdma_0.csr_irq - 3 - - - false - i2c_0 - interrupt_sender - i2c_0.interrupt_sender - 4 - - - false - ext_flash - interrupt_sender - ext_flash.interrupt_sender - 6 - - - false - jtag_uart_0 - irq - jtag_uart_0.irq - 0 - - - false - timer_0 - irq - timer_0.irq - 2 - - - false - spi_0 - irq - spi_0.irq - 5 - - - false - a_16550_uart_0 - irq_sender - a_16550_uart_0.irq_sender - 1 - - - - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - - false - true - true - true - - - [Ljava.lang.String; - none - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - true - - debug_reset_request - Output - 1 - reset - - - - - - embeddedsw.configuration.hideDevice - 1 - - - qsys.ui.connect - instruction_master,data_master - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - DYNAMIC - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 2048 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - java.math.BigInteger - 0 - false - true - false - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - false - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - true - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - false - true - - - int - 1 - false - false - true - true - - - boolean - true - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - false - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - false - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - false - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - debug_mem_slave_address - Input - 9 - address - - - debug_mem_slave_byteenable - Input - 4 - byteenable - - - debug_mem_slave_debugaccess - Input - 1 - debugaccess - - - debug_mem_slave_read - Input - 1 - read - - - debug_mem_slave_readdata - Output - 32 - readdata - - - debug_mem_slave_waitrequest - Output - 1 - waitrequest - - - debug_mem_slave_write - Input - 1 - write - - - debug_mem_slave_writedata - Input - 32 - writedata - - - - - - java.lang.String - - true - true - false - true - - - int - 8 - false - true - false - true - - - int - 0 - false - false - true - true - - - boolean - false - false - true - false - true - - - int - 8 - false - true - false - true - - - int - 0 - true - true - false - true - - - boolean - false - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios_custom_instruction - true - - dummy_ci_port - Output - 1 - readra - - - - - - - embeddedsw.CMacro.BYTES_PER_PAGE - 8192 - - - embeddedsw.CMacro.READ_ONLY_MODE - 0 - - - embeddedsw.CMacro.SECTOR1_ENABLED - 1 - - - embeddedsw.CMacro.SECTOR1_END_ADDR - 32767 - - - embeddedsw.CMacro.SECTOR1_START_ADDR - 0 - - - embeddedsw.CMacro.SECTOR2_ENABLED - 1 - - - embeddedsw.CMacro.SECTOR2_END_ADDR - 65535 - - - embeddedsw.CMacro.SECTOR2_START_ADDR - 32768 - - - embeddedsw.CMacro.SECTOR3_ENABLED - 1 - - - embeddedsw.CMacro.SECTOR3_END_ADDR - 458751 - - - embeddedsw.CMacro.SECTOR3_START_ADDR - 65536 - - - embeddedsw.CMacro.SECTOR4_ENABLED - 1 - - - embeddedsw.CMacro.SECTOR4_END_ADDR - 753663 - - - embeddedsw.CMacro.SECTOR4_START_ADDR - 458752 - - - embeddedsw.CMacro.SECTOR5_ENABLED - 0 - - - embeddedsw.CMacro.SECTOR5_END_ADDR - -1 - - - embeddedsw.CMacro.SECTOR5_START_ADDR - -1 - - - embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR - SIM_DIR - - - embeddedsw.memoryInfo.FLASH_INSTALL_DIR - APP_DIR - - - embeddedsw.memoryInfo.GENERATE_DAT_SYM - 1 - - - embeddedsw.memoryInfo.GENERATE_FLASH - 1 - - - embeddedsw.memoryInfo.GENERATE_HEX - 1 - - - embeddedsw.memoryInfo.HAS_BYTE_LANE - 0 - - - embeddedsw.memoryInfo.HEX_INSTALL_DIR - QPF_DIR - - - embeddedsw.memoryInfo.IS_FLASH - 1 - - - embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH - 32 - - - embeddedsw.memoryInfo.USE_BYTE_ADDRESSING_FOR_HEX - 1 - - - postgeneration.simulation.init_file.param_name - INIT_FILENAME - - - postgeneration.simulation.init_file.type - MEM_INIT - - - java.lang.String - Parallel - false - true - true - true - - - java.lang.String - Incrementing - false - true - true - true - - - int - 8 - false - true - true - true - - - double - 116.0 - false - false - true - true - - - java.lang.String - Internal Configuration - false - false - true - true - - - java.lang.String - Single Compressed Image - false - true - true - true - - - [Ljava.lang.String; - 1,2,3,4,NA - true - false - true - true - - - [Ljava.lang.String; - Read and write,Read and write,Read and write,Read and write,Hidden - false - true - true - true - - - [Ljava.lang.String; - 0x00000 - 0x07fff,0x08000 - 0x0ffff,0x10000 - 0x6ffff,0x70000 - 0xb7fff,NA - true - false - true - true - - - [Ljava.lang.String; - UFM,UFM,UFM,UFM,CFM - true - false - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - false - true - true - - - java.lang.String - altera_onchip_flash.hex - false - false - true - true - - - java.lang.String - altera_onchip_flash.dat - false - false - true - true - - - java.lang.String - ghrd_10m50da_onchip_flash_0 - false - true - false - true - UNIQUE_ID - - - java.lang.String - - true - false - false - true - - - java.lang.String - - true - false - false - true - - - java.lang.String - MAX10FPGA - false - true - false - true - DEVICE_FAMILY - - - java.lang.String - 10M50DAF484C6GES - false - true - false - true - DEVICE - - - long - 50000000 - false - true - false - true - CLOCK_RATE - clk - - - java.lang.String - 50 - true - true - false - true - - - int - 0 - true - true - false - true - - - int - 8191 - true - true - false - true - - - int - 8192 - true - true - false - true - - - int - 16383 - true - true - false - true - - - int - 16384 - true - true - false - true - - - int - 114687 - true - true - false - true - - - int - 114688 - true - true - false - true - - - int - 188415 - true - true - false - true - - - int - 0 - true - false - false - true - - - int - 0 - true - false - false - true - - - int - 0 - true - true - false - true - - - int - 188415 - true - true - false - true - - - int - 0 - true - true - false - true - - - int - 188415 - true - true - false - true - - - int - 1 - true - true - false - true - - - int - 2 - true - true - false - true - - - int - 3 - true - true - false - true - - - int - 4 - true - true - false - true - - - int - 0 - true - true - false - true - - - int - 188415 - true - true - false - true - - - int - 2048 - true - true - false - true - - - int - 0 - true - true - false - true - - - int - 18 - true - true - false - true - - - int - 32 - true - true - false - true - - - int - 4 - true - true - false - true - - - int - 16 - true - true - false - true - - - int - 4 - true - true - false - true - - - int - 2 - true - true - false - true - - - int - 5 - true - true - false - true - - - int - 12 - true - true - false - true - - - int - 60 - true - true - false - true - - - int - 17500000 - true - true - false - true - - - int - 15250 - true - true - false - true - - - boolean - true - true - true - false - true - - - boolean - true - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - False - true - true - false - true - - - java.lang.String - True - true - true - false - true - - - java.lang.String - True - true - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 50000000 - true - true - false - true - - clock - false - - clock - Input - 1 - clk - - - - - - java.lang.String - clk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - embeddedsw.configuration.isFlash - 1 - - - embeddedsw.configuration.isMemoryDevice - 1 - - - embeddedsw.configuration.isNonVolatileStorage - 1 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - DYNAMIC - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 753664 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - nreset - false - true - true - true - - - int - 8 - false - true - true - true - - - java.math.BigInteger - - false - true - false - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 753664 - false - true - true - true - - - int - 0 - false - false - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 1 - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - false - true - true - - - int - 0 - false - true - false - true - - - int - 0 - false - false - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - false - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - false - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - false - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - avmm_data_addr - Input - 18 - address - - - avmm_data_read - Input - 1 - read - - - avmm_data_writedata - Input - 32 - writedata - - - avmm_data_write - Input - 1 - write - - - avmm_data_readdata - Output - 32 - readdata - - - avmm_data_waitrequest - Output - 1 - waitrequest - - - avmm_data_readdatavalid - Output - 1 - readdatavalid - - - avmm_data_burstcount - Input - 4 - burstcount - - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 0 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - DYNAMIC - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 8 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - nreset - false - true - true - true - - - int - 8 - false - true - true - true - - - java.math.BigInteger - - false - true - false - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - false - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - avmm_csr_addr - Input - 1 - address - - - avmm_csr_read - Input - 1 - read - - - avmm_csr_writedata - Input - 32 - writedata - - - avmm_csr_write - Input - 1 - write - - - avmm_csr_readdata - Output - 32 - readdata - - - - - - - embeddedsw.CMacro.ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR - 0 - - - embeddedsw.CMacro.ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE - 0 - - - embeddedsw.CMacro.CONTENTS_INFO - "" - - - embeddedsw.CMacro.DUAL_PORT - 0 - - - embeddedsw.CMacro.GUI_RAM_BLOCK_TYPE - AUTO - - - embeddedsw.CMacro.INIT_CONTENTS_FILE - ghrd_10m50da_onchip_memory2_0 - - - embeddedsw.CMacro.INIT_MEM_CONTENT - 0 - - - embeddedsw.CMacro.INSTANCE_ID - NONE - - - embeddedsw.CMacro.NON_DEFAULT_INIT_FILE_ENABLED - 0 - - - embeddedsw.CMacro.RAM_BLOCK_TYPE - AUTO - - - embeddedsw.CMacro.READ_DURING_WRITE_MODE - DONT_CARE - - - embeddedsw.CMacro.SINGLE_CLOCK_OP - 0 - - - embeddedsw.CMacro.SIZE_MULTIPLE - 1 - - - embeddedsw.CMacro.SIZE_VALUE - 131072 - - - embeddedsw.CMacro.WRITABLE - 1 - - - embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR - SIM_DIR - - - embeddedsw.memoryInfo.GENERATE_DAT_SYM - 1 - - - embeddedsw.memoryInfo.GENERATE_HEX - 1 - - - embeddedsw.memoryInfo.HAS_BYTE_LANE - 0 - - - embeddedsw.memoryInfo.HEX_INSTALL_DIR - QPF_DIR - - - embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH - 32 - - - embeddedsw.memoryInfo.MEM_INIT_FILENAME - ghrd_10m50da_onchip_memory2_0 - - - postgeneration.simulation.init_file.param_name - INIT_FILE - - - postgeneration.simulation.init_file.type - MEM_INIT - - - boolean - false - false - true - true - true - - - java.lang.String - AUTO - false - true - true - true - - - int - 32 - false - true - true - true - - - int - 32 - false - true - false - true - - - boolean - false - false - true - true - true - - - boolean - false - false - false - true - true - - - boolean - false - true - true - false - true - - - boolean - false - false - true - true - true - - - java.lang.String - onchip_mem.hex - false - false - true - true - - - boolean - false - false - false - true - true - - - java.lang.String - NONE - false - false - true - true - - - long - 131072 - false - true - true - true - - - java.lang.String - DONT_CARE - false - false - true - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - boolean - false - false - false - true - true - - - boolean - false - true - true - false - true - - - int - 1 - false - true - true - true - - - int - 1 - false - false - true - true - - - boolean - false - false - false - true - true - - - boolean - false - false - false - false - true - - - boolean - false - false - false - true - true - - - boolean - true - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - true - false - true - true - true - - - java.lang.String - ghrd_10m50da_onchip_memory2_0 - false - true - false - true - UNIQUE_ID - - - java.lang.String - MAX10FPGA - false - true - false - true - DEVICE_FAMILY - - - java.lang.String - ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 - false - true - false - true - DEVICE_FEATURES - - - int - 15 - true - true - false - true - - - int - 15 - true - true - false - true - - - int - 32 - true - true - false - true - - - int - 32 - true - true - false - true - - - java.lang.String - Automatic - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - ghrd_10m50da_onchip_memory2_0.hex - true - true - false - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clk - Input - 1 - clk - - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 1 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - DYNAMIC - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 131072 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk1 - false - true - true - true - - - java.lang.String - reset1 - false - true - true - true - - - int - 8 - false - true - true - true - - - java.math.BigInteger - - false - true - false - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 131072 - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - true - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 1 - false - true - true - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - address - Input - 15 - address - - - clken - Input - 1 - clken - - - chipselect - Input - 1 - chipselect - - - write - Input - 1 - write - - - readdata - Output - 32 - readdata - - - writedata - Input - 32 - writedata - - - byteenable - Input - 4 - byteenable - - - - - - java.lang.String - clk1 - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset - Input - 1 - reset - - - reset_req - Input - 1 - reset_req - - - - - - - embeddedsw.CMacro.CLOCKMULT - 1 - - - embeddedsw.CMacro.CLOCKPHASE - 1 - - - embeddedsw.CMacro.CLOCKPOLARITY - 0 - - - embeddedsw.CMacro.CLOCKUNITS - "Hz" - - - embeddedsw.CMacro.DATABITS - 8 - - - embeddedsw.CMacro.DATAWIDTH - 16 - - - embeddedsw.CMacro.DELAYMULT - "1.0E-9" - - - embeddedsw.CMacro.DELAYUNITS - "ns" - - - embeddedsw.CMacro.EXTRADELAY - 0 - - - embeddedsw.CMacro.INSERT_SYNC - 0 - - - embeddedsw.CMacro.ISMASTER - 1 - - - embeddedsw.CMacro.LSBFIRST - 0 - - - embeddedsw.CMacro.NUMSLAVES - 1 - - - embeddedsw.CMacro.PREFIX - "spi_" - - - embeddedsw.CMacro.SYNC_REG_DEPTH - 2 - - - embeddedsw.CMacro.TARGETCLOCK - 128000u - - - embeddedsw.CMacro.TARGETSSDELAY - "0.0" - - - embeddedsw.dts.compatible - altr,spi-1.0 - - - embeddedsw.dts.group - spi - - - embeddedsw.dts.name - spi - - - embeddedsw.dts.vendor - altr - - - int - 1 - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 8 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - true - false - true - true - true - - - int - 1 - false - true - true - true - - - int - 2 - false - false - true - true - - - long - 128000 - false - true - true - true - - - double - 0.0 - false - false - true - true - - - java.lang.String - 2.0 - false - true - false - true - AVALON_SPEC - - - long - 50000000 - false - true - false - true - CLOCK_RATE - clk - - - double - 127551.0 - true - true - true - true - - - double - 0.0 - true - false - true - true - - - boolean - false - true - true - false - true - - - int - 16 - true - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 50000000 - true - true - false - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - clk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 0 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - NATIVE - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 8 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - java.math.BigInteger - - false - true - false - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - true - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - false - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 1 - false - true - false - true - - - int - 1 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - data_from_cpu - Input - 16 - writedata - - - data_to_cpu - Output - 16 - readdata - - - mem_addr - Input - 3 - address - - - read_n - Input - 1 - read_n - - - spi_select - Input - 1 - chipselect - - - write_n - Input - 1 - write_n - - - - - - com.altera.entityinterfaces.IConnectionPoint - spi_0.spi_control_port - false - true - true - true - - - java.lang.String - clk - false - true - false - true - - - java.lang.String - reset - false - true - false - true - - - java.lang.Integer - - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - NONE - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - false - - irq - Output - 1 - irq - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - MISO - Input - 1 - export - - - MOSI - Output - 1 - export - - - SCLK - Output - 1 - export - - - SS_n - Output - 1 - export - - - - - - - embeddedsw.CMacro.ID - 0 - - - embeddedsw.CMacro.TIMESTAMP - 1512455752 - - - embeddedsw.dts.compatible - altr,sysid-1.0 - - - embeddedsw.dts.group - sysid - - - embeddedsw.dts.name - sysid - - - embeddedsw.dts.params.id - 0 - - - embeddedsw.dts.params.timestamp - 1512455752 - - - embeddedsw.dts.vendor - altr - - - int - 0 - false - true - true - true - - - int - 1512455752 - true - false - false - true - GENERATION_ID - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clock - Input - 1 - clk - - - - - - java.lang.String - clk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - embeddedsw.configuration.isMemoryDevice - false - - - embeddedsw.configuration.isNonVolatileStorage - false - - - embeddedsw.configuration.isPrintableDevice - false - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - DYNAMIC - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 8 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - java.math.BigInteger - - false - true - false - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - true - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - false - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - readdata - Output - 32 - readdata - - - address - Input - 1 - address - - - - - - - embeddedsw.CMacro.ALWAYS_RUN - 0 - - - embeddedsw.CMacro.COUNTER_SIZE - 32 - - - embeddedsw.CMacro.FIXED_PERIOD - 0 - - - embeddedsw.CMacro.FREQ - 50000000 - - - embeddedsw.CMacro.LOAD_VALUE - 49999 - - - embeddedsw.CMacro.MULT - 0.001 - - - embeddedsw.CMacro.PERIOD - 1 - - - embeddedsw.CMacro.PERIOD_UNITS - ms - - - embeddedsw.CMacro.RESET_OUTPUT - 0 - - - embeddedsw.CMacro.SNAPSHOT - 1 - - - embeddedsw.CMacro.TICKS_PER_SEC - 1000 - - - embeddedsw.CMacro.TIMEOUT_PULSE_OUTPUT - 0 - - - embeddedsw.dts.compatible - altr,timer-1.0 - - - embeddedsw.dts.group - timer - - - embeddedsw.dts.name - timer - - - embeddedsw.dts.params.clock-frequency - 50000000 - - - embeddedsw.dts.vendor - altr - - - boolean - false - false - true - true - true - - - int - 32 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - 1 - false - true - true - true - - - java.lang.String - MSEC - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - true - false - true - true - true - - - boolean - false - false - true - true - true - - - long - 50000000 - false - true - false - true - CLOCK_RATE - clk - - - int - 2 - false - true - false - true - - - java.lang.String - FULL_FEATURED - true - true - false - true - - - java.lang.String - ms - true - true - false - true - - - double - 0.001 - true - true - false - true - - - java.lang.String - 49999 - true - true - false - true - - - double - 0.001 - true - true - false - true - - - double - 1000.0 - true - true - false - true - - - int - 3 - true - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 50000000 - true - true - false - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - clk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 0 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - embeddedsw.configuration.isTimerDevice - 1 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - NATIVE - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 8 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - java.math.BigInteger - - false - true - false - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - true - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - false - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - address - Input - 3 - address - - - writedata - Input - 16 - writedata - - - readdata - Output - 16 - readdata - - - chipselect - Input - 1 - chipselect - - - write_n - Input - 1 - write_n - - - - - - com.altera.entityinterfaces.IConnectionPoint - timer_0.s1 - false - true - true - true - - - java.lang.String - clk - false - true - false - true - - - java.lang.String - reset - false - true - false - true - - - java.lang.Integer - - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - true - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - NONE - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - false - - irq - Output - 1 - irq - - - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x00201000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_gen2_0 - data_master - jtag_uart_0 - avalon_jtag_slave - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x00100000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_gen2_0 - data_master - a_16550_uart_0 - avalon_slave - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x00100240 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_gen2_0 - data_master - ext_flash - avl_csr - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x08000000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_gen2_0 - data_master - ext_flash - avl_mem - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x00100300 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_gen2_0 - data_master - sysid - control_slave - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x001002c0 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_gen2_0 - data_master - msgdma_0 - csr - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x00100200 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_gen2_0 - data_master - i2c_0 - csr - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x00200000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_gen2_0 - data_master - onchip_flash_0 - csr - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x0000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_gen2_0 - data_master - onchip_flash_0 - data - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x00200800 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_gen2_0 - data_master - nios2_gen2_0 - debug_mem_slave - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x001002f0 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_gen2_0 - data_master - msgdma_0 - descriptor_slave - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x00400000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_gen2_0 - data_master - onchip_memory2_0 - s1 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x001002a0 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_gen2_0 - data_master - timer_0 - s1 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x001002e0 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_gen2_0 - data_master - led - s1 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x00100280 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_gen2_0 - data_master - spi_0 - spi_control_port - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x08000000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_gen2_0 - instruction_master - ext_flash - avl_mem - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x0000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_gen2_0 - instruction_master - onchip_flash_0 - data - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x00200800 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_gen2_0 - instruction_master - nios2_gen2_0 - debug_mem_slave - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x00400000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_gen2_0 - instruction_master - onchip_memory2_0 - s1 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x00400000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - msgdma_0 - mm_read - onchip_memory2_0 - s1 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x00400000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - msgdma_0 - mm_write - onchip_memory2_0 - s1 - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - altpll_0 - c0 - ext_flash - clock_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk - nios2_gen2_0 - clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk - jtag_uart_0 - clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk - timer_0 - clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk - spi_0 - clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk - led - clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk - sysid - clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk - onchip_flash_0 - clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk - onchip_memory2_0 - clk1 - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk - a_16550_uart_0 - clock - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk - msgdma_0 - clock - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk - i2c_0 - clock - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk - altpll_0 - inclk_interface - - - - int - 3 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_gen2_0 - irq - msgdma_0 - csr_irq - - - - int - 4 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_gen2_0 - irq - i2c_0 - interrupt_sender - - - - int - 6 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_gen2_0 - irq - ext_flash - interrupt_sender - - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_gen2_0 - irq - jtag_uart_0 - irq - - - - int - 2 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_gen2_0 - irq - timer_0 - irq - - - - int - 5 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_gen2_0 - irq - spi_0 - irq - - - - int - 1 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_gen2_0 - irq - a_16550_uart_0 - irq_sender - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk_reset - altpll_0 - inclk_interface_reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk_reset - onchip_flash_0 - nreset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk_reset - nios2_gen2_0 - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk_reset - jtag_uart_0 - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk_reset - timer_0 - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk_reset - spi_0 - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk_reset - ext_flash - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk_reset - led - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk_reset - sysid - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk_reset - onchip_memory2_0 - reset1 - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk_reset - msgdma_0 - reset_n - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk_reset - a_16550_uart_0 - reset_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk_reset - i2c_0 - reset_sink - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_gen2_0 - debug_reset_request - nios2_gen2_0 - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_gen2_0 - debug_reset_request - jtag_uart_0 - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_gen2_0 - debug_reset_request - spi_0 - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_gen2_0 - debug_reset_request - ext_flash - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_gen2_0 - debug_reset_request - led - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_gen2_0 - debug_reset_request - onchip_memory2_0 - reset1 - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_gen2_0 - debug_reset_request - msgdma_0 - reset_n - - - 1 - altera_16550_uart - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Altera 16550 Compatible UART - 17.0 - - - 16 - avalon_slave - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Avalon Memory Mapped Slave - 17.0 - - - 13 - clock_sink - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Clock Input - 17.0 - - - 13 - reset_sink - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Reset Input - 17.0 - - - 7 - interrupt_sender - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Interrupt Sender - 17.0 - - - 6 - conduit_end - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Conduit - 17.0 - - - 1 - altpll - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Avalon ALTPLL - 17.0 - - - 1 - clock_source - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Clock Output - 17.0 - - - 1 - clock_source - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Clock Source - 17.0 - - - 1 - clock_sink - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Clock Input - 17.0 - - - 1 - reset_sink - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Reset Input - 17.0 - - - 1 - clock_source - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Clock Output - 17.0 - - - 1 - reset_source - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Reset Output - 17.0 - - - 1 - altera_generic_quad_spi_controller2 - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Altera Generic QUAD SPI controller II - 17.0 - - - 1 - altera_avalon_i2c - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Altera Avalon I2C (Master) - 17.0 - - - 1 - altera_avalon_jtag_uart - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - JTAG UART - 17.0 - - - 1 - altera_avalon_pio - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - PIO (Parallel I/O) - 17.0 - - - 1 - altera_msgdma - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Modular Scatter-Gather DMA - 17.0 - - - 4 - avalon_master - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Avalon Memory Mapped Master - 17.0 - - - 1 - altera_nios2_gen2 - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Nios II Processor - 17.0 - - - 1 - interrupt_receiver - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Interrupt Receiver - 17.0 - - - 1 - reset_source - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Reset Output - 17.0 - - - 1 - nios_custom_instruction_master - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Custom Instruction Master - 17.0 - - - 1 - altera_onchip_flash - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Altera On-Chip Flash - 17.0 - - - 1 - altera_avalon_onchip_memory2 - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - On-Chip Memory (RAM or ROM) - 17.0 - - - 1 - altera_avalon_spi - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - SPI (3 Wire Serial) - 17.0 - - - 1 - altera_avalon_sysid_qsys - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - System ID Peripheral - 17.0 - - - 1 - altera_avalon_timer - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Interval Timer - 17.0 - - - 21 - avalon - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IConnection - Avalon Memory Mapped Connection - 17.0 - - - 13 - clock - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IConnection - Clock Connection - 17.0 - - - 7 - interrupt - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IConnection - Interrupt Connection - 17.0 - - - 20 - reset - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IConnection - Reset Connection - 17.0 - - 17.0 595 - - diff --git a/soc/altr/zephyr_nios2f/cpu/ghrd_10m50da_top.v b/soc/altr/zephyr_nios2f/cpu/ghrd_10m50da_top.v deleted file mode 100644 index 846659543a4..00000000000 --- a/soc/altr/zephyr_nios2f/cpu/ghrd_10m50da_top.v +++ /dev/null @@ -1,121 +0,0 @@ -module ghrd_10m50da_top ( - //Clock and Reset - input wire clk_50, - //input wire clk_ddr3_100_p, - input wire fpga_reset_n, - //QSPI - output wire qspi_clk, - inout wire[3:0] qspi_io, - output wire qspi_csn, - //ddr3 - //output wire [13:0] mem_a, - //output wire [2:0] mem_ba, - //inout wire [0:0] mem_ck, - //inout wire [0:0] mem_ck_n, - //output wire [0:0] mem_cke, - //output wire [0:0] mem_cs_n, - //output wire [0:0] mem_dm, - //output wire [0:0] mem_ras_n, - //output wire [0:0] mem_cas_n, - //output wire [0:0] mem_we_n, - //output wire mem_reset_n, - ///inout wire [7:0] mem_dq, - //inout wire [0:0] mem_dqs, - //inout wire [0:0] mem_dqs_n, - //output wire [0:0] mem_odt, - //i2c - inout wire i2c_sda, - inout wire i2c_scl, - //spi - input wire spi_miso, - output wire spi_mosi, - output wire spi_sclk, - output wire spi_ssn, - //16550 UART - input wire uart_rx, - output wire uart_tx, - output wire [4:0] user_led -); -//Heart-beat counter -reg [25:0] heart_beat_cnt; - -//DDR3 interface assignments -//wire local_init_done; -//wire local_cal_success; -//wire local_cal_fail; - -//i2c interface -wire i2c_serial_sda_in ; -wire i2c_serial_scl_in ; -wire i2c_serial_sda_oe ; -wire i2c_serial_scl_oe ; -assign i2c_serial_scl_in = i2c_scl; -assign i2c_scl = i2c_serial_scl_oe ? 1'b0 : 1'bz; - -assign i2c_serial_sda_in = i2c_sda; -assign i2c_sda = i2c_serial_sda_oe ? 1'b0 : 1'bz; - -//assign system_resetn = fpga_reset_n & local_init_done; - -// SoC sub-system module -ghrd_10m50da ghrd_10m50da_inst ( - .clk_clk (clk_50), - //.ref_clock_bridge_in_clk_clk (clk_ddr3_100_p), - .reset_reset_n (fpga_reset_n), - //.mem_resetn_in_reset_reset_n (fpga_reset_n ), // mem_resetn_in_reset.reset_n - .ext_flash_qspi_pins_data (qspi_io), - .ext_flash_qspi_pins_dclk (qspi_clk), - .ext_flash_qspi_pins_ncs (qspi_csn), - //.memory_mem_a (mem_a[12:0] ), // memory.mem_a - //.memory_mem_ba (mem_ba ), // .mem_ba - //.memory_mem_ck (mem_ck ), // .mem_ck - //.memory_mem_ck_n (mem_ck_n ), // .mem_ck_n - //.memory_mem_cke (mem_cke ), // .mem_cke - //.memory_mem_cs_n (mem_cs_n ), // .mem_cs_n - //.memory_mem_dm (mem_dm ), // .mem_dm - //.memory_mem_ras_n (mem_ras_n ), // .mem_ras_n - //.memory_mem_cas_n (mem_cas_n ), // .mem_cas_n - //.memory_mem_we_n (mem_we_n ), // .mem_we_n - //.memory_mem_reset_n (mem_reset_n ), // .mem_reset_n - //.memory_mem_dq (mem_dq ), // .mem_dq - //.memory_mem_dqs (mem_dqs ), // .mem_dqs - //.memory_mem_dqs_n (mem_dqs_n ), // .mem_dqs_n - //.memory_mem_odt (mem_odt ), // .mem_odt - //.mem_if_ddr3_emif_0_status_local_init_done (local_init_done ), // mem_if_ddr3_emif_0_status.local_init_done - //.mem_if_ddr3_emif_0_status_local_cal_success (local_cal_success ), // .local_cal_success - //.mem_if_ddr3_emif_0_status_local_cal_fail (local_cal_fail ), // .local_cal_fail - //i2c - .i2c_0_i2c_serial_sda_in (i2c_serial_sda_in), - .i2c_0_i2c_serial_scl_in (i2c_serial_scl_in), - .i2c_0_i2c_serial_sda_oe (i2c_serial_sda_oe), - .i2c_0_i2c_serial_scl_oe (i2c_serial_scl_oe), - //spi - .spi_0_external_MISO (spi_miso), // spi_0_external.MISO - .spi_0_external_MOSI (spi_mosi), // .MOSI - .spi_0_external_SCLK (spi_sclk), // .SCLK - .spi_0_external_SS_n (spi_ssn), // .SS_n - //pio - .led_external_connection_export (user_led[3:0]), - //16550 UART - .a_16550_uart_0_rs_232_serial_sin (uart_rx), // a_16550_uart_0_rs_232_serial.sin - .a_16550_uart_0_rs_232_serial_sout (uart_tx), // .sout - .a_16550_uart_0_rs_232_serial_sout_oe () // .sout_oe - -); - -//DDR3 Address Bit #13 is not available for DDR3 SDRAM A (64Mx16) -//assign mem_a[13] = 1'b0; - -//Heart beat by 50MHz clock -always @(posedge clk_50 or negedge fpga_reset_n) - if (!fpga_reset_n) - heart_beat_cnt <= 26'h0; //0x3FFFFFF - else - heart_beat_cnt <= heart_beat_cnt + 1'b1; - -assign user_led[4] = heart_beat_cnt[25]; - - -endmodule - - diff --git a/soc/altr/zephyr_nios2f/cpu/ghrd_timing.sdc b/soc/altr/zephyr_nios2f/cpu/ghrd_timing.sdc deleted file mode 100644 index 5f962e7c58e..00000000000 --- a/soc/altr/zephyr_nios2f/cpu/ghrd_timing.sdc +++ /dev/null @@ -1,28 +0,0 @@ -#************************************************************** -# Create Clock -#************************************************************** - -derive_pll_clocks - -# JTAG Signal Constraints constrain the TCK port, assuming a 10MHz JTAG clock and 3ns delays -create_clock -name {altera_reserved_tck} -period 41.667 [get_ports { altera_reserved_tck }] -set_input_delay -clock altera_reserved_tck -clock_fall -max 5 [get_ports altera_reserved_tdi] -set_input_delay -clock altera_reserved_tck -clock_fall -max 5 [get_ports altera_reserved_tms] -set_output_delay -clock altera_reserved_tck 5 [get_ports altera_reserved_tdo] - -create_clock -name {clk_50} -period 20.000 {clk_50} - -set_false_path -to [get_ports {user_led[*]}] -set_false_path -to [get_ports {fpga_reset_n}] -set_false_path -from [get_ports {fpga_reset_n}] - -derive_clock_uncertainty - -# QSPI interface -set_output_delay -clock {clk_50 } -rise -min 11 [get_ports {qspi_io[*]}] -set_output_delay -clock {clk_50 } -rise -min 11 [get_ports {qspi_clk}] -set_output_delay -clock {clk_50 } -rise -min 11 [get_ports {qspi_csn}] -set_input_delay -clock {clk_50 } -rise -min 10 [get_ports {qspi_io[*]}] - -# UART -set_false_path -from * -to [get_ports {uart_tx}] diff --git a/soc/altr/zephyr_nios2f/include/layout.h b/soc/altr/zephyr_nios2f/include/layout.h deleted file mode 100644 index d8c702967c4..00000000000 --- a/soc/altr/zephyr_nios2f/include/layout.h +++ /dev/null @@ -1,10 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -#define _RESET_VECTOR ALT_CPU_RESET_ADDR -#define _EXC_VECTOR ALT_CPU_EXCEPTION_ADDR diff --git a/soc/altr/zephyr_nios2f/include/linker.h b/soc/altr/zephyr_nios2f/include/linker.h deleted file mode 100644 index 3a3c5617945..00000000000 --- a/soc/altr/zephyr_nios2f/include/linker.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - * linker.h - Linker script mapping information - * - * Machine generated for CPU 'nios2_gen2_0' in SOPC Builder design 'ghrd_10m50da' - * SOPC Builder design path: ../../ghrd_10m50da.sopcinfo - * - * Generated: Tue Dec 05 14:42:02 SGT 2017 - */ - -/* - * DO NOT MODIFY THIS FILE - * - * Changing this file will have subtle consequences - * which will almost certainly lead to a nonfunctioning - * system. If you do modify this file, be aware that your - * changes will be overwritten and lost when this file - * is generated again. - * - * DO NOT MODIFY THIS FILE - */ - -/* - * License Agreement - * - * Copyright (c) 2008 - * Altera Corporation, San Jose, California, USA. - * All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * This agreement shall be governed in all respects by the laws of the State - * of California and by the laws of the United States of America. - */ - -#ifndef __LINKER_H_ -#define __LINKER_H_ - - -/* - * BSP controls alt_load() behavior in crt0. - * - */ - -#define ALT_LOAD_EXPLICITLY_CONTROLLED - - -/* - * Base address and span (size in bytes) of each linker region - * - */ - -#define EXT_FLASH_AVL_MEM_REGION_BASE 0x8000000 -#define EXT_FLASH_AVL_MEM_REGION_SPAN 67108864 -#define ONCHIP_FLASH_0_DATA_REGION_BASE 0x20 -#define ONCHIP_FLASH_0_DATA_REGION_SPAN 753632 -#define ONCHIP_MEMORY2_0_BEFORE_EXCEPTION_REGION_BASE 0x400000 -#define ONCHIP_MEMORY2_0_BEFORE_EXCEPTION_REGION_SPAN 32 -#define ONCHIP_MEMORY2_0_REGION_BASE 0x400020 -#define ONCHIP_MEMORY2_0_REGION_SPAN 131040 -#define RESET_REGION_BASE 0x0 -#define RESET_REGION_SPAN 32 - - -/* - * Devices associated with code sections - * - */ - -#define ALT_EXCEPTIONS_DEVICE ONCHIP_MEMORY2_0 -#define ALT_RESET_DEVICE ONCHIP_FLASH_0_DATA -#define ALT_RODATA_DEVICE ONCHIP_MEMORY2_0 -#define ALT_RWDATA_DEVICE ONCHIP_MEMORY2_0 -#define ALT_TEXT_DEVICE ONCHIP_FLASH_0_DATA - - -/* - * Initialization code at the reset address is allowed (e.g. no external bootloader). - * - */ - -#define ALT_ALLOW_CODE_AT_RESET - - -/* - * The alt_load() facility is called from crt0 to copy sections into RAM. - * - */ - -#define ALT_LOAD_COPY_EXCEPTIONS -#define ALT_LOAD_COPY_RODATA -#define ALT_LOAD_COPY_RWDATA - -#endif /* __LINKER_H_ */ diff --git a/soc/altr/zephyr_nios2f/include/system.h b/soc/altr/zephyr_nios2f/include/system.h deleted file mode 100644 index 02f83fcf0fb..00000000000 --- a/soc/altr/zephyr_nios2f/include/system.h +++ /dev/null @@ -1,567 +0,0 @@ -/* - * system.h - SOPC Builder system and BSP software package information - * - * Machine generated for CPU 'nios2_gen2_0' in SOPC Builder design 'ghrd_10m50da' - * SOPC Builder design path: ../../ghrd_10m50da.sopcinfo - * - * Generated: Tue Dec 05 14:41:17 SGT 2017 - */ - -/* - * DO NOT MODIFY THIS FILE - * - * Changing this file will have subtle consequences - * which will almost certainly lead to a nonfunctioning - * system. If you do modify this file, be aware that your - * changes will be overwritten and lost when this file - * is generated again. - * - * DO NOT MODIFY THIS FILE - */ - -/* - * License Agreement - * - * Copyright (c) 2008 - * Altera Corporation, San Jose, California, USA. - * All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * This agreement shall be governed in all respects by the laws of the State - * of California and by the laws of the United States of America. - */ - -#ifndef __SYSTEM_H_ -#define __SYSTEM_H_ - -/* Include definitions from linker script generator */ -#include "linker.h" - - -/* - * CPU configuration - * - */ - -#define ALT_CPU_ARCHITECTURE "altera_nios2_gen2" -#define ALT_CPU_BIG_ENDIAN 0 -#define ALT_CPU_BREAK_ADDR 0x00200820 -#define ALT_CPU_CPU_ARCH_NIOS2_R1 -#define ALT_CPU_CPU_FREQ 50000000u -#define ALT_CPU_CPU_ID_SIZE 1 -#define ALT_CPU_CPU_ID_VALUE 0x00000000 -#define ALT_CPU_CPU_IMPLEMENTATION "fast" -#define ALT_CPU_DATA_ADDR_WIDTH 0x1c -#define ALT_CPU_DCACHE_BYPASS_MASK 0x80000000 -#define ALT_CPU_DCACHE_LINE_SIZE 32 -#define ALT_CPU_DCACHE_LINE_SIZE_LOG2 5 -#define ALT_CPU_DCACHE_SIZE 2048 -#define ALT_CPU_EXCEPTION_ADDR 0x00400020 -#define ALT_CPU_FLASH_ACCELERATOR_LINES 0 -#define ALT_CPU_FLASH_ACCELERATOR_LINE_SIZE 0 -#define ALT_CPU_FLUSHDA_SUPPORTED -#define ALT_CPU_FREQ 50000000 -#define ALT_CPU_HARDWARE_DIVIDE_PRESENT 1 -#define ALT_CPU_HARDWARE_MULTIPLY_PRESENT 1 -#define ALT_CPU_HARDWARE_MULX_PRESENT 0 -#define ALT_CPU_HAS_DEBUG_CORE 1 -#define ALT_CPU_HAS_DEBUG_STUB -#define ALT_CPU_HAS_DIVISION_ERROR_EXCEPTION -#define ALT_CPU_HAS_EXTRA_EXCEPTION_INFO -#define ALT_CPU_HAS_ILLEGAL_INSTRUCTION_EXCEPTION -#define ALT_CPU_HAS_JMPI_INSTRUCTION -#define ALT_CPU_ICACHE_LINE_SIZE 32 -#define ALT_CPU_ICACHE_LINE_SIZE_LOG2 5 -#define ALT_CPU_ICACHE_SIZE 4096 -#define ALT_CPU_INITDA_SUPPORTED -#define ALT_CPU_INST_ADDR_WIDTH 0x1c -#define ALT_CPU_NAME "nios2_gen2_0" -#define ALT_CPU_NUM_OF_SHADOW_REG_SETS 0 -#define ALT_CPU_OCI_VERSION 1 -#define ALT_CPU_RESET_ADDR 0x00000000 - - -/* - * CPU configuration (with legacy prefix - don't use these anymore) - * - */ - -#define NIOS2_BIG_ENDIAN 0 -#define NIOS2_BREAK_ADDR 0x00200820 -#define NIOS2_CPU_ARCH_NIOS2_R1 -#define NIOS2_CPU_FREQ 50000000u -#define NIOS2_CPU_ID_SIZE 1 -#define NIOS2_CPU_ID_VALUE 0x00000000 -#define NIOS2_CPU_IMPLEMENTATION "fast" -#define NIOS2_DATA_ADDR_WIDTH 0x1c -#define NIOS2_DCACHE_BYPASS_MASK 0x80000000 -#define NIOS2_DCACHE_LINE_SIZE 32 -#define NIOS2_DCACHE_LINE_SIZE_LOG2 5 -#define NIOS2_DCACHE_SIZE 2048 -#define NIOS2_EXCEPTION_ADDR 0x00400020 -#define NIOS2_FLASH_ACCELERATOR_LINES 0 -#define NIOS2_FLASH_ACCELERATOR_LINE_SIZE 0 -#define NIOS2_FLUSHDA_SUPPORTED -#define NIOS2_HARDWARE_DIVIDE_PRESENT 1 -#define NIOS2_HARDWARE_MULTIPLY_PRESENT 1 -#define NIOS2_HARDWARE_MULX_PRESENT 0 -#define NIOS2_HAS_DEBUG_CORE 1 -#define NIOS2_HAS_DEBUG_STUB -#define NIOS2_HAS_DIVISION_ERROR_EXCEPTION -#define NIOS2_HAS_EXTRA_EXCEPTION_INFO -#define NIOS2_HAS_ILLEGAL_INSTRUCTION_EXCEPTION -#define NIOS2_HAS_JMPI_INSTRUCTION -#define NIOS2_ICACHE_LINE_SIZE 32 -#define NIOS2_ICACHE_LINE_SIZE_LOG2 5 -#define NIOS2_ICACHE_SIZE 4096 -#define NIOS2_INITDA_SUPPORTED -#define NIOS2_INST_ADDR_WIDTH 0x1c -#define NIOS2_NUM_OF_SHADOW_REG_SETS 0 -#define NIOS2_OCI_VERSION 1 -#define NIOS2_RESET_ADDR 0x00000000 - - -/* - * Define for each module class mastered by the CPU - * - */ - -#define __ALTERA_16550_UART -#define __ALTERA_AVALON_I2C -#define __ALTERA_AVALON_JTAG_UART -#define __ALTERA_AVALON_ONCHIP_MEMORY2 -#define __ALTERA_AVALON_PIO -#define __ALTERA_AVALON_SPI -#define __ALTERA_AVALON_SYSID_QSYS -#define __ALTERA_AVALON_TIMER -#define __ALTERA_GENERIC_QUAD_SPI_CONTROLLER2 -#define __ALTERA_MSGDMA -#define __ALTERA_NIOS2_GEN2 -#define __ALTERA_ONCHIP_FLASH - - -/* - * System configuration - * - */ - -#define ALT_DEVICE_FAMILY "MAX 10" -#define ALT_ENHANCED_INTERRUPT_API_PRESENT -#define ALT_IRQ_BASE NULL -#define ALT_LOG_PORT "/dev/null" -#define ALT_LOG_PORT_BASE 0x0 -#define ALT_LOG_PORT_DEV null -#define ALT_LOG_PORT_TYPE "" -#define ALT_NUM_EXTERNAL_INTERRUPT_CONTROLLERS 0 -#define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1 -#define ALT_NUM_INTERRUPT_CONTROLLERS 1 -#define ALT_STDERR "/dev/jtag_uart_0" -#define ALT_STDERR_BASE 0x201000 -#define ALT_STDERR_DEV jtag_uart_0 -#define ALT_STDERR_IS_JTAG_UART -#define ALT_STDERR_PRESENT -#define ALT_STDERR_TYPE "altera_avalon_jtag_uart" -#define ALT_STDIN "/dev/jtag_uart_0" -#define ALT_STDIN_BASE 0x201000 -#define ALT_STDIN_DEV jtag_uart_0 -#define ALT_STDIN_IS_JTAG_UART -#define ALT_STDIN_PRESENT -#define ALT_STDIN_TYPE "altera_avalon_jtag_uart" -#define ALT_STDOUT "/dev/jtag_uart_0" -#define ALT_STDOUT_BASE 0x201000 -#define ALT_STDOUT_DEV jtag_uart_0 -#define ALT_STDOUT_IS_JTAG_UART -#define ALT_STDOUT_PRESENT -#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart" -#define ALT_SYSTEM_NAME "ghrd_10m50da" - - -/* - * a_16550_uart_0 configuration - * - */ - -#define ALT_MODULE_CLASS_a_16550_uart_0 altera_16550_uart -#define A_16550_UART_0_BASE 0x100000 -#define A_16550_UART_0_FIFO_DEPTH 64 -#define A_16550_UART_0_FIFO_MODE 1 -#define A_16550_UART_0_FIO_HWFC 0 -#define A_16550_UART_0_FIO_SWFC 0 -#define A_16550_UART_0_FREQ 50000000 -#define A_16550_UART_0_IRQ 1 -#define A_16550_UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0 -#define A_16550_UART_0_NAME "/dev/a_16550_uart_0" -#define A_16550_UART_0_SPAN 512 -#define A_16550_UART_0_TYPE "altera_16550_uart" - - -/* - * ext_flash_avl_csr configuration - * - */ - -#define ALT_MODULE_CLASS_ext_flash_avl_csr altera_generic_quad_spi_controller2 -#define EXT_FLASH_AVL_CSR_BASE 0x100240 -#define EXT_FLASH_AVL_CSR_FLASH_TYPE "Micron512" -#define EXT_FLASH_AVL_CSR_IRQ 6 -#define EXT_FLASH_AVL_CSR_IRQ_INTERRUPT_CONTROLLER_ID 0 -#define EXT_FLASH_AVL_CSR_IS_EPCS 0 -#define EXT_FLASH_AVL_CSR_NAME "/dev/ext_flash_avl_csr" -#define EXT_FLASH_AVL_CSR_NUMBER_OF_SECTORS 1024 -#define EXT_FLASH_AVL_CSR_PAGE_SIZE 256 -#define EXT_FLASH_AVL_CSR_SECTOR_SIZE 65536 -#define EXT_FLASH_AVL_CSR_SPAN 64 -#define EXT_FLASH_AVL_CSR_SUBSECTOR_SIZE 4096 -#define EXT_FLASH_AVL_CSR_TYPE "altera_generic_quad_spi_controller2" - - -/* - * ext_flash_avl_mem configuration - * - */ - -#define ALT_MODULE_CLASS_ext_flash_avl_mem altera_generic_quad_spi_controller2 -#define EXT_FLASH_AVL_MEM_BASE 0x8000000 -#define EXT_FLASH_AVL_MEM_FLASH_TYPE "Micron512" -#define EXT_FLASH_AVL_MEM_IRQ -1 -#define EXT_FLASH_AVL_MEM_IRQ_INTERRUPT_CONTROLLER_ID -1 -#define EXT_FLASH_AVL_MEM_IS_EPCS 0 -#define EXT_FLASH_AVL_MEM_NAME "/dev/ext_flash_avl_mem" -#define EXT_FLASH_AVL_MEM_NUMBER_OF_SECTORS 1024 -#define EXT_FLASH_AVL_MEM_PAGE_SIZE 256 -#define EXT_FLASH_AVL_MEM_SECTOR_SIZE 65536 -#define EXT_FLASH_AVL_MEM_SPAN 67108864 -#define EXT_FLASH_AVL_MEM_SUBSECTOR_SIZE 4096 -#define EXT_FLASH_AVL_MEM_TYPE "altera_generic_quad_spi_controller2" - - -/* - * hal configuration - * - */ - -#define ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API -#define ALT_MAX_FD 32 -#define ALT_SYS_CLK TIMER_0 -#define ALT_TIMESTAMP_CLK none - - -/* - * i2c_0 configuration - * - */ - -#define ALT_MODULE_CLASS_i2c_0 altera_avalon_i2c -#define I2C_0_BASE 0x100200 -#define I2C_0_FIFO_DEPTH 16 -#define I2C_0_FREQ 50000000 -#define I2C_0_IRQ 4 -#define I2C_0_IRQ_INTERRUPT_CONTROLLER_ID 0 -#define I2C_0_NAME "/dev/i2c_0" -#define I2C_0_SPAN 64 -#define I2C_0_TYPE "altera_avalon_i2c" -#define I2C_0_USE_AV_ST 0 - - -/* - * jtag_uart_0 configuration - * - */ - -#define ALT_MODULE_CLASS_jtag_uart_0 altera_avalon_jtag_uart -#define JTAG_UART_0_BASE 0x201000 -#define JTAG_UART_0_IRQ 0 -#define JTAG_UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0 -#define JTAG_UART_0_NAME "/dev/jtag_uart_0" -#define JTAG_UART_0_READ_DEPTH 64 -#define JTAG_UART_0_READ_THRESHOLD 8 -#define JTAG_UART_0_SPAN 8 -#define JTAG_UART_0_TYPE "altera_avalon_jtag_uart" -#define JTAG_UART_0_WRITE_DEPTH 64 -#define JTAG_UART_0_WRITE_THRESHOLD 8 - - -/* - * led configuration - * - */ - -#define ALT_MODULE_CLASS_led altera_avalon_pio -#define LED_BASE 0x1002e0 -#define LED_BIT_CLEARING_EDGE_REGISTER 0 -#define LED_BIT_MODIFYING_OUTPUT_REGISTER 0 -#define LED_CAPTURE 0 -#define LED_DATA_WIDTH 4 -#define LED_DO_TEST_BENCH_WIRING 0 -#define LED_DRIVEN_SIM_VALUE 0 -#define LED_EDGE_TYPE "NONE" -#define LED_FREQ 50000000 -#define LED_HAS_IN 0 -#define LED_HAS_OUT 1 -#define LED_HAS_TRI 0 -#define LED_IRQ -1 -#define LED_IRQ_INTERRUPT_CONTROLLER_ID -1 -#define LED_IRQ_TYPE "NONE" -#define LED_NAME "/dev/led" -#define LED_RESET_VALUE 0 -#define LED_SPAN 16 -#define LED_TYPE "altera_avalon_pio" - - -/* - * msgdma_0_csr configuration - * - */ - -#define ALT_MODULE_CLASS_msgdma_0_csr altera_msgdma -#define MSGDMA_0_CSR_BASE 0x1002c0 -#define MSGDMA_0_CSR_BURST_ENABLE 1 -#define MSGDMA_0_CSR_BURST_WRAPPING_SUPPORT 1 -#define MSGDMA_0_CSR_CHANNEL_ENABLE 0 -#define MSGDMA_0_CSR_CHANNEL_ENABLE_DERIVED 0 -#define MSGDMA_0_CSR_CHANNEL_WIDTH 8 -#define MSGDMA_0_CSR_DATA_FIFO_DEPTH 32 -#define MSGDMA_0_CSR_DATA_WIDTH 32 -#define MSGDMA_0_CSR_DESCRIPTOR_FIFO_DEPTH 128 -#define MSGDMA_0_CSR_DMA_MODE 0 -#define MSGDMA_0_CSR_ENHANCED_FEATURES 0 -#define MSGDMA_0_CSR_ERROR_ENABLE 0 -#define MSGDMA_0_CSR_ERROR_ENABLE_DERIVED 0 -#define MSGDMA_0_CSR_ERROR_WIDTH 8 -#define MSGDMA_0_CSR_IRQ 3 -#define MSGDMA_0_CSR_IRQ_INTERRUPT_CONTROLLER_ID 0 -#define MSGDMA_0_CSR_MAX_BURST_COUNT 2 -#define MSGDMA_0_CSR_MAX_BYTE 1024 -#define MSGDMA_0_CSR_MAX_STRIDE 1 -#define MSGDMA_0_CSR_NAME "/dev/msgdma_0_csr" -#define MSGDMA_0_CSR_PACKET_ENABLE 0 -#define MSGDMA_0_CSR_PACKET_ENABLE_DERIVED 0 -#define MSGDMA_0_CSR_PREFETCHER_ENABLE 0 -#define MSGDMA_0_CSR_PROGRAMMABLE_BURST_ENABLE 0 -#define MSGDMA_0_CSR_RESPONSE_PORT 2 -#define MSGDMA_0_CSR_SPAN 32 -#define MSGDMA_0_CSR_STRIDE_ENABLE 0 -#define MSGDMA_0_CSR_STRIDE_ENABLE_DERIVED 0 -#define MSGDMA_0_CSR_TRANSFER_TYPE "Aligned Accesses" -#define MSGDMA_0_CSR_TYPE "altera_msgdma" - - -/* - * msgdma_0_descriptor_slave configuration - * - */ - -#define ALT_MODULE_CLASS_msgdma_0_descriptor_slave altera_msgdma -#define MSGDMA_0_DESCRIPTOR_SLAVE_BASE 0x1002f0 -#define MSGDMA_0_DESCRIPTOR_SLAVE_BURST_ENABLE 1 -#define MSGDMA_0_DESCRIPTOR_SLAVE_BURST_WRAPPING_SUPPORT 1 -#define MSGDMA_0_DESCRIPTOR_SLAVE_CHANNEL_ENABLE 0 -#define MSGDMA_0_DESCRIPTOR_SLAVE_CHANNEL_ENABLE_DERIVED 0 -#define MSGDMA_0_DESCRIPTOR_SLAVE_CHANNEL_WIDTH 8 -#define MSGDMA_0_DESCRIPTOR_SLAVE_DATA_FIFO_DEPTH 32 -#define MSGDMA_0_DESCRIPTOR_SLAVE_DATA_WIDTH 32 -#define MSGDMA_0_DESCRIPTOR_SLAVE_DESCRIPTOR_FIFO_DEPTH 128 -#define MSGDMA_0_DESCRIPTOR_SLAVE_DMA_MODE 0 -#define MSGDMA_0_DESCRIPTOR_SLAVE_ENHANCED_FEATURES 0 -#define MSGDMA_0_DESCRIPTOR_SLAVE_ERROR_ENABLE 0 -#define MSGDMA_0_DESCRIPTOR_SLAVE_ERROR_ENABLE_DERIVED 0 -#define MSGDMA_0_DESCRIPTOR_SLAVE_ERROR_WIDTH 8 -#define MSGDMA_0_DESCRIPTOR_SLAVE_IRQ -1 -#define MSGDMA_0_DESCRIPTOR_SLAVE_IRQ_INTERRUPT_CONTROLLER_ID -1 -#define MSGDMA_0_DESCRIPTOR_SLAVE_MAX_BURST_COUNT 2 -#define MSGDMA_0_DESCRIPTOR_SLAVE_MAX_BYTE 1024 -#define MSGDMA_0_DESCRIPTOR_SLAVE_MAX_STRIDE 1 -#define MSGDMA_0_DESCRIPTOR_SLAVE_NAME "/dev/msgdma_0_descriptor_slave" -#define MSGDMA_0_DESCRIPTOR_SLAVE_PACKET_ENABLE 0 -#define MSGDMA_0_DESCRIPTOR_SLAVE_PACKET_ENABLE_DERIVED 0 -#define MSGDMA_0_DESCRIPTOR_SLAVE_PREFETCHER_ENABLE 0 -#define MSGDMA_0_DESCRIPTOR_SLAVE_PROGRAMMABLE_BURST_ENABLE 0 -#define MSGDMA_0_DESCRIPTOR_SLAVE_RESPONSE_PORT 2 -#define MSGDMA_0_DESCRIPTOR_SLAVE_SPAN 16 -#define MSGDMA_0_DESCRIPTOR_SLAVE_STRIDE_ENABLE 0 -#define MSGDMA_0_DESCRIPTOR_SLAVE_STRIDE_ENABLE_DERIVED 0 -#define MSGDMA_0_DESCRIPTOR_SLAVE_TRANSFER_TYPE "Aligned Accesses" -#define MSGDMA_0_DESCRIPTOR_SLAVE_TYPE "altera_msgdma" - - -/* - * onchip_flash_0_csr configuration - * - */ - -#define ALT_MODULE_CLASS_onchip_flash_0_csr altera_onchip_flash -#define ONCHIP_FLASH_0_CSR_BASE 0x200000 -#define ONCHIP_FLASH_0_CSR_BYTES_PER_PAGE 8192 -#define ONCHIP_FLASH_0_CSR_IRQ -1 -#define ONCHIP_FLASH_0_CSR_IRQ_INTERRUPT_CONTROLLER_ID -1 -#define ONCHIP_FLASH_0_CSR_NAME "/dev/onchip_flash_0_csr" -#define ONCHIP_FLASH_0_CSR_READ_ONLY_MODE 0 -#define ONCHIP_FLASH_0_CSR_SECTOR1_ENABLED 1 -#define ONCHIP_FLASH_0_CSR_SECTOR1_END_ADDR 0x7fff -#define ONCHIP_FLASH_0_CSR_SECTOR1_START_ADDR 0 -#define ONCHIP_FLASH_0_CSR_SECTOR2_ENABLED 1 -#define ONCHIP_FLASH_0_CSR_SECTOR2_END_ADDR 0xffff -#define ONCHIP_FLASH_0_CSR_SECTOR2_START_ADDR 0x8000 -#define ONCHIP_FLASH_0_CSR_SECTOR3_ENABLED 1 -#define ONCHIP_FLASH_0_CSR_SECTOR3_END_ADDR 0x6ffff -#define ONCHIP_FLASH_0_CSR_SECTOR3_START_ADDR 0x10000 -#define ONCHIP_FLASH_0_CSR_SECTOR4_ENABLED 1 -#define ONCHIP_FLASH_0_CSR_SECTOR4_END_ADDR 0xb7fff -#define ONCHIP_FLASH_0_CSR_SECTOR4_START_ADDR 0x70000 -#define ONCHIP_FLASH_0_CSR_SECTOR5_ENABLED 0 -#define ONCHIP_FLASH_0_CSR_SECTOR5_END_ADDR 0xffffffff -#define ONCHIP_FLASH_0_CSR_SECTOR5_START_ADDR 0xffffffff -#define ONCHIP_FLASH_0_CSR_SPAN 8 -#define ONCHIP_FLASH_0_CSR_TYPE "altera_onchip_flash" - - -/* - * onchip_flash_0_data configuration - * - */ - -#define ALT_MODULE_CLASS_onchip_flash_0_data altera_onchip_flash -#define ONCHIP_FLASH_0_DATA_BASE 0x0 -#define ONCHIP_FLASH_0_DATA_BYTES_PER_PAGE 8192 -#define ONCHIP_FLASH_0_DATA_IRQ -1 -#define ONCHIP_FLASH_0_DATA_IRQ_INTERRUPT_CONTROLLER_ID -1 -#define ONCHIP_FLASH_0_DATA_NAME "/dev/onchip_flash_0_data" -#define ONCHIP_FLASH_0_DATA_READ_ONLY_MODE 0 -#define ONCHIP_FLASH_0_DATA_SECTOR1_ENABLED 1 -#define ONCHIP_FLASH_0_DATA_SECTOR1_END_ADDR 0x7fff -#define ONCHIP_FLASH_0_DATA_SECTOR1_START_ADDR 0 -#define ONCHIP_FLASH_0_DATA_SECTOR2_ENABLED 1 -#define ONCHIP_FLASH_0_DATA_SECTOR2_END_ADDR 0xffff -#define ONCHIP_FLASH_0_DATA_SECTOR2_START_ADDR 0x8000 -#define ONCHIP_FLASH_0_DATA_SECTOR3_ENABLED 1 -#define ONCHIP_FLASH_0_DATA_SECTOR3_END_ADDR 0x6ffff -#define ONCHIP_FLASH_0_DATA_SECTOR3_START_ADDR 0x10000 -#define ONCHIP_FLASH_0_DATA_SECTOR4_ENABLED 1 -#define ONCHIP_FLASH_0_DATA_SECTOR4_END_ADDR 0xb7fff -#define ONCHIP_FLASH_0_DATA_SECTOR4_START_ADDR 0x70000 -#define ONCHIP_FLASH_0_DATA_SECTOR5_ENABLED 0 -#define ONCHIP_FLASH_0_DATA_SECTOR5_END_ADDR 0xffffffff -#define ONCHIP_FLASH_0_DATA_SECTOR5_START_ADDR 0xffffffff -#define ONCHIP_FLASH_0_DATA_SPAN 753664 -#define ONCHIP_FLASH_0_DATA_TYPE "altera_onchip_flash" - - -/* - * onchip_memory2_0 configuration - * - */ - -#define ALT_MODULE_CLASS_onchip_memory2_0 altera_avalon_onchip_memory2 -#define ONCHIP_MEMORY2_0_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0 -#define ONCHIP_MEMORY2_0_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0 -#define ONCHIP_MEMORY2_0_BASE 0x400000 -#define ONCHIP_MEMORY2_0_CONTENTS_INFO "" -#define ONCHIP_MEMORY2_0_DUAL_PORT 0 -#define ONCHIP_MEMORY2_0_GUI_RAM_BLOCK_TYPE "AUTO" -#define ONCHIP_MEMORY2_0_INIT_CONTENTS_FILE "ghrd_10m50da_onchip_memory2_0" -#define ONCHIP_MEMORY2_0_INIT_MEM_CONTENT 0 -#define ONCHIP_MEMORY2_0_INSTANCE_ID "NONE" -#define ONCHIP_MEMORY2_0_IRQ -1 -#define ONCHIP_MEMORY2_0_IRQ_INTERRUPT_CONTROLLER_ID -1 -#define ONCHIP_MEMORY2_0_NAME "/dev/onchip_memory2_0" -#define ONCHIP_MEMORY2_0_NON_DEFAULT_INIT_FILE_ENABLED 0 -#define ONCHIP_MEMORY2_0_RAM_BLOCK_TYPE "AUTO" -#define ONCHIP_MEMORY2_0_READ_DURING_WRITE_MODE "DONT_CARE" -#define ONCHIP_MEMORY2_0_SINGLE_CLOCK_OP 0 -#define ONCHIP_MEMORY2_0_SIZE_MULTIPLE 1 -#define ONCHIP_MEMORY2_0_SIZE_VALUE 131072 -#define ONCHIP_MEMORY2_0_SPAN 131072 -#define ONCHIP_MEMORY2_0_TYPE "altera_avalon_onchip_memory2" -#define ONCHIP_MEMORY2_0_WRITABLE 1 - - -/* - * spi_0 configuration - * - */ - -#define ALT_MODULE_CLASS_spi_0 altera_avalon_spi -#define SPI_0_BASE 0x100280 -#define SPI_0_CLOCKMULT 1 -#define SPI_0_CLOCKPHASE 1 -#define SPI_0_CLOCKPOLARITY 0 -#define SPI_0_CLOCKUNITS "Hz" -#define SPI_0_DATABITS 8 -#define SPI_0_DATAWIDTH 16 -#define SPI_0_DELAYMULT "1.0E-9" -#define SPI_0_DELAYUNITS "ns" -#define SPI_0_EXTRADELAY 0 -#define SPI_0_INSERT_SYNC 0 -#define SPI_0_IRQ 5 -#define SPI_0_IRQ_INTERRUPT_CONTROLLER_ID 0 -#define SPI_0_ISMASTER 1 -#define SPI_0_LSBFIRST 0 -#define SPI_0_NAME "/dev/spi_0" -#define SPI_0_NUMSLAVES 1 -#define SPI_0_PREFIX "spi_" -#define SPI_0_SPAN 32 -#define SPI_0_SYNC_REG_DEPTH 2 -#define SPI_0_TARGETCLOCK 128000u -#define SPI_0_TARGETSSDELAY "0.0" -#define SPI_0_TYPE "altera_avalon_spi" - - -/* - * sysid configuration - * - */ - -#define ALT_MODULE_CLASS_sysid altera_avalon_sysid_qsys -#define SYSID_BASE 0x100300 -#define SYSID_ID 0 -#define SYSID_IRQ -1 -#define SYSID_IRQ_INTERRUPT_CONTROLLER_ID -1 -#define SYSID_NAME "/dev/sysid" -#define SYSID_SPAN 8 -#define SYSID_TIMESTAMP 1512455752 -#define SYSID_TYPE "altera_avalon_sysid_qsys" - - -/* - * timer_0 configuration - * - */ - -#define ALT_MODULE_CLASS_timer_0 altera_avalon_timer -#define TIMER_0_ALWAYS_RUN 0 -#define TIMER_0_BASE 0x1002a0 -#define TIMER_0_COUNTER_SIZE 32 -#define TIMER_0_FIXED_PERIOD 0 -#define TIMER_0_FREQ 50000000 -#define TIMER_0_IRQ 2 -#define TIMER_0_IRQ_INTERRUPT_CONTROLLER_ID 0 -#define TIMER_0_LOAD_VALUE 49999 -#define TIMER_0_MULT 0.001 -#define TIMER_0_NAME "/dev/timer_0" -#define TIMER_0_PERIOD 1 -#define TIMER_0_PERIOD_UNITS "ms" -#define TIMER_0_RESET_OUTPUT 0 -#define TIMER_0_SNAPSHOT 1 -#define TIMER_0_SPAN 32 -#define TIMER_0_TICKS_PER_SEC 1000 -#define TIMER_0_TIMEOUT_PULSE_OUTPUT 0 -#define TIMER_0_TYPE "altera_avalon_timer" - -#endif /* __SYSTEM_H_ */ diff --git a/soc/altr/zephyr_nios2f/linker.ld b/soc/altr/zephyr_nios2f/linker.ld deleted file mode 100644 index 2370601984a..00000000000 --- a/soc/altr/zephyr_nios2f/linker.ld +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @brief Linker script for the Nios II/e CPU with timer and 16550 UART - */ - -#include -#include - -#define _RAM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_sram)) -#define _RAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) - -#define _ROM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_flash)) -#define _ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash)) - -#include diff --git a/soc/altr/zephyr_nios2f/soc.h b/soc/altr/zephyr_nios2f/soc.h deleted file mode 100644 index d23ddaa9187..00000000000 --- a/soc/altr/zephyr_nios2f/soc.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - - -#ifndef __SOC_H_ -#define __SOC_H_ - -#include - -#endif diff --git a/soc/altr/zephyr_nios2f/soc.yml b/soc/altr/zephyr_nios2f/soc.yml deleted file mode 100644 index 156e865a4cb..00000000000 --- a/soc/altr/zephyr_nios2f/soc.yml +++ /dev/null @@ -1,2 +0,0 @@ -socs: - - name: zephyr_nios2f diff --git a/tests/boards/altera_max10/i2c_master/CMakeLists.txt b/tests/boards/altera_max10/i2c_master/CMakeLists.txt deleted file mode 100644 index 351d582ea40..00000000000 --- a/tests/boards/altera_max10/i2c_master/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -cmake_minimum_required(VERSION 3.20.0) -find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -project(i2c_master) - -FILE(GLOB app_sources src/*.c) -target_sources(app PRIVATE ${app_sources}) diff --git a/tests/boards/altera_max10/i2c_master/README.txt b/tests/boards/altera_max10/i2c_master/README.txt deleted file mode 100644 index 5140572f6ab..00000000000 --- a/tests/boards/altera_max10/i2c_master/README.txt +++ /dev/null @@ -1,2 +0,0 @@ -Build test for: - Altera Nios-II I2C master soft IP core. diff --git a/tests/boards/altera_max10/i2c_master/prj.conf b/tests/boards/altera_max10/i2c_master/prj.conf deleted file mode 100644 index 3ec96195906..00000000000 --- a/tests/boards/altera_max10/i2c_master/prj.conf +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_I2C=y -CONFIG_I2C_INIT_PRIORITY=60 -CONFIG_ZTEST=y diff --git a/tests/boards/altera_max10/i2c_master/src/i2c_master.c b/tests/boards/altera_max10/i2c_master/src/i2c_master.c deleted file mode 100644 index c05bfa2e34e..00000000000 --- a/tests/boards/altera_max10/i2c_master/src/i2c_master.c +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (c) 2018 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include - -/* - * For ADV7513 Programming details, please - * refer to the following link. - * https://ez.analog.com/docs/DOC-1986 - */ - -#define ADV7513_HDMI_I2C_SLAVE_ADDR 0x39 - -#define ADV7513_CHIP_REVISION_REG 0x0 -#define CHIP_REVISION_VAL 0x13 - -#define ADV7513_MAIN_POWER_REG 0x41 -#define POWER_ON_VAL 0x10 - -#define ADV7513_HPD_CTRL_REG 0xD6 -#define HPD_CTRL_VAL 0xC0 - -#define ADV7513_WRITE_TEST_REG 0x2 -#define WRITE_TEST_VAL 0x66 - -static int powerup_adv7513(const struct device *i2c_dev) -{ - uint8_t data; - - TC_PRINT("Powering up ADV7513\n"); - /* write to HPD control registers */ - if (i2c_reg_write_byte(i2c_dev, ADV7513_HDMI_I2C_SLAVE_ADDR, - ADV7513_HPD_CTRL_REG, HPD_CTRL_VAL)) { - TC_PRINT("i2c write fail\n"); - return TC_FAIL; - } - if (i2c_reg_read_byte(i2c_dev, ADV7513_HDMI_I2C_SLAVE_ADDR, - 0xD6, &data)) { - TC_PRINT("failed to read HPD control\n"); - return TC_FAIL; - } - TC_PRINT("HPD control 0x%x\n", data); - - /* write to power control registers */ - if (i2c_reg_write_byte(i2c_dev, ADV7513_HDMI_I2C_SLAVE_ADDR, - ADV7513_MAIN_POWER_REG, POWER_ON_VAL)) { - TC_PRINT("i2c write fail\n"); - return TC_FAIL; - } - - if (i2c_reg_read_byte(i2c_dev, ADV7513_HDMI_I2C_SLAVE_ADDR, - 0x41, &data)) { - TC_PRINT("failed to read Power state\n"); - return TC_FAIL; - } - TC_PRINT("Power state 0x%x\n", data); - - return TC_PASS; -} - -static int test_i2c_adv7513(void) -{ - const struct device *const i2c_dev = DEVICE_DT_GET_ONE(altr_nios2_i2c); - uint32_t i2c_cfg = I2C_SPEED_SET(I2C_SPEED_STANDARD) | I2C_MODE_CONTROLLER; - uint8_t data; - - if (!device_is_ready(i2c_dev)) { - TC_PRINT("i2c device is not ready\n"); - return TC_FAIL; - } - - /* Test i2c_configure() */ - if (i2c_configure(i2c_dev, i2c_cfg)) { - TC_PRINT("i2c config failed\n"); - return TC_FAIL; - } - - /* Power up ADV7513 */ - zassert_true(powerup_adv7513(i2c_dev) == TC_PASS, - "ADV7513 power up failed"); - - TC_PRINT("*** Running i2c read/write tests ***\n"); - /* Test i2c byte read */ - data = 0x0; - if (i2c_reg_read_byte(i2c_dev, ADV7513_HDMI_I2C_SLAVE_ADDR, - ADV7513_CHIP_REVISION_REG, &data)) { - TC_PRINT("failed to read chip revision\n"); - return TC_FAIL; - } - if (data != CHIP_REVISION_VAL) { - TC_PRINT("chip revision does not match 0x%x\n", data); - return TC_FAIL; - } - TC_PRINT("i2c read test passed\n"); - - - /* Test i2c byte write */ - data = WRITE_TEST_VAL; - if (i2c_reg_write_byte(i2c_dev, ADV7513_HDMI_I2C_SLAVE_ADDR, - ADV7513_WRITE_TEST_REG, data)) { - TC_PRINT("i2c write fail\n"); - return TC_FAIL; - } - data = 0x0; - if (i2c_reg_read_byte(i2c_dev, ADV7513_HDMI_I2C_SLAVE_ADDR, - ADV7513_WRITE_TEST_REG, &data)) { - TC_PRINT("i2c read fail\n"); - return TC_FAIL; - } - if (data != WRITE_TEST_VAL) { - TC_PRINT("i2c write test failed 0x%x\n", data); - return TC_FAIL; - } - TC_PRINT("i2c write & verify test passed\n"); - - return TC_PASS; -} - -ZTEST(nios2_i2c_master, test_i2c_master) -{ - zassert_true(test_i2c_adv7513() == TC_PASS); -} - -ZTEST_SUITE(nios2_i2c_master, NULL, NULL, NULL, NULL, NULL); diff --git a/tests/boards/altera_max10/i2c_master/testcase.yaml b/tests/boards/altera_max10/i2c_master/testcase.yaml deleted file mode 100644 index dcdef34d092..00000000000 --- a/tests/boards/altera_max10/i2c_master/testcase.yaml +++ /dev/null @@ -1,4 +0,0 @@ -tests: - boards.altera_max10.i2c_master: - platform_allow: altera_max10 - tags: i2c diff --git a/tests/boards/altera_max10/msgdma/CMakeLists.txt b/tests/boards/altera_max10/msgdma/CMakeLists.txt deleted file mode 100644 index 96f0d8944ad..00000000000 --- a/tests/boards/altera_max10/msgdma/CMakeLists.txt +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -cmake_minimum_required(VERSION 3.20.0) -find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -project(msgdma) - -FILE(GLOB app_sources src/*.c) -target_sources(app PRIVATE ${app_sources}) - -target_include_directories(app PRIVATE - ${ZEPHYR_BASE}/kernel/include - ${ZEPHYR_BASE}/arch/${ARCH}/include - ) diff --git a/tests/boards/altera_max10/msgdma/README.txt b/tests/boards/altera_max10/msgdma/README.txt deleted file mode 100644 index 467a303c076..00000000000 --- a/tests/boards/altera_max10/msgdma/README.txt +++ /dev/null @@ -1,2 +0,0 @@ -Build test for: - Altera Nios-II Modular Scatter Gather DMA (MSGDMA) soft IP core. diff --git a/tests/boards/altera_max10/msgdma/prj.conf b/tests/boards/altera_max10/msgdma/prj.conf deleted file mode 100644 index ac2c3481e93..00000000000 --- a/tests/boards/altera_max10/msgdma/prj.conf +++ /dev/null @@ -1,2 +0,0 @@ -CONFIG_DMA=y -CONFIG_ZTEST=y diff --git a/tests/boards/altera_max10/msgdma/src/dma.c b/tests/boards/altera_max10/msgdma/src/dma.c deleted file mode 100644 index f02cab1330c..00000000000 --- a/tests/boards/altera_max10/msgdma/src/dma.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright (c) 2018 Intel Corporation. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include - -#define DMA_BUFF_SIZE 1024 - -enum dma_op_status { - DMA_OP_STAT_NONE = 0, - DMA_OP_STAT_ERR, - DMA_OP_STAT_SUCCESS, -}; - -static enum dma_op_status dma_stat; - -static char tx_data[DMA_BUFF_SIZE]; -static char rx_data[DMA_BUFF_SIZE]; - -static struct dma_config dma_cfg = {0}; -static struct dma_block_config dma_block_cfg = {0}; - -static void dma_user_callback(const struct device *dma_dev, void *arg, - uint32_t id, int status) -{ - if (status >= 0) { - TC_PRINT("DMA completed successfully\n"); - dma_stat = DMA_OP_STAT_SUCCESS; - } else { - TC_PRINT("DMA error occurred!! (%d)\n", status); - dma_stat = DMA_OP_STAT_ERR; - } -} - -ZTEST(nios2_msgdma, test_msgdma) -{ - const struct device *dma; - static uint32_t chan_id; - int i; - - dma = DEVICE_DT_GET(DT_NODELABEL(dma)); - __ASSERT_NO_MSG(device_is_ready(dma)); - - /* Init tx buffer */ - for (i = 0; i < DMA_BUFF_SIZE; i++) { - tx_data[i] = i; - } - - /* Init DMA config info */ - dma_cfg.channel_direction = MEMORY_TO_MEMORY; - dma_cfg.source_data_size = 1U; - dma_cfg.dest_data_size = 1U; - dma_cfg.source_burst_length = 1U; - dma_cfg.dest_burst_length = 1U; - dma_cfg.dma_callback = dma_user_callback; - dma_cfg.block_count = 1U; - dma_cfg.head_block = &dma_block_cfg; - - /* - * Set channel id to 0 as Nios-II - * MSGDMA only supports one channel - */ - chan_id = 0U; - - /* Init DMA descriptor info */ - dma_block_cfg.block_size = DMA_BUFF_SIZE; - dma_block_cfg.source_address = (uint32_t)tx_data; - dma_block_cfg.dest_address = (uint32_t)rx_data; - - /* Configure DMA */ - zassert_true(dma_config(dma, chan_id, &dma_cfg) == 0, - "DMA config error"); - - /* Make sure all the data is written out to memory */ - z_nios2_dcache_flush_all(); - - /* Start DMA operation */ - zassert_true(dma_start(dma, chan_id) == 0, "DMA start error"); - - while (dma_stat == DMA_OP_STAT_NONE) { - k_busy_wait(10); - } - - /* Invalidate the data cache */ - z_nios2_dcache_flush_no_writeback(rx_data, DMA_BUFF_SIZE); - - zassert_true(dma_stat == DMA_OP_STAT_SUCCESS, - "Nios-II DMA operation failed!!"); - - zassert_true(!memcmp(&tx_data, &rx_data, DMA_BUFF_SIZE), - "Nios-II DMA Test failed!!"); - -} - -ZTEST_SUITE(nios2_msgdma, NULL, NULL, NULL, NULL, NULL); diff --git a/tests/boards/altera_max10/msgdma/testcase.yaml b/tests/boards/altera_max10/msgdma/testcase.yaml deleted file mode 100644 index 52082445ce6..00000000000 --- a/tests/boards/altera_max10/msgdma/testcase.yaml +++ /dev/null @@ -1,4 +0,0 @@ -tests: - boards.altera_max10.dma: - platform_allow: altera_max10 - tags: dma diff --git a/tests/boards/altera_max10/qspi/CMakeLists.txt b/tests/boards/altera_max10/qspi/CMakeLists.txt deleted file mode 100644 index 24002a414be..00000000000 --- a/tests/boards/altera_max10/qspi/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -cmake_minimum_required(VERSION 3.20.0) -find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -project(qspi) - -FILE(GLOB app_sources src/*.c) -target_sources(app PRIVATE ${app_sources}) diff --git a/tests/boards/altera_max10/qspi/README.txt b/tests/boards/altera_max10/qspi/README.txt deleted file mode 100644 index ea7ca5a30c7..00000000000 --- a/tests/boards/altera_max10/qspi/README.txt +++ /dev/null @@ -1,2 +0,0 @@ -Build test for: - Altera Nios-II QSPI flash soft IP core. diff --git a/tests/boards/altera_max10/qspi/prj.conf b/tests/boards/altera_max10/qspi/prj.conf deleted file mode 100644 index c1de9b374e2..00000000000 --- a/tests/boards/altera_max10/qspi/prj.conf +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_STDOUT_CONSOLE=y -CONFIG_FLASH=y -CONFIG_SOC_FLASH_NIOS2_QSPI=y -CONFIG_ZTEST=y diff --git a/tests/boards/altera_max10/qspi/src/qspi_flash.c b/tests/boards/altera_max10/qspi/src/qspi_flash.c deleted file mode 100644 index cf6da9aa67b..00000000000 --- a/tests/boards/altera_max10/qspi/src/qspi_flash.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) 2018 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include - -#define MAX_NUM_OF_SECTORS 1024 -#define NUM_OF_SECTORS_TO_TEST 4 -#define FLASH_SECTOR_SIZE 65536 -#define TEST_DATA_LEN 4 - -ZTEST(nios2_qspi, test_qspi_flash) -{ - const struct device *flash_dev; - uint32_t i, offset, rd_val, wr_val; - uint8_t wr_buf[4] = {0xAA, 0xBB, 0xCC, 0xDD}; - uint8_t rd_buf[2]; - - flash_dev = DEVICE_DT_GET(DT_NODELABEL(n25q512ax3)); - zassert_true(!device_is_ready(flash_dev), TC_PASS, "Flash device is not ready!"); - - for (i = 0U; i < NUM_OF_SECTORS_TO_TEST; i++) { - TC_PRINT("\nTesting: Flash Sector-%d\n", i); - offset = FLASH_SECTOR_SIZE * i; - - /* Flash Erase Test */ - TC_PRINT(" Flash Erase Test..."); - zassert_equal(flash_erase(flash_dev, - offset, FLASH_SECTOR_SIZE), - TC_PASS, "Flash erase call failed!"); - zassert_equal(flash_read(flash_dev, offset, - &rd_val, TEST_DATA_LEN), - TC_PASS, "Flash read call failed!"); - /* In case of erase all bits will be set to 1 */ - wr_val = 0xffffffff; - zassert_equal(rd_val != wr_val, TC_PASS, - "Flash Erase Test failed!!"); - TC_PRINT("PASS\n"); - - - /* Flash Write & Read Test */ - TC_PRINT(" Flash Write & Read Test..."); - wr_val = 0xAABBCCDD; - zassert_equal(flash_write(flash_dev, offset, - &wr_val, TEST_DATA_LEN), - TC_PASS, "Flash write call failed!"); - zassert_equal(flash_read(flash_dev, offset, - &rd_val, TEST_DATA_LEN), - TC_PASS, "Flash read call failed!"); - zassert_equal(rd_val != wr_val, TC_PASS, - "Flash Write & Read Test failed!!"); - TC_PRINT("PASS\n"); - - - /* Flash Unaligned Read Test */ - TC_PRINT(" Flash Unaligned Read Test..."); - zassert_equal(flash_write(flash_dev, offset + sizeof(wr_val), - &wr_buf, sizeof(wr_buf)), - TC_PASS, "Flash write call failed!"); - zassert_equal(flash_read(flash_dev, offset + sizeof(wr_val) + 1, - &rd_buf, sizeof(rd_buf)), - TC_PASS, "Flash read call failed!"); - zassert_equal(memcmp(wr_buf + 1, rd_buf, sizeof(rd_buf)), - TC_PASS, "Flash Write & Read Test failed!!"); - TC_PRINT("PASS\n"); - } -} - -ZTEST_SUITE(nios2_qspi, NULL, NULL, NULL, NULL, NULL); diff --git a/tests/boards/altera_max10/qspi/testcase.yaml b/tests/boards/altera_max10/qspi/testcase.yaml deleted file mode 100644 index 363a54f5933..00000000000 --- a/tests/boards/altera_max10/qspi/testcase.yaml +++ /dev/null @@ -1,6 +0,0 @@ -tests: - boards.altera_max10.qspi: - platform_allow: altera_max10 - tags: - - qspi - - flash diff --git a/tests/boards/altera_max10/sysid/CMakeLists.txt b/tests/boards/altera_max10/sysid/CMakeLists.txt deleted file mode 100644 index 3c3abcb8d48..00000000000 --- a/tests/boards/altera_max10/sysid/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -cmake_minimum_required(VERSION 3.20.0) -find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -project(sysid) - -FILE(GLOB app_sources src/*.c) -target_sources(app PRIVATE ${app_sources}) diff --git a/tests/boards/altera_max10/sysid/README.txt b/tests/boards/altera_max10/sysid/README.txt deleted file mode 100644 index 5750997e8d5..00000000000 --- a/tests/boards/altera_max10/sysid/README.txt +++ /dev/null @@ -1,2 +0,0 @@ -Build test for: - Altera Nios-II System ID soft IP core. diff --git a/tests/boards/altera_max10/sysid/prj.conf b/tests/boards/altera_max10/sysid/prj.conf deleted file mode 100644 index 9467c292689..00000000000 --- a/tests/boards/altera_max10/sysid/prj.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_ZTEST=y diff --git a/tests/boards/altera_max10/sysid/src/sysid.c b/tests/boards/altera_max10/sysid/src/sysid.c deleted file mode 100644 index 962b4e90496..00000000000 --- a/tests/boards/altera_max10/sysid/src/sysid.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (c) 2017 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include - -#include "altera_avalon_sysid.h" - -ZTEST(nios2_sysid, test_sysid) -{ - int32_t sysid, status = TC_FAIL; - - sysid = alt_avalon_sysid_test(); - if (!sysid) { - status = TC_PASS; - TC_PRINT("[SysID] hardware and software appear to be in sync\n"); - } else if (sysid > 0) { - TC_PRINT("[SysID] software appears to be older than hardware\n"); - } else { - TC_PRINT("[SysID] hardware appears to be older than software\n"); - } - - zassert_equal(status, TC_PASS, "SysID test failed"); -} - -ZTEST_SUITE(nios2_sysid, NULL, NULL, NULL, NULL, NULL); diff --git a/tests/boards/altera_max10/sysid/testcase.yaml b/tests/boards/altera_max10/sysid/testcase.yaml deleted file mode 100644 index c38c908b176..00000000000 --- a/tests/boards/altera_max10/sysid/testcase.yaml +++ /dev/null @@ -1,4 +0,0 @@ -tests: - boards.altera_max10.sysid: - platform_allow: altera_max10 - tags: sysid