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driver: espi: add espi driver for rts5912 

add espi driver for rts5912

Signed-off-by: jhan bo chao <jhan_bo_chao@realtek.com>
pull/90829/head
jhan bo chao 2 months ago committed by Benjamin Cabé
parent
3f72a1a73e
commit
537791facf
8 changed files with 992 additions and 0 deletions
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  1. 9
      boards/realtek/rts5912_evb/rts5912_evb.dts
  2. 1
      drivers/espi/CMakeLists.txt
  3. 2
      drivers/espi/Kconfig
  4. 9
      drivers/espi/Kconfig.rts5912
  5. 240
      drivers/espi/espi_realtek_rts5912.c
  6. 79
      dts/arm/realtek/ec/rts5912.dtsi
  7. 19
      dts/bindings/espi/realtek,rts5912-espi.yaml
  8. 633
      soc/realtek/ec/rts5912/reg/reg_espi.h

9
boards/realtek/rts5912_evb/rts5912_evb.dts
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@ -71,3 +71,12 @@ @@ -71,3 +71,12 @@
pinctrl-names = "default";
pulses-per-round = <2>;
};
&espi0 {
status = "okay";
pinctrl-0 = < &espi_alert_gpio003 &espi_cs_gpio004
&espi_io3_gpio005 &espi_io2_gpio006
&espi_io1_gpio007 &espi_io0_gpio008
&espi_clk_gpio009 &espi_reset_gpio020>;
pinctrl-names = "default";
};

1
drivers/espi/CMakeLists.txt
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@ -15,3 +15,4 @@ zephyr_library_sources_ifdef(CONFIG_ESPI_XEC_V2 espi_mchp_xec_v2.c) @@ -15,3 +15,4 @@ zephyr_library_sources_ifdef(CONFIG_ESPI_XEC_V2 espi_mchp_xec_v2.c)
zephyr_library_sources_ifdef(CONFIG_ESPI_XEC_V2 espi_mchp_xec_host_v2.c)
zephyr_library_sources_ifdef(CONFIG_ESPI_IT8XXX2 espi_it8xxx2.c)
zephyr_library_sources_ifdef(CONFIG_ESPI_TAF_XEC_V2 espi_saf_mchp_xec_v2.c)
zephyr_library_sources_ifdef(CONFIG_ESPI_RTS5912 espi_realtek_rts5912.c)

2
drivers/espi/Kconfig
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@ -18,6 +18,8 @@ source "drivers/espi/Kconfig.espi_emul" @@ -18,6 +18,8 @@ source "drivers/espi/Kconfig.espi_emul"
source "drivers/espi/Kconfig.it8xxx2"
source "drivers/espi/Kconfig.rts5912"
module = ESPI
module-str = espi
source "subsys/logging/Kconfig.template.log_config"

9
drivers/espi/Kconfig.rts5912
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@ -0,0 +1,9 @@ @@ -0,0 +1,9 @@
# Copyright (c) 2025, Realtek, SIBG-SD7
# SPDX-License-Identifier: Apache-2.0
config ESPI_RTS5912
bool "Realtek RTS5912 eSPI Driver"
default y
depends on DT_HAS_REALTEK_RTS5912_ESPI_ENABLED
help
Enable the Realtek RTS5912 eSPI driver.

240
drivers/espi/espi_realtek_rts5912.c
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@ -0,0 +1,240 @@ @@ -0,0 +1,240 @@
/*
* Copyright (c) 2025 Realtek, SIBG-SD7
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT realtek_rts5912_espi
#include <zephyr/kernel.h>
#include <zephyr/drivers/espi.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/clock_control_rts5912.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(espi, CONFIG_ESPI_LOG_LEVEL);
#include "espi_utils.h"
#include "reg/reg_espi.h"
BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1, "support only one espi compatible node");
struct espi_rts5912_config {
volatile struct espi_reg *const espi_reg;
uint32_t espislv_clk_grp;
uint32_t espislv_clk_idx;
const struct device *clk_dev;
const struct pinctrl_dev_config *pcfg;
};
struct espi_rts5912_data {
sys_slist_t callbacks;
uint32_t config_data;
};
/*
* =========================================================================
* ESPI common function and API
* =========================================================================
*/
#define RTS5912_ESPI_MAX_FREQ_20 20
#define RTS5912_ESPI_MAX_FREQ_25 25
#define RTS5912_ESPI_MAX_FREQ_33 33
#define RTS5912_ESPI_MAX_FREQ_50 50
#define RTS5912_ESPI_MAX_FREQ_66 66
static int espi_rts5912_configure(const struct device *dev, struct espi_cfg *cfg)
{
const struct espi_rts5912_config *const espi_config = dev->config;
struct espi_rts5912_data *data = dev->data;
volatile struct espi_reg *const espi_reg = espi_config->espi_reg;
uint32_t gen_conf = 0;
uint8_t io_mode = 0;
/* Maximum Frequency Supported */
switch (cfg->max_freq) {
case RTS5912_ESPI_MAX_FREQ_20:
gen_conf |= 0UL << ESPI_ESPICFG_MXFREQSUP_Pos;
break;
case RTS5912_ESPI_MAX_FREQ_25:
gen_conf |= 1UL << ESPI_ESPICFG_MXFREQSUP_Pos;
break;
case RTS5912_ESPI_MAX_FREQ_33:
gen_conf |= 2UL << ESPI_ESPICFG_MXFREQSUP_Pos;
break;
case RTS5912_ESPI_MAX_FREQ_50:
gen_conf |= 3UL << ESPI_ESPICFG_MXFREQSUP_Pos;
break;
case RTS5912_ESPI_MAX_FREQ_66:
gen_conf |= 4UL << ESPI_ESPICFG_MXFREQSUP_Pos;
break;
default:
return -EINVAL;
}
/* I/O Mode Supported */
io_mode = cfg->io_caps >> 1;
if (io_mode > 3) {
return -EINVAL;
}
gen_conf |= io_mode << ESPI_ESPICFG_IOSUP_Pos;
/* Channel Supported */
if (cfg->channel_caps & ESPI_CHANNEL_PERIPHERAL) {
gen_conf |= BIT(0) << ESPI_ESPICFG_CHSUP_Pos;
}
if (cfg->channel_caps & ESPI_CHANNEL_VWIRE) {
gen_conf |= BIT(1) << ESPI_ESPICFG_CHSUP_Pos;
}
if (cfg->channel_caps & ESPI_CHANNEL_OOB) {
gen_conf |= BIT(2) << ESPI_ESPICFG_CHSUP_Pos;
}
if (cfg->channel_caps & ESPI_CHANNEL_FLASH) {
gen_conf |= BIT(3) << ESPI_ESPICFG_CHSUP_Pos;
}
espi_reg->ESPICFG = gen_conf;
data->config_data = espi_reg->ESPICFG;
return 0;
}
static bool espi_rts5912_channel_ready(const struct device *dev, enum espi_channel ch)
{
const struct espi_rts5912_config *const espi_config = dev->config;
volatile struct espi_reg *const espi_reg = espi_config->espi_reg;
switch (ch) {
case ESPI_CHANNEL_PERIPHERAL:
return espi_reg->EPCFG & ESPI_EPCFG_CHEN ? true : false;
case ESPI_CHANNEL_VWIRE:
return espi_reg->EVCFG & ESPI_EVCFG_CHEN ? true : false;
case ESPI_CHANNEL_OOB:
return espi_reg->EOCFG & ESPI_EOCFG_CHEN ? true : false;
case ESPI_CHANNEL_FLASH:
return espi_reg->EFCONF & ESPI_EFCONF_CHEN ? true : false;
default:
return false;
}
}
static int espi_rts5912_manage_callback(const struct device *dev, struct espi_callback *callback,
bool set)
{
struct espi_rts5912_data *data = dev->data;
return espi_manage_callback(&data->callbacks, callback, set);
}
static DEVICE_API(espi, espi_rts5912_driver_api) = {
.config = espi_rts5912_configure,
.get_channel_status = espi_rts5912_channel_ready,
.manage_callback = espi_rts5912_manage_callback,
};
static void espi_rst_isr(const struct device *dev)
{
const struct espi_rts5912_config *const espi_config = dev->config;
struct espi_rts5912_data *data = dev->data;
struct espi_event evt = {.evt_type = ESPI_BUS_RESET, .evt_details = 0, .evt_data = 0};
volatile struct espi_reg *const espi_reg = espi_config->espi_reg;
uint32_t status = espi_reg->ERSTCFG;
espi_reg->ERSTCFG |= ESPI_ERSTCFG_RSTSTS;
espi_reg->ERSTCFG ^= ESPI_ERSTCFG_RSTPOL;
if (status & ESPI_ERSTCFG_RSTSTS) {
if (status & ESPI_ERSTCFG_RSTPOL) {
/* rst pin high go low trigger interrupt */
evt.evt_data = 0;
} else {
/* rst pin low go high trigger interrupt */
evt.evt_data = 1;
}
espi_send_callbacks(&data->callbacks, dev, evt);
}
}
static void espi_bus_reset_setup(const struct device *dev)
{
const struct espi_rts5912_config *const espi_config = dev->config;
volatile struct espi_reg *const espi_reg = espi_config->espi_reg;
espi_reg->ERSTCFG = ESPI_ERSTCFG_RSTINTEN;
espi_reg->ERSTCFG = ESPI_ERSTCFG_RSTMONEN;
if (espi_reg->ERSTCFG & ESPI_ERSTCFG_RSTSTS) {
/* high to low */
espi_reg->ERSTCFG =
ESPI_ERSTCFG_RSTMONEN | ESPI_ERSTCFG_RSTPOL | ESPI_ERSTCFG_RSTINTEN;
} else {
/* low to high */
espi_reg->ERSTCFG = ESPI_ERSTCFG_RSTMONEN | ESPI_ERSTCFG_RSTINTEN;
}
NVIC_ClearPendingIRQ(DT_IRQ_BY_NAME(DT_DRV_INST(0), bus_rst, irq));
IRQ_CONNECT(DT_IRQ_BY_NAME(DT_DRV_INST(0), bus_rst, irq),
DT_IRQ_BY_NAME(DT_DRV_INST(0), bus_rst, priority), espi_rst_isr,
DEVICE_DT_GET(DT_DRV_INST(0)), 0);
irq_enable(DT_IRQ_BY_NAME(DT_DRV_INST(0), bus_rst, irq));
}
static int espi_rts5912_init(const struct device *dev)
{
const struct espi_rts5912_config *const espi_config = dev->config;
struct rts5912_sccon_subsys sccon;
int rc;
/* Setup eSPI pins */
rc = pinctrl_apply_state(espi_config->pcfg, PINCTRL_STATE_DEFAULT);
if (rc < 0) {
LOG_ERR("eSPI pinctrl setup failed (%d)", rc);
return rc;
}
if (!device_is_ready(espi_config->clk_dev)) {
LOG_ERR("eSPI clock not ready");
return -ENODEV;
}
/* Enable eSPI clock */
sccon.clk_grp = espi_config->espislv_clk_grp;
sccon.clk_idx = espi_config->espislv_clk_idx;
rc = clock_control_on(espi_config->clk_dev, (clock_control_subsys_t)&sccon);
if (rc != 0) {
LOG_ERR("eSPI clock control on failed");
goto exit;
}
/* Setup eSPI bus reset */
espi_bus_reset_setup(dev);
exit:
return rc;
}
PINCTRL_DT_INST_DEFINE(0);
static struct espi_rts5912_data espi_rts5912_data_0;
static const struct espi_rts5912_config espi_rts5912_config = {
.espi_reg = (volatile struct espi_reg *const)DT_INST_REG_ADDR_BY_NAME(0, espi_target),
.espislv_clk_grp = DT_CLOCKS_CELL_BY_NAME(DT_DRV_INST(0), espi_target, clk_grp),
.espislv_clk_idx = DT_CLOCKS_CELL_BY_NAME(DT_DRV_INST(0), espi_target, clk_idx),
.clk_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
};
DEVICE_DT_INST_DEFINE(0, &espi_rts5912_init, NULL, &espi_rts5912_data_0, &espi_rts5912_config,
PRE_KERNEL_2, CONFIG_ESPI_INIT_PRIORITY, &espi_rts5912_driver_api);

79
dts/arm/realtek/ec/rts5912.dtsi
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@ -169,6 +169,85 @@ @@ -169,6 +169,85 @@
status = "disabled";
};
espi0: espi0@400b1000 {
compatible = "realtek,rts5912-espi";
status = "disabled";
reg = <0x400b1000 0x200 /* espi target */
0x400a0400 0x01c /* port80 */
0x400a0200 0x1c /* ACPI */
0x400A021C 0x1C /* PROMT0 */
0x400A0238 0x1C /* PROMT1 */
0x400A0254 0x1C /* PROMT2 */
0x400A0270 0x1C /* PROMT3 */
0x40082000 0x14 /* EMI0 */
0x40082020 0x14 /* EMI1 */
0x40082040 0x14 /* EMI2 */
0x40082060 0x14 /* EMI3 */
0x40082080 0x14 /* EMI4 */
0x400820A0 0x14 /* EMI5 */
0x400820C0 0x14 /* EMI6 */
0x400820E0 0x14 /* EMI7 */
0x400a0100 0x1c /* KBC */
0x400B1600 0xd0>; /* MBX */
reg-names = "espi_target", "port80", "acpi", "promt0", "promt1", "promt2",
"promt3", "emi0", "emi1", "emi2", "emi3", "emi4", "emi5",
"emi6", "emi7", "kbc", "mbx";
clocks = <&sccon RTS5912_SCCON_PERIPH_GRP0 PERIPH_GRP0_ESPI_CLKPWR>,
<&sccon RTS5912_SCCON_PERIPH_GRP0 PERIPH_GRP0_P80_CLKPWR>,
<&sccon RTS5912_SCCON_PERIPH_GRP0 PERIPH_GRP0_ACPI_CLKPWR>,
<&sccon RTS5912_SCCON_PERIPH_GRP0 PERIPH_GRP0_PMPORT0_CLKPWR>,
<&sccon RTS5912_SCCON_PERIPH_GRP0 PERIPH_GRP0_PMPORT1_CLKPWR>,
<&sccon RTS5912_SCCON_PERIPH_GRP0 PERIPH_GRP0_PMPORT2_CLKPWR>,
<&sccon RTS5912_SCCON_PERIPH_GRP0 PERIPH_GRP0_PMPORT3_CLKPWR>,
<&sccon RTS5912_SCCON_PERIPH_GRP0 PERIPH_GRP0_EMI0_CLKPWR>,
<&sccon RTS5912_SCCON_PERIPH_GRP0 PERIPH_GRP0_EMI1_CLKPWR>,
<&sccon RTS5912_SCCON_PERIPH_GRP1 PERIPH_GRP1_EMI2_CLKPWR>,
<&sccon RTS5912_SCCON_PERIPH_GRP1 PERIPH_GRP1_EMI3_CLKPWR>,
<&sccon RTS5912_SCCON_PERIPH_GRP1 PERIPH_GRP1_EMI4_CLKPWR>,
<&sccon RTS5912_SCCON_PERIPH_GRP1 PERIPH_GRP1_EMI5_CLKPWR>,
<&sccon RTS5912_SCCON_PERIPH_GRP1 PERIPH_GRP1_EMI6_CLKPWR>,
<&sccon RTS5912_SCCON_PERIPH_GRP1 PERIPH_GRP1_EMI7_CLKPWR>,
<&sccon RTS5912_SCCON_PERIPH_GRP0 PERIPH_GRP0_KBC_CLKPWR>;
clock-names = "espi-target", "port80", "acpi", "promt0", "promt1", "promt2",
"promt3", "emi0", "emi1", "emi2", "emi3", "emi4", "emi5",
"emi6", "emi7", "kbc";
interrupts = <133 0>, <134 0>, <146 0>,
<145 0>, <144 0>, <143 0>,
<142 0>, <141 0>, <140 0>,
<139 0>, <138 0>, <137 0>,
<136 0>, <135 0>, <154 0>,
<155 0>, <156 0>, <157 0>,
<158 0>, <159 0>, <160 0>,
<161 0>, <162 0>, <163 0>,
<164 0>, <165 0>, <212 0>,
<213 0>, <214 0>, <215 0>,
<216 0>, <217 0>, <218 0>,
<219 0>, <147 0>, <148 0>,
<149 0>, <152 0>, <153 0>,
<166 0>, <220 0>;
interrupt-names = "bus-rst", "periph-ch", "vw-ch",
"vw-idx2", "vw-idx3", "vw-idx7",
"vw-idx41", "vw-idx42", "vw-idx43",
"vw-idx44", "vw-idx47", "vw-idx4a",
"vw-idx51", "vw-idx61", "kbc_ibf",
"kbc_obe", "acpi_ibf", "acpi_obe",
"promt0_ibf", "promt0_obe", "promt1_ibf",
"promt1_obe", "promt2_ibf", "promt2_obe",
"promt3_ibf", "promt3_obe", "emi0",
"emi1", "emi2", "emi3",
"emi4", "emi5", "emi6",
"emi7", "oob_tx", "oob_rx",
"oob_chg", "maf_tr", "flash_chg",
"port80", "mbx";
};
slwtmr0: slwtmr0@4000c200 {
compatible = "realtek,rts5912-slwtimer";
reg = <0x4000c200 0x10>;

19
dts/bindings/espi/realtek,rts5912-espi.yaml
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@ -0,0 +1,19 @@ @@ -0,0 +1,19 @@
# Copyright (c) 2025, Realtek, SIBG-SD7
# SPDX-License-Identifier: Apache-2.0
description: Realtek RTS5912 eSPI controller
compatible: "realtek,rts5912-espi"
include: [espi-controller.yaml, pinctrl-device.yaml]
properties:
reg:
description: mmio register space
required: true
pinctrl-0:
required: true
pinctrl-names:
required: true

633
soc/realtek/ec/rts5912/reg/reg_espi.h
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@ -0,0 +1,633 @@ @@ -0,0 +1,633 @@
/*
* Copyright (c) 2025 Realtek, SIBG-SD7
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_SOC_REALTEK_RTS5912_REG_ESPI_H
#define ZEPHYR_SOC_REALTEK_RTS5912_REG_ESPI_H
struct espi_reg {
uint32_t EPSTS;
uint32_t EPCFG;
uint32_t EPINTEN;
const uint32_t EPRXINFO;
uint32_t EPRXADRH;
uint32_t EPRXADRL;
uint32_t EPCPRADR;
uint32_t EPCPRVLD;
uint32_t EPBUF;
uint32_t EPBUFSZ;
uint32_t EPPTRCLR;
uint32_t ELMSG;
uint32_t EPMRDA;
uint32_t EPMRADRL;
uint32_t EPMRADRH;
uint32_t EPMRLEN;
uint32_t EVSTS;
uint32_t EVCFG;
uint32_t EVIDX2;
uint32_t EVIDX3;
uint32_t EVIDX7;
uint32_t EVIDX41;
uint32_t EVIDX42;
uint32_t EVIDX43;
uint32_t EVIDX44;
uint32_t EVIDX47;
uint32_t EVIDX4A;
uint32_t EVTXDAT;
uint32_t EVPVIDX;
uint32_t EVRXINTEN;
uint32_t EVTXINTEN;
uint32_t EOSTS;
uint32_t EOCFG;
uint32_t EORXINTEN;
uint32_t EORXBUF;
uint32_t EORXLEN;
uint32_t EOTXBUF;
uint32_t EOTXLEN;
uint32_t EOTXCTRL;
uint32_t EOTXINTEN;
uint32_t EFSTS;
uint32_t EFCONF;
uint32_t EMADR;
uint32_t EMTRLEN;
uint32_t EMBUF;
uint32_t EMCTRL;
uint32_t EMINTEN;
uint32_t ESBUF;
uint32_t ESINTEN;
uint32_t ESRXADR;
uint32_t ESRXLEN;
uint32_t ESPICFG;
uint32_t ERSTCFG;
uint32_t EVIDX51;
uint32_t EVIDX61;
uint32_t ESRXC;
uint32_t EFCFG2;
uint32_t EFCFG3;
uint32_t EFCFG4;
const uint32_t RESERVED[3];
uint32_t ELCTRL;
uint32_t ESBUF1;
uint32_t ESPRG0;
uint32_t ESPRG1;
uint32_t ESPDRT;
uint32_t ESP0STR;
uint32_t ESP1STR;
uint32_t ESP2STR;
uint32_t ESP3STR;
uint32_t ESP4STR;
uint32_t ESP5STR;
uint32_t ESP6STR;
uint32_t ESP7STR;
uint32_t ESP8STR;
uint32_t ESP9STR;
uint32_t ESPASTR;
uint32_t ESPBSTR;
uint32_t ESPCSTR;
uint32_t ESPDSTR;
uint32_t ESPESTR;
uint32_t ESPFSTR;
uint32_t ESP0LEN;
uint32_t ESP1LEN;
uint32_t ESP2LEN;
uint32_t ESP3LEN;
uint32_t ESP4LEN;
uint32_t ESP5LEN;
uint32_t ESP6LEN;
uint32_t ESP7LEN;
uint32_t ESP8LEN;
uint32_t ESP9LEN;
uint32_t ESPALEN;
uint32_t ESPBLEN;
uint32_t ESPCLEN;
uint32_t ESPDLEN;
uint32_t ESPELEN;
uint32_t ESPFLEN;
uint32_t ESWPRG0;
uint32_t ESRPRG0;
uint32_t ESWPRG1;
uint32_t ESRPRG1;
uint32_t ESWPRG2;
uint32_t ESRPRG2;
uint32_t ESWPRG3;
uint32_t ESRPRG3;
uint32_t ESWPRG4;
uint32_t ESRPRG4;
uint32_t ESWPRG5;
uint32_t ESRPRG5;
uint32_t ESWPRG6;
uint32_t ESRPRG6;
uint32_t ESWPRG7;
uint32_t ESRPRG7;
uint32_t ESWPRG8;
uint32_t ESRPRG8;
uint32_t ESWPRG9;
uint32_t ESRPRG9;
uint32_t ESWPRGA;
uint32_t ESRPRGA;
uint32_t ESWPRGB;
uint32_t ESRPRGB;
uint32_t ESWPRGC;
uint32_t ESRPRGC;
uint32_t ESWPRGD;
uint32_t ESRPRGD;
uint32_t ESWPRGE;
uint32_t ESRPRGE;
uint32_t ESWPRGF;
uint32_t ESRPRGF;
uint32_t ESPREN;
uint32_t ESPSTS;
uint32_t ESFLSZ;
uint32_t ESPINTEN;
uint32_t IOSHORTSTS;
uint32_t IOSHORTRDADDR;
uint32_t IOSHORTRDDATA;
uint32_t LDNCFG;
uint32_t ID0;
uint32_t ID1;
uint32_t VER;
};
BUILD_ASSERT(sizeof(struct espi_reg) == 568, "reg_espi size is not correct");
/* EPSTS */
#define ESPI_EPSTS_MWDONE BIT(0)
#define ESPI_EPSTS_MWADMS BIT(1)
#define ESPI_EPSTS_MRDONE BIT(2)
#define ESPI_EPSTS_LTXDONE BIT(3)
#define ESPI_EPSTS_CLRSTS BIT(4)
/* EPCFG */
#define ESPI_EPCFG_CHEN BIT(0)
#define ESPI_EPCFG_CHRDY BIT(1)
#define ESPI_EPCFG_BMTREN BIT(2)
#define ESPI_EPCFG_MXPLSUP GENMASK(6, 4)
#define ESPI_EPCFG_MXPLSEL GENMASK(10, 8)
#define ESPI_EPCFG_MXRDSZ GENMASK(14, 12)
/* EPINTEN */
#define ESPI_EPINTEN_CFGCHGEN BIT(0)
#define ESPI_EPINTEN_MEMWREN BIT(1)
#define ESPI_EPINTEN_MEMRDEN BIT(2)
/* EPRXINFO */
#define ESPI_EPRXINFO_LENGTH GENMASK(11, 0)
#define ESPI_EPRXINFO_TAG GENMASK(15, 12)
#define ESPI_EPRXINFO_CYCLE GENMASK(23, 16)
#define ESPI_EPRXINFO_OPCODE GENMASK(31, 24)
/* EPCPRVLD */
#define ESPI_EPCPRVLD_VALIDEN BIT(0)
/* EPBUFSZ */
#define ESPI_EPBUFSZ_SIZE GENMASK(3, 0)
/* EPPTRCLR */
#define ESPI_EPPTRCLR_WRCLR BIT(0)
#define ESPI_EPPTRCLR_RDCLR BIT(1)
/* ELMSG */
#define ESPI_ELMSG_MSGDAT GENMASK(15, 0)
#define ESPI_ELMSG_MSGCODE GENMASK(31, 16)
/* EPMRLEN */
#define ESPI_EPMRLEN_RXLEN GENMASK(11, 0)
/* EVSTS */
#define ESPI_EVSTS_RXEPT BIT(0)
#define ESPI_EVSTS_RXOVR BIT(1)
#define ESPI_EVSTS_TXFULL BIT(2)
#define ESPI_EVSTS_ILLCHG BIT(3)
#define ESPI_EVSTS_IDX2CHG BIT(4)
#define ESPI_EVSTS_IDX3CHG BIT(5)
#define ESPI_EVSTS_IDX7CHG BIT(6)
#define ESPI_EVSTS_IDX41CHG BIT(7)
#define ESPI_EVSTS_IDX42CHG BIT(8)
#define ESPI_EVSTS_IDX43CHG BIT(9)
#define ESPI_EVSTS_IDX44CHG BIT(10)
#define ESPI_EVSTS_IDX47CHG BIT(11)
#define ESPI_EVSTS_IDX4ACHG BIT(12)
#define ESPI_EVSTS_IDX51CHG BIT(13)
#define ESPI_EVSTS_IDX61CHG BIT(14)
#define ESPI_EVSTS_RXIDXCHG BIT(15)
#define ESPI_EVSTS_TXDONE BIT(16)
#define ESPI_EVSTS_RXIDXCLR BIT(17)
/* EVCFG */
#define ESPI_EVCFG_CHEN BIT(0)
#define ESPI_EVCFG_CHRDY BIT(1)
#define ESPI_EVCFG_MAXSUP GENMASK(13, 8)
#define ESPI_EVCFG_MAXCNT GENMASK(21, 16)
/* EVIDX2 */
#define ESPI_EVIDX2_RXDAT GENMASK(7, 0)
/* EVIDX3 */
#define ESPI_EVIDX3_RXDAT GENMASK(7, 0)
/* EVIDX7 */
#define ESPI_EVIDX7_RXDAT GENMASK(7, 0)
/* EVIDX41 */
#define ESPI_EVIDX41_RXDAT GENMASK(7, 0)
/* EVIDX42 */
#define ESPI_EVIDX42_RXDAT GENMASK(7, 0)
/* EVIDX43 */
#define ESPI_EVIDX43_RXDAT GENMASK(7, 0)
/* EVIDX44 */
#define ESPI_EVIDX44_RXDAT GENMASK(7, 0)
/* EVIDX47 */
#define ESPI_EVIDX47_RXDAT GENMASK(7, 0)
/* EVIDX4A */
#define ESPI_EVIDX4A_RXDAT GENMASK(7, 0)
/* EVTXDAT */
#define ESPI_EVTXDAT_TXDAT GENMASK(7, 0)
#define ESPI_EVTXDAT_TXIDX GENMASK(15, 8)
/* EVPVIDX */
#define ESPI_EVPVIDX_PVIDX GENMASK(7, 0)
/* EVRXINTEN */
#define ESPI_EVRXINTEN_CFGCHGEN BIT(0)
#define ESPI_EVRXINTEN_RXCHGEN GENMASK(2, 1)
/* EVTXINTEN */
#define ESPI_EVTXINTEN_TXMPTEN BIT(0)
/* EOSTS */
#define ESPI_EOSTS_RXPND BIT(0)
#define ESPI_EOSTS_RXDONE BIT(1)
#define ESPI_EOSTS_TXPND BIT(2)
#define ESPI_EOSTS_TXDONE BIT(3)
#define ESPI_EOSTS_CFGENCHG BIT(4)
/* EOCFG */
#define ESPI_EOCFG_CHEN BIT(0)
#define ESPI_EOCFG_CHRDY BIT(1)
#define ESPI_EOCFG_MXSZSUP GENMASK(6, 4)
#define ESPI_EOCFG_MXSZSEL GENMASK(10, 8)
/* EORXINTEN */
#define ESPI_EORXINTEN_CHENCHG BIT(0)
#define ESPI_EORXINTEN_RXEN GENMASK(1, 0)
/* EORXBUF */
#define ESPI_EORXBUF_RXDAT GENMASK(7, 0)
/* EORXLEN */
#define ESPI_EORXLEN_LENGTH GENMASK(11, 0)
/* EOTXBUF */
#define ESPI_EOTXBUF_TXDAT GENMASK(7, 0)
/* EOTXLEN */
#define ESPI_EOTXLEN_LENGTH GENMASK(11, 0)
/* EOTXCTRL */
#define ESPI_EOTXCTRL_TXSTR BIT(0)
/* EOTXINTEN */
#define ESPI_EOTXINTEN_TXEN BIT(0)
/* EFSTS */
#define ESPI_EFSTS_MAFTXDN BIT(0)
#define ESPI_EFSTS_MAFREOVR BIT(1)
#define ESPI_EFSTS_MAFREUDR BIT(2)
#define ESPI_EFSTS_SAFDONE BIT(3)
#define ESPI_EFSTS_SAFRW BIT(4)
#define ESPI_EFSTS_SAFERS BIT(5)
#define ESPI_EFSTS_CHENCHG BIT(6)
#define ESPI_EFSTS_OP2 BIT(7)
/* EFCONF */
#define ESPI_EFCONF_CHEN BIT(0)
#define ESPI_EFCONF_CHRDY BIT(1)
#define ESPI_EFCONF_ERBLKSZ GENMASK(3, 1)
#define ESPI_EFCONF_MXPLSUP GENMASK(13, 11)
#define ESPI_EFCONF_MXPLSEL GENMASK(15, 13)
#define ESPI_EFCONF_SHAREMD BIT(11)
#define ESPI_EFCONF_MXRDSZ GENMASK(14, 12)
#define ESPI_EFCONF_SHARECAPSP GENMASK(18, 16)
#define ESPI_EFCONF_RPMCCNT1 GENMASK(22, 20)
#define ESPI_EFCONF_RPMCOP1 GENMASK(31, 24)
/* EMTRLEN */
#define ESPI_EMTRLEN_TRLEN GENMASK(11, 0)
/* EMCTRL */
#define ESPI_EMCTRL_START BIT(0)
#define ESPI_EMCTRL_MDSEL_Pos 1
#define ESPI_EMCTRL_MDSEL_Msk (0x3UL << ESPI_EMCTRL_MDSEL_Pos)
#define ESPI_EMCTRL_MDSEL GENMASK(2, 1)
/* EMINTEN */
#define ESPI_EMINTEN_CHENCHG BIT(0)
#define ESPI_EMINTEN_TRDONEEN BIT(1)
/* ESBUF */
#define ESPI_ESINTEN_TRDONEEN BIT(0)
#define ESPI_ESINTEN_ERASEEN BIT(1)
#define ESPI_ESINTEN_RPMCEN BIT(2)
/* ESRXADR */
#define ESPI_ESRXLEN_LENGTH GENMASK(11, 0)
/* ESPICFG */
#define ESPI_ESPICFG_CHSUP_Pos (0UL)
#define ESPI_ESPICFG_CHSUP GENMASK(7, 0)
#define ESPI_ESPICFG_MXWAITALW GENMASK(11, 8)
#define ESPI_ESPICFG_MXFREQSUP_Pos (16UL)
#define ESPI_ESPICFG_MXFREQSUP_Msk (0x7UL << ESPI_ESPICFG_MXFREQSUP_Pos)
#define ESPI_ESPICFG_ODALRSUP BIT(19)
#define ESPI_ESPICFG_OPFREQ GENMASK(22, 20)
#define ESPI_ESPICFG_ODALRSEL GENMASK(25, 24)
#define ESPI_ESPICFG_IOSUP_Pos (24UL) /*!< IOSUP (Bit 24) */
#define ESPI_ESPICFG_IOSUP GENMASK(27, 26)
#define ESPI_ESPICFG_IOSEL GENMASK(29, 28)
#define ESPI_ESPICFG_ALRMODE BIT(28)
#define ESPI_ESPICFG_RTCINBMC BIT(29)
#define ESPI_ESPICFG_RSPMDFEN BIT(30)
#define ESPI_ESPICFG_CRCCHKEN BIT(31)
/* ERSTCFG */
#define ESPI_ERSTCFG_RSTMONEN BIT(0)
#define ESPI_ERSTCFG_RSTPOL BIT(1)
#define ESPI_ERSTCFG_RSTINTEN BIT(2)
#define ESPI_ERSTCFG_RSTSTS BIT(3)
/* EVIDX51 */
#define ESPI_EVIDX51_RXDAT GENMASK(7, 0)
/* EVIDX61 */
#define ESPI_EVIDX61_RXDAT GENMASK(7, 0)
/* ESRXC */
#define ESPI_ESRXC_RXDAT GENMASK(7, 0)
/* EFCFG2 */
#define ESPI_EFCFG2_MXRDSZ GENMASK(2, 0)
#define ESPI_EFCFG2_ERBLKSZ GENMASK(11, 8)
#define ESPI_EFCFG2_RPMCSP GENMASK(21, 16)
#define ESPI_EFCFG2_NUMRPMC GENMASK(24, 22)
/* EFCFG3 */
#define ESPI_EFCFG3_RPMCCNT2 GENMASK(23, 20)
#define ESPI_EFCFG3_RPMCOP2 GENMASK(31, 24)
/* EFCFG4 */
#define ESPI_EFCFG4_RPMCCNT3 GENMASK(3, 0)
#define ESPI_EFCFG4_RPMCOP3 GENMASK(11, 8)
#define ESPI_EFCFG4_RPMCCNT4 GENMASK(23, 20)
#define ESPI_EFCFG4_RPMCOP4 GENMASK(31, 24)
/* ELCTRL */
#define ESPI_ELCTRL_TXSTR BIT(0)
/* ESBUF1 */
#define ESPI_ESPRG0_TAG0GRP GENMASK(2, 0)
#define ESPI_ESPRG0_TAG1GRP GENMASK(6, 4)
#define ESPI_ESPRG0_TAG2GRP GENMASK(10, 8)
#define ESPI_ESPRG0_TAG3GRP GENMASK(14, 12)
#define ESPI_ESPRG0_TAG4GRP GENMASK(18, 16)
#define ESPI_ESPRG0_TAG5GRP GENMASK(22, 20)
#define ESPI_ESPRG0_TAG6GRP GENMASK(26, 24)
#define ESPI_ESPRG0_TAG7GRP GENMASK(30, 28)
/* ESPRG1 */
#define ESPI_ESPRG1_TAG8GRP GENMASK(2, 0)
#define ESPI_ESPRG1_TAG9GRP GENMASK(6, 4)
#define ESPI_ESPRG1_TAGAGRP GENMASK(10, 8)
#define ESPI_ESPRG1_TAGBGRP GENMASK(14, 12)
#define ESPI_ESPRG1_TAGCGRP GENMASK(18, 16)
#define ESPI_ESPRG1_TAGDGRP GENMASK(22, 20)
#define ESPI_ESPRG1_TAGEGRP GENMASK(26, 24)
#define ESPI_ESPRG1_TAGFGRP GENMASK(30, 28)
/* ESPDRT */
#define ESPI_ESPDRT_TAGDRT BIT(0)
/* ESP0STR */
#define ESPI_ESP0STR_ADDR GENMASK(19, 0)
/* ESP1STR */
#define ESPI_ESP1STR_ADDR GENMASK(19, 0)
/* ESP2STR */
#define ESPI_ESP2STR_ADDR GENMASK(19, 0)
/* ESP3STR */
#define ESPI_ESP3STR_ADDR GENMASK(19, 0)
/* ESP4STR */
#define ESPI_ESP4STR_ADDR GENMASK(19, 0)
/* ESP5STR */
#define ESPI_ESP5STR_ADDR GENMASK(19, 0)
/* ESP6STR */
#define ESPI_ESP6STR_ADDR GENMASK(19, 0)
/* ESP7STR */
#define ESPI_ESP7STR_ADDR GENMASK(19, 0)
/* ESP8STR */
#define ESPI_ESP8STR_ADDR GENMASK(19, 0)
/* ESP9STR */
#define ESPI_ESP9STR_ADDR GENMASK(19, 0)
/* ESPASTR */
#define ESPI_ESPASTR_ADDR GENMASK(19, 0)
/* ESPBSTR */
#define ESPI_ESPBSTR_ADDR GENMASK(19, 0)
/* ESPCSTR */
#define ESPI_ESPCSTR_ADDR GENMASK(19, 0)
/* ESPDSTR */
#define ESPI_ESPDSTR_ADDR GENMASK(19, 0)
/* ESPESTR */
#define ESPI_ESPESTR_ADDR GENMASK(19, 0)
/* ESPFSTR */
#define ESPI_ESPFSTR_ADDR GENMASK(19, 0)
/* ESP0LEN */
#define ESPI_ESP0LEN_LEN GENMASK(15, 0)
/* ESP1LEN */
#define ESPI_ESP1LEN_LEN GENMASK(15, 0)
/* ESP2LEN */
#define ESPI_ESP2LEN_LEN GENMASK(15, 0)
/* ESP3LEN */
#define ESPI_ESP3LEN_LEN GENMASK(15, 0)
/* ESP4LEN */
#define ESPI_ESP4LEN_LEN GENMASK(15, 0)
/* ESP5LEN */
#define ESPI_ESP5LEN_LEN GENMASK(15, 0)
/* ESP6LEN */
#define ESPI_ESP6LEN_LEN GENMASK(15, 0)
/* ESP7LEN */
#define ESPI_ESP7LEN_LEN GENMASK(15, 0)
/* ESP8LEN */
#define ESPI_ESP8LEN_LEN GENMASK(15, 0)
/* ESP9LEN */
#define ESPI_ESP9LEN_LEN GENMASK(15, 0)
/* ESPALEN */
#define ESPI_ESPALEN_LEN GENMASK(15, 0)
/* ESPBLEN */
#define ESPI_ESPBLEN_LEN GENMASK(15, 0)
/* ESPCLEN */
#define ESPI_ESPCLEN_LEN GENMASK(15, 0)
/* ESPDLEN */
#define ESPI_ESPDLEN_LEN GENMASK(15, 0)
/* ESPELEN */
#define ESPI_ESPELEN_LEN GENMASK(15, 0)
/* ESPFLEN */
#define ESPI_ESPFLEN_LEN GENMASK(15, 0)
/* ESWPRG0 */
#define ESPI_ESWPRG0_GWREN BIT(0)
/* ESWPRG1 */
#define ESPI_ESWPRG1_GWREN BIT(0)
/* ESWPRG2 */
#define ESPI_ESWPRG2_GWREN BIT(0)
/* ESWPRG3 */
#define ESPI_ESWPRG3_GWREN BIT(0)
/* ESWPRG4 */
#define ESPI_ESWPRG4_GWREN BIT(0)
/* ESWPRG5 */
#define ESPI_ESWPRG5_GWREN BIT(0)
/* ESWPRG6 */
#define ESPI_ESWPRG6_GWREN BIT(0)
/* ESWPRG7 */
#define ESPI_ESWPRG7_GWREN BIT(0)
/* ESWPRG8 */
#define ESPI_ESWPRG8_GWREN BIT(0)
/* ESWPRG9 */
#define ESPI_ESWPRG9_GWREN BIT(0)
/* ESWPRGA */
#define ESPI_ESWPRGA_GWREN BIT(0)
/* ESWPRGB */
#define ESPI_ESWPRGB_GWREN BIT(0)
/* ESWPRGC */
#define ESPI_ESWPRGC_GWREN BIT(0)
/* ESWPRGD */
#define ESPI_ESWPRGD_GWREN BIT(0)
/* ESWPRGE */
#define ESPI_ESWPRGE_GWREN BIT(0)
/* ESWPRGF */
#define ESPI_ESWPRGF_GWREN BIT(0)
/* ESRPRG0 */
#define ESPI_ESRPRG0_GRDEN BIT(0)
/* ESRPRG1 */
#define ESPI_ESRPRG1_GRDEN BIT(0)
/* ESRPRG2 */
#define ESPI_ESRPRG2_GRDEN BIT(0)
/* ESRPRG3 */
#define ESPI_ESRPRG3_GRDEN BIT(0)
/* ESRPRG4 */
#define ESPI_ESRPRG4_GRDEN BIT(0)
/* ESRPRG5 */
#define ESPI_ESRPRG5_GRDEN BIT(0)
/* ESRPRG6 */
#define ESPI_ESRPRG6_GRDEN BIT(0)
/* ESRPRG7 */
#define ESPI_ESRPRG7_GRDEN BIT(0)
/* ESRPRG8 */
#define ESPI_ESRPRG8_GRDEN BIT(0)
/* ESRPRG9 */
#define ESPI_ESRPRG9_GRDEN BIT(0)
/* ESRPRGA */
#define ESPI_ESRPRGA_GRDEN BIT(0)
/* ESRPRGB */
#define ESPI_ESRPRGB_GRDEN BIT(0)
/* ESRPRGC */
#define ESPI_ESRPRGC_GRDEN BIT(0)
/* ESRPRGD */
#define ESPI_ESRPRGD_GRDEN BIT(0)
/* ESRPRGE */
#define ESPI_ESRPRGE_GRDEN BIT(0)
/* ESRPRGF */
#define ESPI_ESRPRGF_GRDEN BIT(0)
/* ESPREN */
#define ESPI_ESPREN_EN BIT(0)
/* ESPSTS */
#define ESPI_ESPSTS_OVSIZE BIT(0)
#define ESPI_ESPSTS_HIT BIT(1)
#define ESPI_ESPSTS_CRS4K BIT(2)
/* ESPINTEN */
#define ESPI_ESPINTEN_OVSIZEEN BIT(0)
#define ESPI_ESPINTEN_HITEN BIT(1)
#define ESPI_ESPINTEN_CRS4KEN BIT(2)
/* IOSHORTSTS */
#define ESPI_IOSHORTSTS_BYTES GENMASK(1, 0)
#define ESPI_IOSHORTSTS_TYPE GENMASK(3, 2)
#define ESPI_IOSHORTSTS_ACCEPT GENMASK(4, 3)
/* IOSHORTRDADDR */
#define ESPI_IOSHORTRDADDR_ADDR GENMASK(15, 0)
/* LDNCFG */
#define ESPI_LDNCFG_IDX GENMASK(15, 0)
#endif /* ZEPHYR_SOC_REALTEK_RTS5912_REG_ESPI_H */
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