soc: microchip_miv: Port to HWMv2

Ports the SoC configuration to hardware model version 2

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>

soc/microchip/miv/Kconfig

@@ -1,4 +1,8 @@
 # Copyright (c) 2024 Nordic Semiconductor ASA
 # SPDX-License-Identifier: Apache-2.0
 
-source "soc/soc_legacy/riscv/microchip_miv/*/Kconfig.defconfig.series"
+if SOC_FAMILY_MICROCHIP_MIV
+
+rsource "*/Kconfig"
+
+endif # SOC_FAMILY_MICROCHIP_MIV

soc/microchip/miv/Kconfig.defconfig

@@ -0,0 +1,8 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_FAMILY_MICROCHIP_MIV
+
+rsource "*/Kconfig.defconfig"
+
+endif # SOC_FAMILY_MICROCHIP_MIV

soc/microchip/miv/Kconfig.soc

@@ -0,0 +1,10 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_MICROCHIP_MIV
+	bool
+
+config SOC_FAMILY
+	default "microchip_miv" if SOC_FAMILY_MICROCHIP_MIV
+
+rsource "*/Kconfig.soc"

soc/microchip/miv/miv/Kconfig

@@ -3,12 +3,12 @@
 # Copyright (c) 2018 Antmicro <www.antmicro.com>
 # SPDX-License-Identifier: Apache-2.0
 
-choice
+config SOC_SERIES_MIV
-	prompt "Microchip Mi-V system implementation"
+	select RISCV
-	depends on SOC_SERIES_MIV
+	select RISCV_PRIVILEGED
+	select RISCV_HAS_PLIC
 
 config SOC_MIV
-	bool "Microchip Mi-V system implementation"
 	select ATOMIC_OPERATIONS_BUILTIN
 	select INCLUDE_RESET_VECTOR
 	select RISCV_ISA_RV32I
@@ -16,5 +16,3 @@ config SOC_MIV
 	select RISCV_ISA_EXT_A
 	select RISCV_ISA_EXT_ZICSR
 	select RISCV_ISA_EXT_ZIFENCEI
-
-endchoice

soc/microchip/miv/miv/Kconfig.defconfig

@@ -2,9 +2,6 @@
 
 if SOC_SERIES_MIV
 
-config SOC_SERIES
-	default "miv"
-
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 4000000
 

soc/microchip/miv/miv/Kconfig.soc

@@ -0,0 +1,22 @@
+# RISCV32_MIV configuration options
+
+# Copyright (c) 2018 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_MIV
+	bool
+	select SOC_FAMILY_MICROCHIP_MIV
+	help
+	  Microchip Mi-V implementation#
+
+config SOC_MIV
+	bool
+	select SOC_SERIES_MIV
+	help
+	  Microchip Mi-V system implementation
+
+config SOC_SERIES
+	default "miv" if SOC_SERIES_MIV
+
+config SOC
+	default "miv" if SOC_MIV

soc/microchip/miv/polarfire/Kconfig

@@ -3,12 +3,12 @@
 # Copyright (c) 2020-2021 Microchip Technology Inc
 # SPDX-License-Identifier: Apache-2.0
 
-choice
+config SOC_SERIES_POLARFIRE
-	prompt "Microchip Polarfire SOC implementation"
+	select RISCV
-	depends on SOC_SERIES_POLARFIRE
+	select RISCV_PRIVILEGED
+	select RISCV_HAS_PLIC
 
 config SOC_POLARFIRE
-	bool "Microchip MPFS system implementation"
 	select ATOMIC_OPERATIONS_BUILTIN
 	select RISCV_GP
 	select USE_SWITCH_SUPPORTED
@@ -22,8 +22,6 @@ config SOC_POLARFIRE
 	select RISCV_ISA_EXT_ZICSR
 	select RISCV_ISA_EXT_ZIFENCEI
 
-endchoice
-
 config MPFS_HAL
 	depends on SOC_POLARFIRE
 	bool "Microchip Polarfire SOC hardware abstracton layer"

soc/microchip/miv/polarfire/Kconfig.defconfig

@@ -3,9 +3,6 @@
 
 if SOC_SERIES_POLARFIRE
 
-config SOC_SERIES
-	default "polarfire"
-
 # MPFS should be configured so that the mtimer clock is 1MHz independent of the CPU clock...
 
 config SYS_CLOCK_HW_CYCLES_PER_SEC

soc/microchip/miv/polarfire/Kconfig.soc

@@ -0,0 +1,22 @@
+# RISCV64_MIV Microchip Polarfire SOC configuration options
+
+# Copyright (c) 2020-2021 Microchip Technology Inc
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_POLARFIRE
+	bool
+	select SOC_FAMILY_MICROCHIP_MIV
+	help
+	  Microchip RV64 implementation
+
+config SOC_POLARFIRE
+	bool
+	select SOC_SERIES_POLARFIRE
+	help
+	  Microchip MPFS system implementation
+
+config SOC_SERIES
+	default "polarfire" if SOC_SERIES_POLARFIRE
+
+config SOC
+	default "polarfire" if SOC_POLARFIRE

soc/microchip/miv/soc.yml

@@ -0,0 +1,9 @@
+family:
+- name: microchip_miv
+  series:
+  - name: miv
+    socs:
+    - name: miv
+  - name: polarfire
+    socs:
+    - name: polarfire

soc/soc_legacy/riscv/microchip_miv/Kconfig

@@ -1,15 +0,0 @@
-# Copyright (c) 2024 Nordic Semiconductor ASA
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_FAMILY_MICROCHIP_MIV
-	bool
-
-if SOC_FAMILY_MICROCHIP_MIV
-
-config SOC_FAMILY
-	string
-	default "microchip_miv"
-
-source "soc/soc_legacy/riscv/microchip_miv/*/Kconfig.soc"
-
-endif # SOC_FAMILY_MICROCHIP_MIV

soc/soc_legacy/riscv/microchip_miv/Kconfig.soc

@@ -1,4 +0,0 @@
-# Copyright (c) 2024 Nordic Semiconductor ASA
-# SPDX-License-Identifier: Apache-2.0
-
-source "soc/soc_legacy/riscv/microchip_miv/*/Kconfig.series"

soc/soc_legacy/riscv/microchip_miv/miv/Kconfig.series

@@ -1,13 +0,0 @@
-# RISCV32_MIV implementation
-
-# Copyright (c) 2018 Antmicro <www.antmicro.com>
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_SERIES_MIV
-	bool "Microchip Mi-V implementation"
-	select SOC_FAMILY_MICROCHIP_MIV
-	select RISCV
-	select RISCV_PRIVILEGED
-	select RISCV_HAS_PLIC
-	help
-	  Enable support for Microchip Mi-V

soc/soc_legacy/riscv/microchip_miv/polarfire/Kconfig.series

@@ -1,13 +0,0 @@
-# RISCV64_MIV implementation
-
-# Copyright (c) 2018 Antmicro <www.antmicro.com>
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_SERIES_POLARFIRE
-	bool "Microchip RV64 implementation"
-	select SOC_FAMILY_MICROCHIP_MIV
-	select RISCV
-	select RISCV_PRIVILEGED
-	select RISCV_HAS_PLIC
-	help
-	  Enable support for Microchip RISCV 64bit