diff --git a/soc/soc_legacy/riscv/microchip_miv/CMakeLists.txt b/soc/microchip/miv/CMakeLists.txt similarity index 100% rename from soc/soc_legacy/riscv/microchip_miv/CMakeLists.txt rename to soc/microchip/miv/CMakeLists.txt diff --git a/soc/soc_legacy/riscv/microchip_miv/Kconfig.defconfig b/soc/microchip/miv/Kconfig similarity index 50% rename from soc/soc_legacy/riscv/microchip_miv/Kconfig.defconfig rename to soc/microchip/miv/Kconfig index 18469be7708..d509a538927 100644 --- a/soc/soc_legacy/riscv/microchip_miv/Kconfig.defconfig +++ b/soc/microchip/miv/Kconfig @@ -1,4 +1,8 @@ # Copyright (c) 2024 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -source "soc/soc_legacy/riscv/microchip_miv/*/Kconfig.defconfig.series" +if SOC_FAMILY_MICROCHIP_MIV + +rsource "*/Kconfig" + +endif # SOC_FAMILY_MICROCHIP_MIV diff --git a/soc/microchip/miv/Kconfig.defconfig b/soc/microchip/miv/Kconfig.defconfig new file mode 100644 index 00000000000..b63f842dd57 --- /dev/null +++ b/soc/microchip/miv/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_MICROCHIP_MIV + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_MICROCHIP_MIV diff --git a/soc/microchip/miv/Kconfig.soc b/soc/microchip/miv/Kconfig.soc new file mode 100644 index 00000000000..5725ff29b19 --- /dev/null +++ b/soc/microchip/miv/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_MICROCHIP_MIV + bool + +config SOC_FAMILY + default "microchip_miv" if SOC_FAMILY_MICROCHIP_MIV + +rsource "*/Kconfig.soc" diff --git a/soc/soc_legacy/riscv/microchip_miv/miv/CMakeLists.txt b/soc/microchip/miv/miv/CMakeLists.txt similarity index 100% rename from soc/soc_legacy/riscv/microchip_miv/miv/CMakeLists.txt rename to soc/microchip/miv/miv/CMakeLists.txt diff --git a/soc/soc_legacy/riscv/microchip_miv/miv/Kconfig.soc b/soc/microchip/miv/miv/Kconfig similarity index 70% rename from soc/soc_legacy/riscv/microchip_miv/miv/Kconfig.soc rename to soc/microchip/miv/miv/Kconfig index 0a48c2e0524..132818de4e7 100644 --- a/soc/soc_legacy/riscv/microchip_miv/miv/Kconfig.soc +++ b/soc/microchip/miv/miv/Kconfig @@ -3,12 +3,12 @@ # Copyright (c) 2018 Antmicro # SPDX-License-Identifier: Apache-2.0 -choice - prompt "Microchip Mi-V system implementation" - depends on SOC_SERIES_MIV +config SOC_SERIES_MIV + select RISCV + select RISCV_PRIVILEGED + select RISCV_HAS_PLIC config SOC_MIV - bool "Microchip Mi-V system implementation" select ATOMIC_OPERATIONS_BUILTIN select INCLUDE_RESET_VECTOR select RISCV_ISA_RV32I @@ -16,5 +16,3 @@ config SOC_MIV select RISCV_ISA_EXT_A select RISCV_ISA_EXT_ZICSR select RISCV_ISA_EXT_ZIFENCEI - -endchoice diff --git a/soc/soc_legacy/riscv/microchip_miv/miv/Kconfig.defconfig.series b/soc/microchip/miv/miv/Kconfig.defconfig similarity index 91% rename from soc/soc_legacy/riscv/microchip_miv/miv/Kconfig.defconfig.series rename to soc/microchip/miv/miv/Kconfig.defconfig index 35f4365b02b..68230c69bb8 100644 --- a/soc/soc_legacy/riscv/microchip_miv/miv/Kconfig.defconfig.series +++ b/soc/microchip/miv/miv/Kconfig.defconfig @@ -2,9 +2,6 @@ if SOC_SERIES_MIV -config SOC_SERIES - default "miv" - config SYS_CLOCK_HW_CYCLES_PER_SEC default 4000000 diff --git a/soc/microchip/miv/miv/Kconfig.soc b/soc/microchip/miv/miv/Kconfig.soc new file mode 100644 index 00000000000..7e2eafe118e --- /dev/null +++ b/soc/microchip/miv/miv/Kconfig.soc @@ -0,0 +1,22 @@ +# RISCV32_MIV configuration options + +# Copyright (c) 2018 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_MIV + bool + select SOC_FAMILY_MICROCHIP_MIV + help + Microchip Mi-V implementation# + +config SOC_MIV + bool + select SOC_SERIES_MIV + help + Microchip Mi-V system implementation + +config SOC_SERIES + default "miv" if SOC_SERIES_MIV + +config SOC + default "miv" if SOC_MIV diff --git a/soc/soc_legacy/riscv/microchip_miv/polarfire/CMakeLists.txt b/soc/microchip/miv/polarfire/CMakeLists.txt similarity index 100% rename from soc/soc_legacy/riscv/microchip_miv/polarfire/CMakeLists.txt rename to soc/microchip/miv/polarfire/CMakeLists.txt diff --git a/soc/soc_legacy/riscv/microchip_miv/polarfire/Kconfig.soc b/soc/microchip/miv/polarfire/Kconfig similarity index 80% rename from soc/soc_legacy/riscv/microchip_miv/polarfire/Kconfig.soc rename to soc/microchip/miv/polarfire/Kconfig index 101e8b4d029..b57d0ee92fb 100644 --- a/soc/soc_legacy/riscv/microchip_miv/polarfire/Kconfig.soc +++ b/soc/microchip/miv/polarfire/Kconfig @@ -3,12 +3,12 @@ # Copyright (c) 2020-2021 Microchip Technology Inc # SPDX-License-Identifier: Apache-2.0 -choice - prompt "Microchip Polarfire SOC implementation" - depends on SOC_SERIES_POLARFIRE +config SOC_SERIES_POLARFIRE + select RISCV + select RISCV_PRIVILEGED + select RISCV_HAS_PLIC config SOC_POLARFIRE - bool "Microchip MPFS system implementation" select ATOMIC_OPERATIONS_BUILTIN select RISCV_GP select USE_SWITCH_SUPPORTED @@ -22,8 +22,6 @@ config SOC_POLARFIRE select RISCV_ISA_EXT_ZICSR select RISCV_ISA_EXT_ZIFENCEI -endchoice - config MPFS_HAL depends on SOC_POLARFIRE bool "Microchip Polarfire SOC hardware abstracton layer" diff --git a/soc/soc_legacy/riscv/microchip_miv/polarfire/Kconfig.defconfig.series b/soc/microchip/miv/polarfire/Kconfig.defconfig similarity index 92% rename from soc/soc_legacy/riscv/microchip_miv/polarfire/Kconfig.defconfig.series rename to soc/microchip/miv/polarfire/Kconfig.defconfig index 53e88f1096e..113a3bd6acb 100644 --- a/soc/soc_legacy/riscv/microchip_miv/polarfire/Kconfig.defconfig.series +++ b/soc/microchip/miv/polarfire/Kconfig.defconfig @@ -3,9 +3,6 @@ if SOC_SERIES_POLARFIRE -config SOC_SERIES - default "polarfire" - # MPFS should be configured so that the mtimer clock is 1MHz independent of the CPU clock... config SYS_CLOCK_HW_CYCLES_PER_SEC diff --git a/soc/microchip/miv/polarfire/Kconfig.soc b/soc/microchip/miv/polarfire/Kconfig.soc new file mode 100644 index 00000000000..ce44e8b8ada --- /dev/null +++ b/soc/microchip/miv/polarfire/Kconfig.soc @@ -0,0 +1,22 @@ +# RISCV64_MIV Microchip Polarfire SOC configuration options + +# Copyright (c) 2020-2021 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_POLARFIRE + bool + select SOC_FAMILY_MICROCHIP_MIV + help + Microchip RV64 implementation + +config SOC_POLARFIRE + bool + select SOC_SERIES_POLARFIRE + help + Microchip MPFS system implementation + +config SOC_SERIES + default "polarfire" if SOC_SERIES_POLARFIRE + +config SOC + default "polarfire" if SOC_POLARFIRE diff --git a/soc/microchip/miv/soc.yml b/soc/microchip/miv/soc.yml new file mode 100644 index 00000000000..11f30cffc32 --- /dev/null +++ b/soc/microchip/miv/soc.yml @@ -0,0 +1,9 @@ +family: +- name: microchip_miv + series: + - name: miv + socs: + - name: miv + - name: polarfire + socs: + - name: polarfire diff --git a/soc/soc_legacy/riscv/microchip_miv/Kconfig b/soc/soc_legacy/riscv/microchip_miv/Kconfig deleted file mode 100644 index 350ade32aff..00000000000 --- a/soc/soc_legacy/riscv/microchip_miv/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_MICROCHIP_MIV - bool - -if SOC_FAMILY_MICROCHIP_MIV - -config SOC_FAMILY - string - default "microchip_miv" - -source "soc/soc_legacy/riscv/microchip_miv/*/Kconfig.soc" - -endif # SOC_FAMILY_MICROCHIP_MIV diff --git a/soc/soc_legacy/riscv/microchip_miv/Kconfig.soc b/soc/soc_legacy/riscv/microchip_miv/Kconfig.soc deleted file mode 100644 index 7e2aa4c18ab..00000000000 --- a/soc/soc_legacy/riscv/microchip_miv/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -source "soc/soc_legacy/riscv/microchip_miv/*/Kconfig.series" diff --git a/soc/soc_legacy/riscv/microchip_miv/miv/Kconfig.series b/soc/soc_legacy/riscv/microchip_miv/miv/Kconfig.series deleted file mode 100644 index 9f348619624..00000000000 --- a/soc/soc_legacy/riscv/microchip_miv/miv/Kconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# RISCV32_MIV implementation - -# Copyright (c) 2018 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_MIV - bool "Microchip Mi-V implementation" - select SOC_FAMILY_MICROCHIP_MIV - select RISCV - select RISCV_PRIVILEGED - select RISCV_HAS_PLIC - help - Enable support for Microchip Mi-V diff --git a/soc/soc_legacy/riscv/microchip_miv/polarfire/Kconfig.series b/soc/soc_legacy/riscv/microchip_miv/polarfire/Kconfig.series deleted file mode 100644 index 59ec4dbdd7a..00000000000 --- a/soc/soc_legacy/riscv/microchip_miv/polarfire/Kconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# RISCV64_MIV implementation - -# Copyright (c) 2018 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_POLARFIRE - bool "Microchip RV64 implementation" - select SOC_FAMILY_MICROCHIP_MIV - select RISCV - select RISCV_PRIVILEGED - select RISCV_HAS_PLIC - help - Enable support for Microchip RISCV 64bit