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boards: nxp: imx8qxp_mek: add esai0 default pin configuration 

Add pad definitions and the pin configuration for i.MX8QXP MEK's
ESAI0.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
pull/92069/head
Laurentiu Mihalcea 4 months ago committed by Benjamin Cabé
parent
d474f0a177
commit
4c8a2ac715
3 changed files with 83 additions and 3 deletions
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  1. 57
      boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp-pinctrl.dtsi
  2. 7
      boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.dts
  3. 22
      include/zephyr/dt-bindings/pinctrl/imx8qxp-pinctrl.h

57
boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp-pinctrl.dtsi
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@ -1,5 +1,5 @@ @@ -1,5 +1,5 @@
/*
* Copyright 2023 NXP
* Copyright 2023, 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -30,6 +30,46 @@ @@ -30,6 +30,46 @@
iomuxc_adma_sai1_txd_spi0_cs1: IOMUXC_ADMA_SAI1_TXD_SPI0_CS1 {
pinmux = <SC_P_SPI0_CS1 IMX8QXP_ADMA_SAI1_TXD_SPI0_CS1>;
};
iomuxc_adma_esai0_fsr_esai0_fsr: IOMUXC_ADMA_ESAI0_FSR_ESAI0_FSR {
pinmux = <SC_P_ESAI0_FSR IMX8QXP_ADMA_ESAI0_FSR_ESAI0_FSR>;
};
iomuxc_adma_esai0_fst_esai0_fst: IOMUXC_ADMA_ESAI0_FST_ESAI0_FST {
pinmux = <SC_P_ESAI0_FST IMX8QXP_ADMA_ESAI0_FST_ESAI0_FST>;
};
iomuxc_adma_esai0_sckr_esai0_sckr: IOMUXC_ADMA_ESAI0_SCKR_ESAI0_SCKR {
pinmux = <SC_P_ESAI0_SCKR IMX8QXP_ADMA_ESAI0_SCKR_ESAI0_SCKR>;
};
iomuxc_adma_esai0_sckt_esai0_sckt: IOMUXC_ADMA_ESAI0_SCKT_ESAI0_SCKT {
pinmux = <SC_P_ESAI0_SCKT IMX8QXP_ADMA_ESAI0_SCKT_ESAI0_SCKT>;
};
iomuxc_adma_esai0_tx0_esai0_tx0: IOMUXC_ADMA_ESAI0_TX0_ESAI0_TX0 {
pinmux = <SC_P_ESAI0_TX0 IMX8QXP_ADMA_ESAI0_TX0_ESAI0_TX0>;
};
iomuxc_adma_esai0_tx1_esai0_tx1: IOMUXC_ADMA_ESAI0_TX1_ESAI0_TX1 {
pinmux = <SC_P_ESAI0_TX1 IMX8QXP_ADMA_ESAI0_TX1_ESAI0_TX1>;
};
iomuxc_adma_esai0_tx2_rx3_esai0_tx2_rx3: IOMUXC_ADMA_ESAI0_TX2_RX3_ESAI0_TX2_RX3 {
pinmux = <SC_P_ESAI0_TX2_RX3 IMX8QXP_ADMA_ESAI0_TX2_RX3_ESAI0_TX2_RX3>;
};
iomuxc_adma_esai0_tx3_rx2_esai0_tx3_rx2: IOMUXC_ADMA_ESAI0_TX3_RX2_ESAI0_TX3_RX2 {
pinmux = <SC_P_ESAI0_TX3_RX2 IMX8QXP_ADMA_ESAI0_TX3_RX2_ESAI0_TX3_RX2>;
};
iomuxc_adma_esai0_tx4_rx1_esai0_tx4_rx1: IOMUXC_ADMA_ESAI0_TX4_RX1_ESAI0_TX4_RX1 {
pinmux = <SC_P_ESAI0_TX4_RX1 IMX8QXP_ADMA_ESAI0_TX4_RX1_ESAI0_TX4_RX1>;
};
iomuxc_adma_esai0_tx5_rx0_esai0_tx5_rx0: IOMUXC_ADMA_ESAI0_TX5_RX0_ESAI0_TX5_RX0 {
pinmux = <SC_P_ESAI0_TX5_RX0 IMX8QXP_ADMA_ESAI0_TX5_RX0_ESAI0_TX5_RX0>;
};
};
&pinctrl {
@ -48,4 +88,19 @@ @@ -48,4 +88,19 @@
<&iomuxc_adma_sai1_txd_spi0_cs1>;
};
};
esai0_default: esai0_default {
group0 {
pinmux = <&iomuxc_adma_esai0_fsr_esai0_fsr>,
<&iomuxc_adma_esai0_fst_esai0_fst>,
<&iomuxc_adma_esai0_sckr_esai0_sckr>,
<&iomuxc_adma_esai0_sckt_esai0_sckt>,
<&iomuxc_adma_esai0_tx0_esai0_tx0>,
<&iomuxc_adma_esai0_tx1_esai0_tx1>,
<&iomuxc_adma_esai0_tx2_rx3_esai0_tx2_rx3>,
<&iomuxc_adma_esai0_tx3_rx2_esai0_tx3_rx2>,
<&iomuxc_adma_esai0_tx4_rx1_esai0_tx4_rx1>,
<&iomuxc_adma_esai0_tx5_rx0_esai0_tx5_rx0>;
};
};
};

7
boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.dts
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@ -1,5 +1,5 @@ @@ -1,5 +1,5 @@
/*
* Copyright (c) 2021, 2024 NXP
* Copyright (c) 2021, 2024-2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -20,6 +20,11 @@ @@ -20,6 +20,11 @@
};
};
&esai0 {
pinctrl-0 = <&esai0_default>;
pinctrl-names = "default";
};
&lpuart2 {
status = "okay";
current-speed = <115200>;

22
include/zephyr/dt-bindings/pinctrl/imx8qxp-pinctrl.h
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@ -1,5 +1,5 @@ @@ -1,5 +1,5 @@
/*
* Copyright 2023 NXP
* Copyright 2023, 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -8,6 +8,16 @@ @@ -8,6 +8,16 @@
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IMX8QXP_PINCTRL_H_
/* values for pad field */
#define SC_P_ESAI0_FSR 55
#define SC_P_ESAI0_FST 56
#define SC_P_ESAI0_SCKR 57
#define SC_P_ESAI0_SCKT 58
#define SC_P_ESAI0_TX0 59
#define SC_P_ESAI0_TX1 60
#define SC_P_ESAI0_TX2_RX3 61
#define SC_P_ESAI0_TX3_RX2 62
#define SC_P_ESAI0_TX4_RX1 63
#define SC_P_ESAI0_TX5_RX0 64
#define SC_P_SAI1_RXD 86
#define SC_P_SAI1_RXC 87
#define SC_P_SAI1_RXFS 88
@ -22,5 +32,15 @@ @@ -22,5 +32,15 @@
#define IMX8QXP_ADMA_SAI1_RXD_SAI1_RXD 0 /* ADMA_SAI1_RXD <--- SAI1_RXD */
#define IMX8QXP_ADMA_SAI1_TXC_SAI1_RXC 1 /* ADMA_SAI1_TXC <---> SAI1_RXC */
#define IMX8QXP_ADMA_SAI1_TXD_SPI0_CS1 2 /* ADMA_SAI1_TXD ---> SPI0_CS1 */
#define IMX8QXP_ADMA_ESAI0_FSR_ESAI0_FSR 0
#define IMX8QXP_ADMA_ESAI0_FST_ESAI0_FST 0
#define IMX8QXP_ADMA_ESAI0_SCKR_ESAI0_SCKR 0
#define IMX8QXP_ADMA_ESAI0_SCKT_ESAI0_SCKT 0
#define IMX8QXP_ADMA_ESAI0_TX0_ESAI0_TX0 0
#define IMX8QXP_ADMA_ESAI0_TX1_ESAI0_TX1 0
#define IMX8QXP_ADMA_ESAI0_TX2_RX3_ESAI0_TX2_RX3 0
#define IMX8QXP_ADMA_ESAI0_TX3_RX2_ESAI0_TX3_RX2 0
#define IMX8QXP_ADMA_ESAI0_TX4_RX1_ESAI0_TX4_RX1 0
#define IMX8QXP_ADMA_ESAI0_TX5_RX0_ESAI0_TX5_RX0 0
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IMX8QXP_PINCTRL_H_ */

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