From 4c8a2ac7159b0716d405f8a1a20d78a42648d3bb Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Fri, 21 Mar 2025 11:36:25 +0200 Subject: [PATCH] boards: nxp: imx8qxp_mek: add esai0 default pin configuration Add pad definitions and the pin configuration for i.MX8QXP MEK's ESAI0. Signed-off-by: Laurentiu Mihalcea --- .../imx8qxp_mek_mimx8qx6_adsp-pinctrl.dtsi | 57 ++++++++++++++++++- .../imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.dts | 7 ++- .../dt-bindings/pinctrl/imx8qxp-pinctrl.h | 22 ++++++- 3 files changed, 83 insertions(+), 3 deletions(-) diff --git a/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp-pinctrl.dtsi b/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp-pinctrl.dtsi index 33ba2c5446c..de9b7e84840 100644 --- a/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp-pinctrl.dtsi +++ b/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp-pinctrl.dtsi @@ -1,5 +1,5 @@ /* - * Copyright 2023 NXP + * Copyright 2023, 2025 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -30,6 +30,46 @@ iomuxc_adma_sai1_txd_spi0_cs1: IOMUXC_ADMA_SAI1_TXD_SPI0_CS1 { pinmux = ; }; + + iomuxc_adma_esai0_fsr_esai0_fsr: IOMUXC_ADMA_ESAI0_FSR_ESAI0_FSR { + pinmux = ; + }; + + iomuxc_adma_esai0_fst_esai0_fst: IOMUXC_ADMA_ESAI0_FST_ESAI0_FST { + pinmux = ; + }; + + iomuxc_adma_esai0_sckr_esai0_sckr: IOMUXC_ADMA_ESAI0_SCKR_ESAI0_SCKR { + pinmux = ; + }; + + iomuxc_adma_esai0_sckt_esai0_sckt: IOMUXC_ADMA_ESAI0_SCKT_ESAI0_SCKT { + pinmux = ; + }; + + iomuxc_adma_esai0_tx0_esai0_tx0: IOMUXC_ADMA_ESAI0_TX0_ESAI0_TX0 { + pinmux = ; + }; + + iomuxc_adma_esai0_tx1_esai0_tx1: IOMUXC_ADMA_ESAI0_TX1_ESAI0_TX1 { + pinmux = ; + }; + + iomuxc_adma_esai0_tx2_rx3_esai0_tx2_rx3: IOMUXC_ADMA_ESAI0_TX2_RX3_ESAI0_TX2_RX3 { + pinmux = ; + }; + + iomuxc_adma_esai0_tx3_rx2_esai0_tx3_rx2: IOMUXC_ADMA_ESAI0_TX3_RX2_ESAI0_TX3_RX2 { + pinmux = ; + }; + + iomuxc_adma_esai0_tx4_rx1_esai0_tx4_rx1: IOMUXC_ADMA_ESAI0_TX4_RX1_ESAI0_TX4_RX1 { + pinmux = ; + }; + + iomuxc_adma_esai0_tx5_rx0_esai0_tx5_rx0: IOMUXC_ADMA_ESAI0_TX5_RX0_ESAI0_TX5_RX0 { + pinmux = ; + }; }; &pinctrl { @@ -48,4 +88,19 @@ <&iomuxc_adma_sai1_txd_spi0_cs1>; }; }; + + esai0_default: esai0_default { + group0 { + pinmux = <&iomuxc_adma_esai0_fsr_esai0_fsr>, + <&iomuxc_adma_esai0_fst_esai0_fst>, + <&iomuxc_adma_esai0_sckr_esai0_sckr>, + <&iomuxc_adma_esai0_sckt_esai0_sckt>, + <&iomuxc_adma_esai0_tx0_esai0_tx0>, + <&iomuxc_adma_esai0_tx1_esai0_tx1>, + <&iomuxc_adma_esai0_tx2_rx3_esai0_tx2_rx3>, + <&iomuxc_adma_esai0_tx3_rx2_esai0_tx3_rx2>, + <&iomuxc_adma_esai0_tx4_rx1_esai0_tx4_rx1>, + <&iomuxc_adma_esai0_tx5_rx0_esai0_tx5_rx0>; + }; + }; }; diff --git a/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.dts b/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.dts index 460ca19029c..d260715b23a 100644 --- a/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.dts +++ b/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, 2024 NXP + * Copyright (c) 2021, 2024-2025 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -20,6 +20,11 @@ }; }; +&esai0 { + pinctrl-0 = <&esai0_default>; + pinctrl-names = "default"; +}; + &lpuart2 { status = "okay"; current-speed = <115200>; diff --git a/include/zephyr/dt-bindings/pinctrl/imx8qxp-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/imx8qxp-pinctrl.h index da5f76b9da3..e20a321dab1 100644 --- a/include/zephyr/dt-bindings/pinctrl/imx8qxp-pinctrl.h +++ b/include/zephyr/dt-bindings/pinctrl/imx8qxp-pinctrl.h @@ -1,5 +1,5 @@ /* - * Copyright 2023 NXP + * Copyright 2023, 2025 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -8,6 +8,16 @@ #define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IMX8QXP_PINCTRL_H_ /* values for pad field */ +#define SC_P_ESAI0_FSR 55 +#define SC_P_ESAI0_FST 56 +#define SC_P_ESAI0_SCKR 57 +#define SC_P_ESAI0_SCKT 58 +#define SC_P_ESAI0_TX0 59 +#define SC_P_ESAI0_TX1 60 +#define SC_P_ESAI0_TX2_RX3 61 +#define SC_P_ESAI0_TX3_RX2 62 +#define SC_P_ESAI0_TX4_RX1 63 +#define SC_P_ESAI0_TX5_RX0 64 #define SC_P_SAI1_RXD 86 #define SC_P_SAI1_RXC 87 #define SC_P_SAI1_RXFS 88 @@ -22,5 +32,15 @@ #define IMX8QXP_ADMA_SAI1_RXD_SAI1_RXD 0 /* ADMA_SAI1_RXD <--- SAI1_RXD */ #define IMX8QXP_ADMA_SAI1_TXC_SAI1_RXC 1 /* ADMA_SAI1_TXC <---> SAI1_RXC */ #define IMX8QXP_ADMA_SAI1_TXD_SPI0_CS1 2 /* ADMA_SAI1_TXD ---> SPI0_CS1 */ +#define IMX8QXP_ADMA_ESAI0_FSR_ESAI0_FSR 0 +#define IMX8QXP_ADMA_ESAI0_FST_ESAI0_FST 0 +#define IMX8QXP_ADMA_ESAI0_SCKR_ESAI0_SCKR 0 +#define IMX8QXP_ADMA_ESAI0_SCKT_ESAI0_SCKT 0 +#define IMX8QXP_ADMA_ESAI0_TX0_ESAI0_TX0 0 +#define IMX8QXP_ADMA_ESAI0_TX1_ESAI0_TX1 0 +#define IMX8QXP_ADMA_ESAI0_TX2_RX3_ESAI0_TX2_RX3 0 +#define IMX8QXP_ADMA_ESAI0_TX3_RX2_ESAI0_TX3_RX2 0 +#define IMX8QXP_ADMA_ESAI0_TX4_RX1_ESAI0_TX4_RX1 0 +#define IMX8QXP_ADMA_ESAI0_TX5_RX0_ESAI0_TX5_RX0 0 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IMX8QXP_PINCTRL_H_ */